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Port the NetBSD esp(4) driver. This only includes the sbus front-end, so

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its primary use is for the FEPS/FAS366 SCSI found in Sun Ultra 1e and 2
machines.  Once the pci front-end is ported, this driver can replace the
amd(4) driver.

The code as-is is fairly stable.  I've disabled tagged-queueing until I can
figure out a corruption bug related to it.  I'm importing it now so that
people with these machines can (finally) stop netbooting and report bugs
before 5.3.
This commit is contained in:
Scott Long 2004-06-10 05:11:39 +00:00
parent b8fae4f3ef
commit c31d0cf77b
11 changed files with 6363 additions and 0 deletions
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581
sys/dev/esp/esp_sbus.c Normal file
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/*-
* Copyright (c) 2004 Scott Long
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/* $NetBSD: esp_sbus.c,v 1.27 2002/12/10 13:44:47 pk Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace
* Simulation Facility, NASA Ames Research Center; Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/resource.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <dev/ofw/openfirm.h>
#include <machine/ofw_machdep.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <sparc64/sbus/sbusvar.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/scsi/scsi_all.h>
#include <dev/esp/lsi64854reg.h>
#include <dev/esp/lsi64854var.h>
#include <dev/esp/ncr53c9xreg.h>
#include <dev/esp/ncr53c9xvar.h>
/* #define ESP_SBUS_DEBUG */
struct esp_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
struct device *sc_dev;
int sc_rid;
struct resource *sc_res;
bus_space_handle_t sc_regh;
bus_space_tag_t sc_regt;
int sc_irqrid;
struct resource *sc_irqres;
void *sc_irq;
struct lsi64854_softc *sc_dma; /* pointer to my dma */
int sc_pri; /* SBUS priority */
};
static int esp_sbus_probe(device_t);
static int esp_sbus_attach(device_t);
static int esp_sbus_detach(device_t);
static int esp_sbus_suspend(device_t);
static int esp_sbus_resume(device_t);
static device_method_t esp_sbus_methods[] = {
DEVMETHOD(device_probe, esp_sbus_probe),
DEVMETHOD(device_attach, esp_sbus_attach),
DEVMETHOD(device_detach, esp_sbus_detach),
DEVMETHOD(device_suspend, esp_sbus_suspend),
DEVMETHOD(device_resume, esp_sbus_resume),
{0, 0}
};
static driver_t esp_sbus_driver = {
"esp",
esp_sbus_methods,
sizeof(struct esp_softc)
};
static devclass_t esp_devclass;
DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0);
/*
* Functions and the switch for the MI code.
*/
static u_char esp_read_reg(struct ncr53c9x_softc *, int);
static void esp_write_reg(struct ncr53c9x_softc *, int, u_char);
static int esp_dma_isintr(struct ncr53c9x_softc *);
static void esp_dma_reset(struct ncr53c9x_softc *);
static int esp_dma_intr(struct ncr53c9x_softc *);
static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *,
int, size_t *);
static void esp_dma_go(struct ncr53c9x_softc *);
static void esp_dma_stop(struct ncr53c9x_softc *);
static int esp_dma_isactive(struct ncr53c9x_softc *);
static void espattach(struct esp_softc *, struct ncr53c9x_glue *);
static struct ncr53c9x_glue esp_sbus_glue = {
esp_read_reg,
esp_write_reg,
esp_dma_isintr,
esp_dma_reset,
esp_dma_intr,
esp_dma_setup,
esp_dma_go,
esp_dma_stop,
esp_dma_isactive,
NULL, /* gl_clear_latched_intr */
};
static int
esp_sbus_probe(device_t dev)
{
char *name;
name = sbus_get_name(dev);
if (strcmp("SUNW,fas", name) == 0) {
device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI");
return (-10);
}
return (ENXIO);
}
static int
esp_sbus_attach(device_t dev)
{
struct esp_softc *esc = device_get_softc(dev);
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
struct lsi64854_softc *lsc;
phandle_t node;
int burst;
esc->sc_dev = dev;
node = sbus_get_node(dev);
if (OF_getprop(node, "initiator-id", &sc->sc_id,
sizeof(sc->sc_id)) == -1)
sc->sc_id = 7;;
sc->sc_freq = sbus_get_clockfreq(dev);
#ifdef ESP_SBUS_DEBUG
device_printf(dev, "espattach_sbus: sc_id %d, freq %d\n",
sc->sc_id, sc->sc_freq);
#endif
/*
* allocate space for dma, in SUNW,fas there are no separate
* dma device
*/
lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
if (lsc == NULL) {
device_printf(dev, "out of memory (lsi64854_softc)\n");
return (ENOMEM);
}
esc->sc_dma = lsc;
/*
* fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x)
*/
/* Map dma registers */
lsc->sc_rid = 0;
if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&lsc->sc_rid, RF_ACTIVE)) == NULL) {
device_printf(dev, "cannot map dma registers\n");
free(lsc, M_DEVBUF);
return (ENXIO);
}
lsc->sc_regt = rman_get_bustag(lsc->sc_res);
lsc->sc_regh = rman_get_bushandle(lsc->sc_res);
/* Create a parent DMA tag based on this bus */
if (bus_dma_tag_create(NULL, /* parent */
PAGE_SIZE, 0, /* algnmnt, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
0, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
0, /* flags */
NULL, NULL, /* No locking */
&lsc->sc_parent_dmat)) {
device_printf(dev, "cannot allocate parent DMA tag\n");
free(lsc, M_DEVBUF);
return (ENOMEM);
}
burst = sbus_get_burstsz(dev);
#ifdef ESP_SBUS_DEBUG
printf("espattach_sbus: burst 0x%x\n", burst);
#endif
lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 :
(burst & SBUS_BURST_16) ? 16 : 0;
lsc->sc_channel = L64854_CHANNEL_SCSI;
lsc->sc_client = sc;
lsc->sc_dev = dev;
lsi64854_attach(lsc);
/*
* map SCSI core registers
*/
esc->sc_rid = 1;
if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&esc->sc_rid, RF_ACTIVE)) == NULL) {
device_printf(dev, "cannot map scsi core registers\n");
free(lsc, M_DEVBUF);
return (ENXIO);
}
esc->sc_regt = rman_get_bustag(esc->sc_res);
esc->sc_regh = rman_get_bushandle(esc->sc_res);
#if 0
esc->sc_pri = sa->sa_pri;
/* add me to the sbus structures */
esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
sbus_establish(&esc->sc_sd, &sc->sc_dev);
#endif
espattach(esc, &esp_sbus_glue);
return (0);
}
static int
esp_sbus_detach(device_t dev)
{
struct ncr53c9x_softc *sc;
struct esp_softc *esc;
esc = device_get_softc(dev);
sc = &esc->sc_ncr53c9x;
return (ncr53c9x_detach(sc, 0));
}
static int
esp_sbus_suspend(device_t dev)
{
return (ENXIO);
}
static int
esp_sbus_resume(device_t dev)
{
return (ENXIO);
}
/*
* Attach this instance, and then all the sub-devices
*/
void
espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
{
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
unsigned int uid = 0;
/*
* Set up glue for MI code early; we use some of it here.
*/
sc->sc_glue = gluep;
/* gimme MHz */
sc->sc_freq /= 1000000;
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the esp chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
sc->sc_cfg3 = NCRCFG3_CDB;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
sc->sc_rev = NCR_VARIANT_ESP100;
} else {
sc->sc_cfg2 = NCRCFG2_SCSI2;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
sc->sc_cfg3 = 0;
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
if (NCR_READ_REG(sc, NCR_CFG3) !=
(NCRCFG3_CDB | NCRCFG3_FCLK)) {
sc->sc_rev = NCR_VARIANT_ESP100A;
} else {
/* NCRCFG2_FE enables > 64K transfers */
sc->sc_cfg2 |= NCRCFG2_FE;
sc->sc_cfg3 = 0;
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
sc->sc_rev = NCR_VARIANT_ESP200;
/* XXX spec says it's valid after power up or chip reset */
uid = NCR_READ_REG(sc, NCR_UID);
if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */
sc->sc_rev = NCR_VARIANT_FAS366;
}
}
#ifdef ESP_SBUS_DEBUG
printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid);
#endif
/*
* XXX minsync and maxxfer _should_ be set up in MI code,
* XXX but it appears to have some dependency on what sort
* XXX of DMA we're hooked up to, etc.
*/
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
/* limit minsync due to unsolved performance issues */
sc->sc_maxsync = sc->sc_minsync;
sc->sc_maxoffset = 15;
/*
* Alas, we must now modify the value a bit, because it's
* only valid when can switch on FASTCLK and FASTSCSI bits
* in config register 3...
*/
switch (sc->sc_rev) {
case NCR_VARIANT_ESP100:
sc->sc_maxwidth = 0;
sc->sc_maxxfer = 64 * 1024;
sc->sc_minsync = 0; /* No synch on old chip? */
break;
case NCR_VARIANT_ESP100A:
sc->sc_maxwidth = 1;
sc->sc_maxxfer = 64 * 1024;
/* Min clocks/byte is 5 */
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
break;
case NCR_VARIANT_ESP200:
case NCR_VARIANT_FAS366:
sc->sc_maxwidth = 1;
sc->sc_maxxfer = 16 * 1024 * 1024;
/* XXX - do actually set FAST* bits */
break;
}
/* Establish interrupt channel */
esc->sc_irqrid = 0;
if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
&esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
device_printf(esc->sc_dev, "Cannot allocate interrupt\n");
return;
}
if (bus_setup_intr(esc->sc_dev, esc->sc_irqres,
INTR_TYPE_BIO|INTR_ENTROPY, ncr53c9x_intr, sc, &esc->sc_irq)) {
device_printf(esc->sc_dev, "Cannot set up interrupt\n");
return;
}
/* Turn on target selection using the `dma' method */
if (sc->sc_rev != NCR_VARIANT_FAS366)
sc->sc_features |= NCR_F_DMASELECT;
/* Do the common parts of attachment. */
sc->sc_dev = esc->sc_dev;
ncr53c9x_attach(sc);
}
/*
* Glue functions.
*/
#ifdef ESP_SBUS_DEBUG
int esp_sbus_debug = 0;
static struct {
char *r_name;
int r_flag;
} esp__read_regnames [] = {
{ "TCL", 0}, /* 0/00 */
{ "TCM", 0}, /* 1/04 */
{ "FIFO", 0}, /* 2/08 */
{ "CMD", 0}, /* 3/0c */
{ "STAT", 0}, /* 4/10 */
{ "INTR", 0}, /* 5/14 */
{ "STEP", 0}, /* 6/18 */
{ "FFLAGS", 1}, /* 7/1c */
{ "CFG1", 1}, /* 8/20 */
{ "STAT2", 0}, /* 9/24 */
{ "CFG4", 1}, /* a/28 */
{ "CFG2", 1}, /* b/2c */
{ "CFG3", 1}, /* c/30 */
{ "-none", 1}, /* d/34 */
{ "TCH", 1}, /* e/38 */
{ "TCX", 1}, /* f/3c */
};
static struct {
char *r_name;
int r_flag;
} esp__write_regnames[] = {
{ "TCL", 1}, /* 0/00 */
{ "TCM", 1}, /* 1/04 */
{ "FIFO", 0}, /* 2/08 */
{ "CMD", 0}, /* 3/0c */
{ "SELID", 1}, /* 4/10 */
{ "TIMEOUT", 1}, /* 5/14 */
{ "SYNCTP", 1}, /* 6/18 */
{ "SYNCOFF", 1}, /* 7/1c */
{ "CFG1", 1}, /* 8/20 */
{ "CCF", 1}, /* 9/24 */
{ "TEST", 1}, /* a/28 */
{ "CFG2", 1}, /* b/2c */
{ "CFG3", 1}, /* c/30 */
{ "-none", 1}, /* d/34 */
{ "TCH", 1}, /* e/38 */
{ "TCX", 1}, /* f/3c */
};
#endif
u_char
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
{
struct esp_softc *esc = (struct esp_softc *)sc;
u_char v;
v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4);
#ifdef ESP_SBUS_DEBUG
if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
printf("RD:%x <%s> %x\n", reg * 4,
((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v);
#endif
return v;
}
void
esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
{
struct esp_softc *esc = (struct esp_softc *)sc;
#ifdef ESP_SBUS_DEBUG
if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
printf("WR:%x <%s> %x\n", reg * 4,
((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v);
#endif
bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v);
}
int
esp_dma_isintr(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_ISINTR(esc->sc_dma));
}
void
esp_dma_reset(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
DMA_RESET(esc->sc_dma);
}
int
esp_dma_intr(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_INTR(esc->sc_dma));
}
int
esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize));
}
void
esp_dma_go(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
DMA_GO(esc->sc_dma);
}
void
esp_dma_stop(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
u_int32_t csr;
csr = L64854_GCSR(esc->sc_dma);
csr &= ~D_EN_DMA;
L64854_SCSR(esc->sc_dma, csr);
}
int
esp_dma_isactive(struct ncr53c9x_softc *sc)
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_ISACTIVE(esc->sc_dma));
}

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sys/dev/esp/lsi64854.c Normal file
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/*-
* Copyright (c) 2004 Scott Long
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/* $NetBSD: lsi64854.c,v 1.22 2002/10/01 07:07:03 petrov Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/resource.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/scsi/scsi_all.h>
#include <dev/esp/lsi64854reg.h>
#include <dev/esp/lsi64854var.h>
#include <dev/esp/ncr53c9xreg.h>
#include <dev/esp/ncr53c9xvar.h>
void lsi64854_reset(struct lsi64854_softc *);
int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *);
int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *);
#ifdef DEBUG
#define LDB_SCSI 1
#define LDB_ENET 2
#define LDB_PP 4
#define LDB_ANY 0xff
int lsi64854debug = 0;
#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
#else
#define DPRINTF(a,x)
#endif
#define MAX_DMA_SZ (16*1024*1024)
/*
* Finish attaching this DMA device.
* Front-end must fill in these fields:
* sc_regs
* sc_burst
* sc_channel (one of SCSI, ENET, PP)
* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
*/
void
lsi64854_attach(struct lsi64854_softc *sc)
{
u_int32_t csr;
sc->dv_name = device_get_nameunit(sc->sc_dev);
/* Indirect functions */
switch (sc->sc_channel) {
case L64854_CHANNEL_SCSI:
sc->intr = lsi64854_scsi_intr;
sc->setup = lsi64854_setup;
break;
case L64854_CHANNEL_ENET:
sc->intr = lsi64854_enet_intr;
break;
case L64854_CHANNEL_PP:
sc->setup = lsi64854_setup_pp;
break;
default:
printf("%s: unknown channel\n", sc->dv_name);
}
sc->reset = lsi64854_reset;
/* Allocate a dmamap */
if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */
1, 0, /* algnment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAX_DMA_SZ, /* maxsize */
1, /* nsegments */
MAX_DMA_SZ, /* maxsegsize */
BUS_DMA_ALLOCNOW, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->sc_buffer_dmat)) {
printf("%s: can't allocate buffer DMA tag\n", sc->dv_name);
return;
}
if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) {
printf("%s: DMA map create failed\n", sc->dv_name);
return;
}
csr = L64854_GCSR(sc);
sc->sc_rev = csr & L64854_DEVID;
if (sc->sc_rev == DMAREV_HME) {
return;
}
printf(": DMA rev ");
switch (sc->sc_rev) {
case DMAREV_0:
printf("0");
break;
case DMAREV_ESC:
printf("esc");
break;
case DMAREV_1:
printf("1");
break;
case DMAREV_PLUS:
printf("1+");
break;
case DMAREV_2:
printf("2");
break;
default:
printf("unknown (0x%x)", sc->sc_rev);
}
DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
printf("\n");
}
/*
* DMAWAIT waits while condition is true
*/
#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
int count = 500000; \
while ((COND) && --count > 0) DELAY(1); \
if (count == 0) { \
printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
(u_long)L64854_GCSR(SC)); \
if (DONTPANIC) \
printf(MSG); \
else \
panic(MSG); \
} \
} while (0)
#define DMA_DRAIN(sc, dontpanic) do { \
u_int32_t csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_ESC_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
if (sc->sc_rev != DMAREV_HME) { \
/* \
* Select drain bit based on revision \
* also clears errors and D_TC flag \
*/ \
csr = L64854_GCSR(sc); \
if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
csr |= D_ESC_DRAIN; \
else \
csr |= L64854_INVALIDATE; \
\
L64854_SCSR(sc,csr); \
} \
/* \
* Wait for draining to finish \
* rev0 & rev1 call this PACKCNT \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
} while(0)
#define DMA_FLUSH(sc, dontpanic) do { \
u_int32_t csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_ESC_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
csr = L64854_GCSR(sc); \
csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
L64854_SCSR(sc,csr); \
} while(0)
void
lsi64854_reset(struct lsi64854_softc *sc)
{
u_int32_t csr;
DMA_FLUSH(sc, 1);
csr = L64854_GCSR(sc);
DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
/*
* XXX is sync needed?
if (sc->sc_dmamap->dm_nsegs > 0)
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
*/
if (sc->sc_rev == DMAREV_HME)
L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
csr |= L64854_RESET; /* reset DMA */
L64854_SCSR(sc, csr);
DELAY(200); /* > 10 Sbus clocks(?) */
/*DMAWAIT1(sc); why was this here? */
csr = L64854_GCSR(sc);
csr &= ~L64854_RESET; /* de-assert reset line */
L64854_SCSR(sc, csr);
DELAY(5); /* allow a few ticks to settle */
csr = L64854_GCSR(sc);
csr |= L64854_INT_EN; /* enable interrupts */
if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
if (sc->sc_rev == DMAREV_HME)
csr |= D_TWO_CYCLE;
else
csr |= D_FASTER;
}
/* Set burst */
switch (sc->sc_rev) {
case DMAREV_HME:
case DMAREV_2:
csr &= ~L64854_BURST_SIZE;
if (sc->sc_burst == 32) {
csr |= L64854_BURST_32;
} else if (sc->sc_burst == 16) {
csr |= L64854_BURST_16;
} else {
csr |= L64854_BURST_0;
}
break;
case DMAREV_ESC:
csr |= D_ESC_AUTODRAIN; /* Auto-drain */
if (sc->sc_burst == 32) {
csr &= ~D_ESC_BURST;
} else
csr |= D_ESC_BURST;
break;
default:
break;
}
L64854_SCSR(sc, csr);
if (sc->sc_rev == DMAREV_HME) {
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0);
sc->sc_dmactl = csr;
}
sc->sc_active = 0;
DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
}
static void
lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
struct lsi64854_softc *sc;
sc = (struct lsi64854_softc *)arg;
if (nseg != 1)
panic("%s: cannot map %d segments\n", sc->dv_name, nseg);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
segs[0].ds_addr);
}
#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
/*
* setup a DMA transfer
*/
int
lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
u_int32_t csr;
DMA_FLUSH(sc, 0);
#if 0
DMACSR(sc) &= ~D_INT_EN;
#endif
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
sc->sc_datain = datain;
/*
* the rules say we cannot transfer more than the limit
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
/*
* XXX what length?
*/
if (sc->sc_rev == DMAREV_HME) {
L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
L64854_SCSR(sc, sc->sc_dmactl);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, *dmasize);
}
/* Program the DMA address */
if (sc->sc_dmasize) {
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
lsi64854_map_scsi, sc, 0) != 0)
panic("%s: cannot allocate DVMA address", sc->dv_name);
}
if (sc->sc_rev == DMAREV_ESC) {
/* DMA ESC chip bug work-around */
long bcnt = sc->sc_dmasize;
long eaddr = bcnt + (long)*sc->sc_dmaaddr;
if ((eaddr & PAGE_MASK_8K) != 0)
bcnt = roundup(bcnt, PAGE_SIZE_8K);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
bcnt);
}
/* Setup DMA control register */
csr = L64854_GCSR(sc);
if (datain)
csr |= L64854_WRITE;
else
csr &= ~L64854_WRITE;
csr |= L64854_INT_EN;
if (sc->sc_rev == DMAREV_HME) {
csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
}
L64854_SCSR(sc, csr);
return (0);
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. Called from ncr53c9x_intr()
* for now.
*
* return 1 if it was a DMA continue.
*/
int
lsi64854_scsi_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client;
int trans, resid;
u_int32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
csr, DDMACSR_BITS));
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS);
csr &= ~D_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE|D_SLAVE_ERR;
L64854_SCSR(sc, csr);
return (-1);
}
/* This is an "assertion" :) */
if (sc->sc_active == 0)
panic("dmaintr: DMA wasn't active");
DMA_DRAIN(sc, 0);
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the NCR53C9X counter registers get decremented
* as bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid));
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
resid <<= 1;
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the NCR53C9X counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE)
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
: 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n", sc->dv_name, trans,
sc->sc_dmasize);
#endif
trans = sc->sc_dmasize;
}
DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE)
? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
#endif
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 ||
nsc->sc_phase != nsc->sc_prevphase)
return 0;
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return 1;
#endif
return 0;
}
/*
* Pseudo (chained) interrupt to le driver to handle DMA errors.
*/
int
lsi64854_enet_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
u_int32_t csr;
static int dodrain = 0;
int rv;
csr = L64854_GCSR(sc);
/* If the DMA logic shows an interrupt, claim it */
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS);
csr &= ~L64854_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= E_INVALIDATE|E_SLAVE_ERR;
L64854_SCSR(sc, csr);
DMA_RESET(sc);
dodrain = 1;
return (1);
}
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
int i = 10;
csr |= E_DRAIN;
L64854_SCSR(sc, csr);
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
DELAY(1);
}
return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
}
static void
lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
struct lsi64854_softc *sc;
sc = (struct lsi64854_softc *)arg;
if (nsegs != 1)
panic("%s: cannot map %d segments\n", sc->dv_name, nsegs);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain
? BUS_DMASYNC_PREREAD
: BUS_DMASYNC_PREWRITE);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
segs[0].ds_addr);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
sc->sc_dmasize);
}
/*
* setup a DMA transfer
*/
int
lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
u_int32_t csr;
DMA_FLUSH(sc, 0);
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
sc->sc_datain = datain;
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name,
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
/*
* the rules say we cannot transfer more than the limit
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize));
/* Program the DMA address */
if (sc->sc_dmasize) {
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
lsi64854_map_pp, sc, 0) != 0)
panic("%s: pp cannot allocate DVMA address",
sc->dv_name);
}
/* Setup DMA control register */
csr = L64854_GCSR(sc);
csr &= ~L64854_BURST_SIZE;
if (sc->sc_burst == 32) {
csr |= L64854_BURST_32;
} else if (sc->sc_burst == 16) {
csr |= L64854_BURST_16;
} else {
csr |= L64854_BURST_0;
}
csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
#if 0
/* This bit is read-only in PP csr register */
if (datain)
csr |= P_WRITE;
else
csr &= ~P_WRITE;
#endif
L64854_SCSR(sc, csr);
return (0);
}
/*
* Parallel port DMA interrupt.
*/
int
lsi64854_pp_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
int ret, trans, resid = 0;
u_int32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
csr, PDMACSR_BITS));
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
L64854_REG_CNT);
printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid,
csr, PDMACSR_BITS);
csr &= ~P_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= P_INVALIDATE|P_SLAVE_ERR;
L64854_SCSR(sc, csr);
return (1);
}
ret = (csr & P_INT_PEND) != 0;
if (sc->sc_active != 0) {
DMA_DRAIN(sc, 0);
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
L64854_REG_CNT);
}
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
trans = sc->sc_dmasize;
}
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
#endif
return (ret != 0);
}

205
sys/dev/esp/lsi64854reg.h Normal file
View File

@ -0,0 +1,205 @@
/* $NetBSD: lsi64854reg.h,v 1.4 1998/09/21 21:26:52 pk Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
/*
* LSI 64854 DMA engine. Contains three independent channels
* designed to interface with (a) a NCR539X SCSI controller,
* (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
*/
/*
* Register offsets to bus handle.
*/
#define L64854_REG_CSR 0 /* Control bits */
#define L64854_REG_ADDR 4 /* DMA Address */
#define L64854_REG_CNT 8 /* DMA count */
#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */
#define L64854_REG_ENBAR 12 /* ENET Base register */
#define L64854_REG_TEST 12 /* SCSI Test register */
#define L64854_REG_HCR 16 /* PP Hardware Configuration */
#define L64854_REG_OCR 18 /* PP Operation Configuration */
#define L64854_REG_DR 20 /* PP Data register */
#define L64854_REG_TCR 21 /* PP Transfer Control */
#define L64854_REG_OR 22 /* PP Output register */
#define L64854_REG_IR 23 /* PP Input register */
#define L64854_REG_ICR 24 /* PP Interrupt Control */
/*
* Control bits common to all three channels.
*/
#define L64854_INT_PEND 0x00000001 /* Interrupt pending */
#define L64854_ERR_PEND 0x00000002 /* Error pending */
#define L64854_DRAINING 0x0000000c /* FIFO draining */
#define L64854_INT_EN 0x00000010 /* Interrupt enable */
#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */
#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */
#define L64854_RESET 0x00000080 /* Reset device */
#define L64854_WRITE 0x00000100 /* 1: xfer to memory */
#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */
#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */
#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */
#define L64854_BURST_16 0x00000000 /* 16-byte bursts */
#define L64854_BURST_32 0x00040000 /* 32-byte bursts */
#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */
#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */
#define L64854_DEVID 0xf0000000 /* device ID bits */
/*
* SCSI DMA control bits.
*/
#define D_INT_PEND L64854_INT_PEND /* interrupt pending */
#define D_ERR_PEND L64854_ERR_PEND /* error pending */
#define D_DRAINING L64854_DRAINING /* fifo draining */
#define D_INT_EN L64854_INT_EN /* interrupt enable */
#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define D_RESET L64854_RESET /* reset scsi */
#define D_WRITE L64854_WRITE /* 1 = dev -> mem */
#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */
#define D_EN_CNT 0x00002000 /* enable byte counter */
#define D_TC 0x00004000 /* terminal count */
#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */
#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
#define D_DIAG 0x00100000 /* disable fifo drain on addr */
#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
#define D_FASTER 0x00400000 /* 3 clocks per transfer */
#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
#define D_EN_NEXT 0x01000000 /* enable auto next address */
#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */
#define D_DSBL_PARITY_CHK \
0x02000000 /* disable checking for parity on bus (default 1:fas) */
#define D_A_LOADED 0x04000000 /* address loaded */
#define D_NA_LOADED 0x08000000 /* next address loaded */
#define D_HW_RESET_FAS366 \
0x08000000 /* hardware reset FAS366 (fas) */
#define D_DEV_ID L64854_DEVID /* device ID */
#define DMAREV_0 0x00000000 /* Sunray DMA */
#define DMAREV_ESC 0x40000000 /* DMA ESC array */
#define DMAREV_1 0x80000000 /* 'DMA' */
#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
#define DMAREV_2 0xa0000000 /* 'DMA2' */
#define DMAREV_HME 0xb0000000 /* 'HME' */
/*
* revisions 0,1 and ESC have different bits.
*/
#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */
#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
#define DDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
"b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \
"b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \
"b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \
"b\32ALOADED\0b\33NALOADED\0"
/*
* ENET DMA control bits.
*/
#define E_INT_PEND L64854_INT_PEND /* interrupt pending */
#define E_ERR_PEND L64854_ERR_PEND /* error pending */
#define E_DRAINING L64854_DRAINING /* fifo draining */
#define E_INT_EN L64854_INT_EN /* interrupt enable */
#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define E_RESET L64854_RESET /* reset ENET */
#define E_reserved1 0x00000300 /* */
#define E_DRAIN 0x00000400 /* force Ecache drain */
#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */
#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */
#define E_reserved2 0x00006000 /* */
#define E_ILACC 0x00008000 /* ... */
#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */
#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */
#define E_reserved3 0x00100000 /* */
#define E_LOOP_TEST 0x00200000 /* loopback mode */
#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */
#define E_reserved4 0x0c800000 /* */
#define E_DEV_ID L64854_DEVID /* ID bits */
#define EDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \
"b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \
"b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \
"b\25LOOPTEST\0b\26TP\0"
/*
* PP DMA control bits.
*/
#define P_INT_PEND L64854_INT_PEND /* interrupt pending */
#define P_ERR_PEND L64854_ERR_PEND /* error pending */
#define P_DRAINING L64854_DRAINING /* fifo draining */
#define P_INT_EN L64854_INT_EN /* interrupt enable */
#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define P_RESET L64854_RESET /* reset PP */
#define P_WRITE L64854_WRITE /* 1: xfer to memory */
#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */
#define P_reserved1 0x00001c00 /* */
#define P_EN_CNT 0x00002000 /* enable counter */
#define P_TC 0x00004000 /* terminal count */
#define P_reserved2 0x00038000 /* */
#define P_DIAG 0x00100000 /* ... */
#define P_reserved3 0x00600000 /* */
#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */
#define P_EN_NEXT 0x01000000 /* enable DMA chaining */
#define P_DMA_ON 0x02000000 /* DMA xfers enabled */
#define P_A_LOADED 0x04000000 /* addr and byte count valid */
#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */
#define P_DEV_ID L64854_DEVID /* ID bits */
#define PDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
"b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \
"b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0"

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/* $NetBSD: lsi64854var.h,v 1.4 2001/03/29 02:58:39 petrov Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
struct lsi64854_softc {
device_t sc_dev;
const char *dv_name;
int sc_rid;
struct resource *sc_res;
bus_space_handle_t sc_regh;
bus_space_tag_t sc_regt;
u_int sc_rev; /* revision */
int sc_burst; /* max suported burst size */
int sc_channel;
#define L64854_CHANNEL_SCSI 1
#define L64854_CHANNEL_ENET 2
#define L64854_CHANNEL_PP 3
void *sc_client;
int sc_active; /* DMA active ? */
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
bus_dma_tag_t sc_parent_dmat;
bus_dma_tag_t sc_buffer_dmat;
int sc_datain;
size_t sc_dmasize;
caddr_t *sc_dmaaddr;
size_t *sc_dmalen;
void (*reset)(struct lsi64854_softc *);/* reset routine */
int (*setup)(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *); /* DMA setup */
int (*intr)(void *); /* interrupt handler */
int (*sc_intrchain)(void *); /* next handler in intr chain */
void *sc_intrchainarg; /* arg for next intr handler */
u_int sc_dmactl;
};
#define L64854_GCSR(sc) \
(bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR))
#define L64854_SCSR(sc, csr) \
bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR, csr)
/*
* DMA engine interface functions.
*/
#define DMA_RESET(sc) (((sc)->reset)(sc))
#define DMA_INTR(sc) (((sc)->intr)(sc))
#define DMA_SETUP(sc, a, l, d, s) (((sc)->setup)(sc, a, l, d, s))
#define DMA_ISACTIVE(sc) ((sc)->sc_active)
#define DMA_ENINTR(sc) do { \
u_int32_t csr = L64854_GCSR(sc); \
csr |= L64854_INT_EN; \
L64854_SCSR(sc, csr); \
} while (0)
#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
#define DMA_GO(sc) do { \
u_int32_t csr = L64854_GCSR(sc); \
csr |= D_EN_DMA; \
L64854_SCSR(sc, csr); \
sc->sc_active = 1; \
} while (0)
void lsi64854_attach(struct lsi64854_softc *);
int lsi64854_scsi_intr(void *);
int lsi64854_enet_intr(void *);
int lsi64854_pp_intr(void *);

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/* $NetBSD: ncr53c9xreg.h,v 1.11 2003/02/21 17:14:05 tsutsui Exp $ */
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
/*
* Register addresses, relative to some base address
*/
#define NCR_TCL 0x00 /* RW - Transfer Count Low */
#define NCR_TCM 0x01 /* RW - Transfer Count Mid */
#define NCR_TCH 0x0e /* RW - Transfer Count High */
/* NOT on 53C90 */
#define NCR_FIFO 0x02 /* RW - FIFO data */
#define NCR_CMD 0x03 /* RW - Command (2 deep) */
#define NCRCMD_DMA 0x80 /* DMA Bit */
#define NCRCMD_NOP 0x00 /* No Operation */
#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
#define NCRCMD_RESEL 0x40 /* Reselect Sequence */
#define NCRCMD_SELNATN 0x41 /* Select without ATN */
#define NCRCMD_SELATN 0x42 /* Select with ATN */
#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
#define NCRCMD_SNDMSG 0x20 /* Send Message */
#define NCRCMD_SNDSTAT 0x21 /* Send Status */
#define NCRCMD_SNDDATA 0x22 /* Send Data */
#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
#define NCRCMD_DISC 0x27 /* Disconnect */
#define NCRCMD_RECMSG 0x28 /* Receive Message */
#define NCRCMD_RECCMD 0x29 /* Receive Command */
#define NCRCMD_RECDATA 0x2a /* Receive Data */
#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
#define NCRCMD_ABORT 0x04 /* Target Abort DMA */
#define NCRCMD_TRANS 0x10 /* Transfer Information */
#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
#define NCRCMD_MSGOK 0x12 /* Message Accepted */
#define NCRCMD_TRPAD 0x18 /* Transfer Pad */
#define NCRCMD_SETATN 0x1a /* Set ATN */
#define NCRCMD_RSTATN 0x1b /* Reset ATN */
#define NCR_STAT 0x04 /* RO - Status */
#define NCRSTAT_INT 0x80 /* Interrupt */
#define NCRSTAT_GE 0x40 /* Gross Error */
#define NCRSTAT_PE 0x20 /* Parity Error */
#define NCRSTAT_TC 0x10 /* Terminal Count */
#define NCRSTAT_VGC 0x08 /* Valid Group Code */
#define NCRSTAT_PHASE 0x07 /* Phase bits */
#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
#define NCR_BUSID_HME 0x10 /* XXX HME reselect ID */
#define NCR_BUSID_HME32 0x40 /* XXX HME to select more than 16 */
#define NCR_INTR 0x05 /* RO - Interrupt */
#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
#define NCRINTR_ILL 0x40 /* Illegal Command */
#define NCRINTR_DIS 0x20 /* Disconnect */
#define NCRINTR_BS 0x10 /* Bus Service */
#define NCRINTR_FC 0x08 /* Function Complete */
#define NCRINTR_RESEL 0x04 /* Reselected */
#define NCRINTR_SELATN 0x02 /* Select with ATN */
#define NCRINTR_SEL 0x01 /* Selected */
#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
#define NCR_STEP 0x06 /* RO - Sequence Step */
#define NCRSTEP_MASK 0x07 /* the last 3 bits */
#define NCRSTEP_DONE 0x04 /* command went out */
#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
/* Default 5 (53C9X) */
#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
#define NCR_SYNCOFF 0x07 /* WO - Synch Offset */
/* 0 = ASYNC */
/* 1 - 15 = SYNC bytes */
#define NCR_CFG1 0x08 /* RW - Configuration #1 */
#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
#define NCRCFG1_BUSID 0x07 /* Bus ID */
#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
/* 0 = 35.01 - 40MHz */
/* NEVER SET TO 1 */
/* 2 = 10MHz */
/* 3 = 10.01 - 15MHz */
/* 4 = 15.01 - 20MHz */
/* 5 = 20.01 - 25MHz */
/* 6 = 25.01 - 30MHz */
/* 7 = 30.01 - 35MHz */
#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
#define NCR_CFG2 0x0b /* RW - Configuration #2 */
#define NCRCFG2_RSVD 0xa0 /* reserved */
#define NCRCFG2_FE 0x40 /* Features Enable */
#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
#define NCRCFG2_RPE 0x02 /* Register Parity Error */
#define NCRCFG2_DPE 0x01 /* DMA Parity Error */
#define NCRCFG2_HMEFE 0x10 /* HME feature enable */
#define NCRCFG2_HME32 0x80 /* HME 32 extended */
/* Config #3 only on 53C9X */
#define NCR_CFG3 0x0c /* RW - Configuration #3 */
#define NCRCFG3_RSVD 0xe0 /* reserved */
#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
/*
* For some unknown reason, the ESP406/FAS408 looks like every
* other ncr53c9x, except for configuration #3 register. At any
* rate, if you're dealing with these chips, you need to use these
* defines instead.
*/
/* Config #3 different on ESP406/FAS408 */
#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */
#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
#define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */
#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
/* Config #3 also different on NCR53CF9x/FAS216 */
#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
/* Config #3 on FAS366 */
#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */
#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
/* Config #4 only on ESP406/FAS408 */
#define NCR_CFG4 0x0d /* RW - Configuration #4 */
#define NCRCFG4_CRS1 0x80 /* Select register set #1 */
#define NCRCFG4_RSVD 0x7b /* reserved */
#define NCRCFG4_ACTNEG 0x04 /* Active negation */
/*
The following registers are only on the ESP406/FAS408. The
documentation refers to them as "Control Register Set #1".
These are the registers that are visible when bit 7 of
register 0x0d is set. This bit is common to both register sets.
*/
#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
#define NCRJMP_RSVD 0xc0 /* reserved */
#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
#define NCRJMP_J4 0x10 /* Jumper #4 */
#define NCRJMP_J3 0x08 /* Jumper #3 */
#define NCRJMP_J2 0x04 /* Jumper #2 */
#define NCRJMP_J1 0x02 /* Jumper #1 */
#define NCRJMP_J0 0x01 /* Jumper #0 */
#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
#define NCRPSTAT_PERR 0x80 /* PIO Error */
#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
#define NCRPIOI_RSVD 0xe0 /* reserved */
#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
#define NCRPIOI_23 0x04 /* IRQ When 2/3 */
#define NCRPIOI_FULL 0x02 /* IRQ When Full */
#define NCRPIOI_FINV 0x01 /* Flag Invert */
#define NCR_CFG5 0x0d /* RW - Configuration #5 */
#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
#define NCRCFG5_AADDR 0x20 /* Auto Address */
#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
#define NCRCFG5_SINT 0x04 /* SCSI Interupt Enable */
#define NCRCFG5_INTP 0x02 /* INT Polarity */
#define NCRCFG5_AINT 0x01 /* ATA Interupt Enable */
#define NCR_SIGNTR 0x0e /* RO - Signature */
/* Am53c974 Config #3 */
#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */
#define NCRAMDCFG3_RSVD 0x07 /* Reserved */
/* Am53c974 Config #4 */
#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
#define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */
#define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */
#define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */
#define NCRAMDCFG4_RSVD 0x13 /* Reserved */
#define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */
#define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */
/*
* FAS366
*/
#define NCR_RCL NCR_TCH /* Recommand counter low */
#define NCR_RCH 0xf /* Recommand counter high */
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
/* status register #2 definitions (read only) */
#define NCR_STAT2 NCR_CCF
#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */

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/* $NetBSD: ncr53c9xvar.h,v 1.41 2003/02/04 20:05:11 pk Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _DEV_IC_NCR53C9XVAR_H_
#define _DEV_IC_NCR53C9XVAR_H_
#include <sys/lock.h>
/* Set this to 1 for normal debug, or 2 for per-target tracing. */
/* #define NCR53C9X_DEBUG 2 */
/* Wide or differential can have 16 targets */
#define NCR_NLUN 8
#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
#define FREQTOCCF(freq) (((freq + 4) / 5))
/*
* NCR 53c9x variants. Note, these values are used as indexes into
* a table; don't modify them unless you know what you're doing.
*/
#define NCR_VARIANT_ESP100 0
#define NCR_VARIANT_ESP100A 1
#define NCR_VARIANT_ESP200 2
#define NCR_VARIANT_NCR53C94 3
#define NCR_VARIANT_NCR53C96 4
#define NCR_VARIANT_ESP406 5
#define NCR_VARIANT_FAS408 6
#define NCR_VARIANT_FAS216 7
#define NCR_VARIANT_AM53C974 8
#define NCR_VARIANT_FAS366 9
#define NCR_VARIANT_NCR53C90_86C01 10
#define NCR_VARIANT_MAX 11
/*
* ECB. Holds additional information for each SCSI command Comments: We
* need a separate scsi command block because we may need to overwrite it
* with a request sense command. Basicly, we refrain from fiddling with
* the scsipi_xfer struct (except do the expected updating of return values).
* We'll generally update: xs->{flags,resid,error,sense,status} and
* occasionally xs->retries.
*/
struct ncr53c9x_ecb {
TAILQ_ENTRY(ncr53c9x_ecb) chain;
union ccb *ccb; /* SCSI xfer ctrl block from above */
struct ncr53c9x_softc *sc;
int flags;
#define ECB_ALLOC 0x01
#define ECB_READY 0x02
#define ECB_SENSE 0x04
#define ECB_ABORT 0x40
#define ECB_RESET 0x80
#define ECB_TENTATIVE_DONE 0x100
int timeout;
struct {
u_char msg[3]; /* Selection Id msg and tags */
struct scsi_generic cmd; /* SCSI command block */
} cmd;
char *daddr; /* Saved data pointer */
int clen; /* Size of command in cmd.cmd */
int dleft; /* Residue */
u_char stat; /* SCSI status byte */
u_char tag[2]; /* TAG bytes */
u_char pad[1];
#if NCR53C9X_DEBUG > 1
char trace[1000];
#endif
};
#if NCR53C9X_DEBUG > 1
#define ECB_TRACE(ecb, msg, a, b) do { \
const char *f = "[" msg "]"; \
int n = strlen((ecb)->trace); \
if (n < (sizeof((ecb)->trace)-100)) \
sprintf((ecb)->trace + n, f, a, b); \
} while(0)
#else
#define ECB_TRACE(ecb, msg, a, b)
#endif
/*
* Some info about each (possible) target and LUN on the SCSI bus.
*
* SCSI I and II devices can have up to 8 LUNs, each with up to 256
* outstanding tags. SCSI III devices have 64-bit LUN identifiers
* that can be sparsely allocated.
*
* Since SCSI II devices can have up to 8 LUNs, we use an array
* of 8 pointers to ncr53c9x_linfo structures for fast lookup.
* Longer LUNs need to traverse the linked list.
*/
struct ncr53c9x_linfo {
int64_t lun;
LIST_ENTRY(ncr53c9x_linfo) link;
time_t last_used;
unsigned char used; /* # slots in use */
unsigned char avail; /* where to start scanning */
unsigned char busy;
struct ncr53c9x_ecb *untagged;
struct ncr53c9x_ecb *queued[256];
};
struct ncr53c9x_tinfo {
int cmds; /* # of commands processed */
int dconns; /* # of disconnects */
int touts; /* # of timeouts */
int perrs; /* # of parity errors */
int senses; /* # of request sense commands sent */
u_char flags;
#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
#define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */
#define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */
#define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */
#define T_TAG 0x40 /* Turn on TAG QUEUEs */
#define T_WIDE 0x80 /* Negotiate wide options */
#define T_WDTRSENT 0x04 /* WDTR message has been sent to */
u_char period; /* Period suggestion */
u_char offset; /* Offset suggestion */
u_char cfg3; /* per target config 3 */
u_char nextag; /* Next available tag */
u_char width; /* width suggesion */
LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
};
/* Look up a lun in a tinfo */
#define TINFO_LUN(t, l) ( \
(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
? ((t)->lun[(l)]) \
: ncr53c9x_lunsearch((t), (int64_t)(l)) \
)
/* Register a linenumber (for debugging) */
#define LOGLINE(p)
#define NCR_SHOWECBS 0x01
#define NCR_SHOWINTS 0x02
#define NCR_SHOWCMDS 0x04
#define NCR_SHOWMISC 0x08
#define NCR_SHOWTRAC 0x10
#define NCR_SHOWSTART 0x20
#define NCR_SHOWPHASE 0x40
#define NCR_SHOWDMA 0x80
#define NCR_SHOWCCMDS 0x100
#define NCR_SHOWMSGS 0x200
#ifdef NCR53C9X_DEBUG
extern int ncr53c9x_debug;
#define NCR_ECBS(str) \
do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
#define NCR_MISC(str) \
do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
#define NCR_INTS(str) \
do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
#define NCR_TRACE(str) \
do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
#define NCR_CMDS(str) \
do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
#define NCR_START(str) \
do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
#define NCR_PHASE(str) \
do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
#define NCR_DMA(str) \
do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
#define NCR_MSGS(str) \
do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
#else
#define NCR_ECBS(str)
#define NCR_MISC(str)
#define NCR_INTS(str)
#define NCR_TRACE(str)
#define NCR_CMDS(str)
#define NCR_START(str)
#define NCR_PHASE(str)
#define NCR_DMA(str)
#define NCR_MSGS(str)
#endif
#define NCR_MAX_MSG_LEN 8
struct ncr53c9x_softc;
/*
* Function switch used as glue to MD code.
*/
struct ncr53c9x_glue {
/* Mandatory entry points. */
u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
int (*gl_dma_isintr)(struct ncr53c9x_softc *);
void (*gl_dma_reset)(struct ncr53c9x_softc *);
int (*gl_dma_intr)(struct ncr53c9x_softc *);
int (*gl_dma_setup)(struct ncr53c9x_softc *,
caddr_t *, size_t *, int, size_t *);
void (*gl_dma_go)(struct ncr53c9x_softc *);
void (*gl_dma_stop)(struct ncr53c9x_softc *);
int (*gl_dma_isactive)(struct ncr53c9x_softc *);
/* Optional entry points. */
void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
};
struct ncr53c9x_softc {
device_t sc_dev; /* us as a device */
struct cam_sim *sc_sim; /* our scsi adapter */
struct cam_path *sc_path; /* our scsi channel */
struct callout sc_watchdog; /* periodic timer */
struct ncr53c9x_glue *sc_glue; /* glue to MD code */
int sc_cfflags; /* Copy of config flags */
/* register defaults */
u_char sc_cfg1; /* Config 1 */
u_char sc_cfg2; /* Config 2, not ESP100 */
u_char sc_cfg3; /* Config 3, ESP200,FAS */
u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
u_char sc_cfg4; /* Config 4, only ESP200 */
u_char sc_cfg5; /* Config 5, only ESP200 */
u_char sc_ccf; /* Clock Conversion */
u_char sc_timeout;
/* register copies, see espreadregs() */
u_char sc_espintr;
u_char sc_espstat;
u_char sc_espstep;
u_char sc_espstat2;
u_char sc_espfflags;
/* Lists of command blocks */
TAILQ_HEAD(ecb_list, ncr53c9x_ecb)
ready_list;
struct ncr53c9x_ecb *sc_nexus; /* Current command */
int sc_ntarg;
struct ncr53c9x_tinfo *sc_tinfo;
/* Data about the current nexus (updated for every cmd switch) */
caddr_t sc_dp; /* Current data pointer */
ssize_t sc_dleft; /* Data left to transfer */
/* Adapter state */
int sc_phase; /* Copy of what bus phase we are in */
int sc_prevphase; /* Copy of what bus phase we were in */
u_char sc_state; /* State applicable to the adapter */
u_char sc_flags; /* See below */
u_char sc_selid;
u_char sc_lastcmd;
/* Message stuff */
u_short sc_msgify; /* IDENTIFY message associated with this nexus */
u_short sc_msgout; /* What message is on its way out? */
u_short sc_msgpriq; /* One or more messages to send (encoded) */
u_short sc_msgoutq; /* What messages have been sent so far? */
u_char *sc_omess; /* MSGOUT buffer */
caddr_t sc_omp; /* Message pointer (for multibyte messages) */
size_t sc_omlen;
u_char *sc_imess; /* MSGIN buffer */
caddr_t sc_imp; /* Message pointer (for multibyte messages) */
size_t sc_imlen;
caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
size_t sc_cmdlen; /* Size of command in transit */
/* Hardware attributes */
int sc_freq; /* SCSI bus frequency in MHz */
int sc_id; /* Our SCSI id */
int sc_rev; /* Chip revision */
int sc_features; /* Chip features */
int sc_minsync; /* Minimum sync period / 4 */
int sc_maxxfer; /* Maximum transfer size */
int sc_maxsync; /* Maximum sync period */
int sc_maxoffset; /* Maximum offset */
int sc_maxwidth; /* Maximum width */
struct mtx sc_lock; /* driver mutex */
};
/* values for sc_state */
#define NCR_IDLE 1 /* waiting for something to do */
#define NCR_SELECTING 2 /* SCSI command is arbiting */
#define NCR_RESELECTED 3 /* Has been reselected */
#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
#define NCR_CLEANING 8
#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
/* values for sc_flags */
#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
#define NCR_ABORTING 0x02 /* Bailing out */
#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
#define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
#define NCR_ICCS 0x10 /* Expect status phase results */
#define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */
#define NCR_ATN 0x40 /* ATN asserted */
#define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */
/* values for sc_features */
#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
/* values for sc_msgout */
#define SEND_DEV_RESET 0x0001
#define SEND_PARITY_ERROR 0x0002
#define SEND_INIT_DET_ERR 0x0004
#define SEND_REJECT 0x0008
#define SEND_IDENTIFY 0x0010
#define SEND_ABORT 0x0020
#define SEND_WDTR 0x0040
#define SEND_SDTR 0x0080
#define SEND_TAG 0x0100
/* SCSI Status codes */
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
/* phase bits */
#define IOI 0x01
#define CDI 0x02
#define MSGI 0x04
/* Information transfer phases */
#define DATA_OUT_PHASE (0)
#define DATA_IN_PHASE (IOI)
#define COMMAND_PHASE (CDI)
#define STATUS_PHASE (CDI|IOI)
#define MESSAGE_OUT_PHASE (MSGI|CDI)
#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
#define PHASE_MASK (MSGI|CDI|IOI)
/* Some pseudo phases for getphase()*/
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
/*
* Macros to read and write the chip's registers.
*/
#define NCR_READ_REG(sc, reg) \
(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
#define NCR_WRITE_REG(sc, reg, val) \
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
#ifdef NCR53C9X_DEBUG
#define NCRCMD(sc, cmd) do { \
if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \
sc->sc_lastcmd = cmd; \
NCR_WRITE_REG(sc, NCR_CMD, cmd); \
} while (0)
#else
#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
#endif
/*
* DMA macros for NCR53c9x
*/
#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
/*
* Macro to convert the chip register Clock Per Byte value to
* Sunchronous Transfer Period.
*/
#define ncr53c9x_cpb2stp(sc, cpb) \
((250 * (cpb)) / (sc)->sc_freq)
int ncr53c9x_attach(struct ncr53c9x_softc *);
int ncr53c9x_detach(struct ncr53c9x_softc *, int);
void ncr53c9x_action(struct cam_sim *, union ccb *);
void ncr53c9x_reset(struct ncr53c9x_softc *);
void ncr53c9x_intr(void *);
void ncr53c9x_init(struct ncr53c9x_softc *, int);
#endif /* _DEV_IC_NCR53C9XVAR_H_ */

15
sys/modules/esp/Makefile Normal file
View File

@ -0,0 +1,15 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../dev/esp
KMOD= esp
SRCS= ncr53c9x.c
SRCS+= opt_ddb.h opt_cam.h
SRCS+= device_if.h bus_if.h
.if ${MACHINE_ARCH} == "sparc64"
SRCSi+= esp_sbus.c lsi64854.c
.endif
.include <bsd.kmod.mk>

722
sys/sparc64/sbus/lsi64854.c Normal file
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@ -0,0 +1,722 @@
/*-
* Copyright (c) 2004 Scott Long
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/* $NetBSD: lsi64854.c,v 1.22 2002/10/01 07:07:03 petrov Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/resource.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/scsi/scsi_all.h>
#include <dev/esp/lsi64854reg.h>
#include <dev/esp/lsi64854var.h>
#include <dev/esp/ncr53c9xreg.h>
#include <dev/esp/ncr53c9xvar.h>
void lsi64854_reset(struct lsi64854_softc *);
int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *);
int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *);
#ifdef DEBUG
#define LDB_SCSI 1
#define LDB_ENET 2
#define LDB_PP 4
#define LDB_ANY 0xff
int lsi64854debug = 0;
#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
#else
#define DPRINTF(a,x)
#endif
#define MAX_DMA_SZ (16*1024*1024)
/*
* Finish attaching this DMA device.
* Front-end must fill in these fields:
* sc_regs
* sc_burst
* sc_channel (one of SCSI, ENET, PP)
* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
*/
void
lsi64854_attach(struct lsi64854_softc *sc)
{
u_int32_t csr;
sc->dv_name = device_get_nameunit(sc->sc_dev);
/* Indirect functions */
switch (sc->sc_channel) {
case L64854_CHANNEL_SCSI:
sc->intr = lsi64854_scsi_intr;
sc->setup = lsi64854_setup;
break;
case L64854_CHANNEL_ENET:
sc->intr = lsi64854_enet_intr;
break;
case L64854_CHANNEL_PP:
sc->setup = lsi64854_setup_pp;
break;
default:
printf("%s: unknown channel\n", sc->dv_name);
}
sc->reset = lsi64854_reset;
/* Allocate a dmamap */
if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */
1, 0, /* algnment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAX_DMA_SZ, /* maxsize */
1, /* nsegments */
MAX_DMA_SZ, /* maxsegsize */
BUS_DMA_ALLOCNOW, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->sc_buffer_dmat)) {
printf("%s: can't allocate buffer DMA tag\n", sc->dv_name);
return;
}
if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) {
printf("%s: DMA map create failed\n", sc->dv_name);
return;
}
csr = L64854_GCSR(sc);
sc->sc_rev = csr & L64854_DEVID;
if (sc->sc_rev == DMAREV_HME) {
return;
}
printf(": DMA rev ");
switch (sc->sc_rev) {
case DMAREV_0:
printf("0");
break;
case DMAREV_ESC:
printf("esc");
break;
case DMAREV_1:
printf("1");
break;
case DMAREV_PLUS:
printf("1+");
break;
case DMAREV_2:
printf("2");
break;
default:
printf("unknown (0x%x)", sc->sc_rev);
}
DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
printf("\n");
}
/*
* DMAWAIT waits while condition is true
*/
#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
int count = 500000; \
while ((COND) && --count > 0) DELAY(1); \
if (count == 0) { \
printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
(u_long)L64854_GCSR(SC)); \
if (DONTPANIC) \
printf(MSG); \
else \
panic(MSG); \
} \
} while (0)
#define DMA_DRAIN(sc, dontpanic) do { \
u_int32_t csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_ESC_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
if (sc->sc_rev != DMAREV_HME) { \
/* \
* Select drain bit based on revision \
* also clears errors and D_TC flag \
*/ \
csr = L64854_GCSR(sc); \
if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
csr |= D_ESC_DRAIN; \
else \
csr |= L64854_INVALIDATE; \
\
L64854_SCSR(sc,csr); \
} \
/* \
* Wait for draining to finish \
* rev0 & rev1 call this PACKCNT \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
} while(0)
#define DMA_FLUSH(sc, dontpanic) do { \
u_int32_t csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_ESC_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
csr = L64854_GCSR(sc); \
csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
L64854_SCSR(sc,csr); \
} while(0)
void
lsi64854_reset(struct lsi64854_softc *sc)
{
u_int32_t csr;
DMA_FLUSH(sc, 1);
csr = L64854_GCSR(sc);
DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
/*
* XXX is sync needed?
if (sc->sc_dmamap->dm_nsegs > 0)
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
*/
if (sc->sc_rev == DMAREV_HME)
L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
csr |= L64854_RESET; /* reset DMA */
L64854_SCSR(sc, csr);
DELAY(200); /* > 10 Sbus clocks(?) */
/*DMAWAIT1(sc); why was this here? */
csr = L64854_GCSR(sc);
csr &= ~L64854_RESET; /* de-assert reset line */
L64854_SCSR(sc, csr);
DELAY(5); /* allow a few ticks to settle */
csr = L64854_GCSR(sc);
csr |= L64854_INT_EN; /* enable interrupts */
if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
if (sc->sc_rev == DMAREV_HME)
csr |= D_TWO_CYCLE;
else
csr |= D_FASTER;
}
/* Set burst */
switch (sc->sc_rev) {
case DMAREV_HME:
case DMAREV_2:
csr &= ~L64854_BURST_SIZE;
if (sc->sc_burst == 32) {
csr |= L64854_BURST_32;
} else if (sc->sc_burst == 16) {
csr |= L64854_BURST_16;
} else {
csr |= L64854_BURST_0;
}
break;
case DMAREV_ESC:
csr |= D_ESC_AUTODRAIN; /* Auto-drain */
if (sc->sc_burst == 32) {
csr &= ~D_ESC_BURST;
} else
csr |= D_ESC_BURST;
break;
default:
break;
}
L64854_SCSR(sc, csr);
if (sc->sc_rev == DMAREV_HME) {
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0);
sc->sc_dmactl = csr;
}
sc->sc_active = 0;
DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
}
static void
lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
struct lsi64854_softc *sc;
sc = (struct lsi64854_softc *)arg;
if (nseg != 1)
panic("%s: cannot map %d segments\n", sc->dv_name, nseg);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
segs[0].ds_addr);
}
#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
/*
* setup a DMA transfer
*/
int
lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
u_int32_t csr;
DMA_FLUSH(sc, 0);
#if 0
DMACSR(sc) &= ~D_INT_EN;
#endif
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
sc->sc_datain = datain;
/*
* the rules say we cannot transfer more than the limit
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
/*
* XXX what length?
*/
if (sc->sc_rev == DMAREV_HME) {
L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
L64854_SCSR(sc, sc->sc_dmactl);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, *dmasize);
}
/* Program the DMA address */
if (sc->sc_dmasize) {
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
lsi64854_map_scsi, sc, 0) != 0)
panic("%s: cannot allocate DVMA address", sc->dv_name);
}
if (sc->sc_rev == DMAREV_ESC) {
/* DMA ESC chip bug work-around */
long bcnt = sc->sc_dmasize;
long eaddr = bcnt + (long)*sc->sc_dmaaddr;
if ((eaddr & PAGE_MASK_8K) != 0)
bcnt = roundup(bcnt, PAGE_SIZE_8K);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
bcnt);
}
/* Setup DMA control register */
csr = L64854_GCSR(sc);
if (datain)
csr |= L64854_WRITE;
else
csr &= ~L64854_WRITE;
csr |= L64854_INT_EN;
if (sc->sc_rev == DMAREV_HME) {
csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
}
L64854_SCSR(sc, csr);
return (0);
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. Called from ncr53c9x_intr()
* for now.
*
* return 1 if it was a DMA continue.
*/
int
lsi64854_scsi_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client;
int trans, resid;
u_int32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
csr, DDMACSR_BITS));
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS);
csr &= ~D_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE|D_SLAVE_ERR;
L64854_SCSR(sc, csr);
return (-1);
}
/* This is an "assertion" :) */
if (sc->sc_active == 0)
panic("dmaintr: DMA wasn't active");
DMA_DRAIN(sc, 0);
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the NCR53C9X counter registers get decremented
* as bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid));
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
resid <<= 1;
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the NCR53C9X counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE)
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
: 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n", sc->dv_name, trans,
sc->sc_dmasize);
#endif
trans = sc->sc_dmasize;
}
DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE)
? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
#endif
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 ||
nsc->sc_phase != nsc->sc_prevphase)
return 0;
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return 1;
#endif
return 0;
}
/*
* Pseudo (chained) interrupt to le driver to handle DMA errors.
*/
int
lsi64854_enet_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
u_int32_t csr;
static int dodrain = 0;
int rv;
csr = L64854_GCSR(sc);
/* If the DMA logic shows an interrupt, claim it */
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS);
csr &= ~L64854_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= E_INVALIDATE|E_SLAVE_ERR;
L64854_SCSR(sc, csr);
DMA_RESET(sc);
dodrain = 1;
return (1);
}
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
int i = 10;
csr |= E_DRAIN;
L64854_SCSR(sc, csr);
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
DELAY(1);
}
return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
}
static void
lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
struct lsi64854_softc *sc;
sc = (struct lsi64854_softc *)arg;
if (nsegs != 1)
panic("%s: cannot map %d segments\n", sc->dv_name, nsegs);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain
? BUS_DMASYNC_PREREAD
: BUS_DMASYNC_PREWRITE);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
segs[0].ds_addr);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
sc->sc_dmasize);
}
/*
* setup a DMA transfer
*/
int
lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
u_int32_t csr;
DMA_FLUSH(sc, 0);
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
sc->sc_datain = datain;
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name,
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
/*
* the rules say we cannot transfer more than the limit
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize));
/* Program the DMA address */
if (sc->sc_dmasize) {
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
lsi64854_map_pp, sc, 0) != 0)
panic("%s: pp cannot allocate DVMA address",
sc->dv_name);
}
/* Setup DMA control register */
csr = L64854_GCSR(sc);
csr &= ~L64854_BURST_SIZE;
if (sc->sc_burst == 32) {
csr |= L64854_BURST_32;
} else if (sc->sc_burst == 16) {
csr |= L64854_BURST_16;
} else {
csr |= L64854_BURST_0;
}
csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
#if 0
/* This bit is read-only in PP csr register */
if (datain)
csr |= P_WRITE;
else
csr &= ~P_WRITE;
#endif
L64854_SCSR(sc, csr);
return (0);
}
/*
* Parallel port DMA interrupt.
*/
int
lsi64854_pp_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
int ret, trans, resid = 0;
u_int32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
csr, PDMACSR_BITS));
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
L64854_REG_CNT);
printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid,
csr, PDMACSR_BITS);
csr &= ~P_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= P_INVALIDATE|P_SLAVE_ERR;
L64854_SCSR(sc, csr);
return (1);
}
ret = (csr & P_INT_PEND) != 0;
if (sc->sc_active != 0) {
DMA_DRAIN(sc, 0);
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
L64854_REG_CNT);
}
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
trans = sc->sc_dmasize;
}
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
#endif
return (ret != 0);
}

205
sys/sparc64/sbus/lsi64854reg.h Normal file
View File

@ -0,0 +1,205 @@
/* $NetBSD: lsi64854reg.h,v 1.4 1998/09/21 21:26:52 pk Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
/*
* LSI 64854 DMA engine. Contains three independent channels
* designed to interface with (a) a NCR539X SCSI controller,
* (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
*/
/*
* Register offsets to bus handle.
*/
#define L64854_REG_CSR 0 /* Control bits */
#define L64854_REG_ADDR 4 /* DMA Address */
#define L64854_REG_CNT 8 /* DMA count */
#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */
#define L64854_REG_ENBAR 12 /* ENET Base register */
#define L64854_REG_TEST 12 /* SCSI Test register */
#define L64854_REG_HCR 16 /* PP Hardware Configuration */
#define L64854_REG_OCR 18 /* PP Operation Configuration */
#define L64854_REG_DR 20 /* PP Data register */
#define L64854_REG_TCR 21 /* PP Transfer Control */
#define L64854_REG_OR 22 /* PP Output register */
#define L64854_REG_IR 23 /* PP Input register */
#define L64854_REG_ICR 24 /* PP Interrupt Control */
/*
* Control bits common to all three channels.
*/
#define L64854_INT_PEND 0x00000001 /* Interrupt pending */
#define L64854_ERR_PEND 0x00000002 /* Error pending */
#define L64854_DRAINING 0x0000000c /* FIFO draining */
#define L64854_INT_EN 0x00000010 /* Interrupt enable */
#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */
#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */
#define L64854_RESET 0x00000080 /* Reset device */
#define L64854_WRITE 0x00000100 /* 1: xfer to memory */
#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */
#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */
#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */
#define L64854_BURST_16 0x00000000 /* 16-byte bursts */
#define L64854_BURST_32 0x00040000 /* 32-byte bursts */
#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */
#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */
#define L64854_DEVID 0xf0000000 /* device ID bits */
/*
* SCSI DMA control bits.
*/
#define D_INT_PEND L64854_INT_PEND /* interrupt pending */
#define D_ERR_PEND L64854_ERR_PEND /* error pending */
#define D_DRAINING L64854_DRAINING /* fifo draining */
#define D_INT_EN L64854_INT_EN /* interrupt enable */
#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define D_RESET L64854_RESET /* reset scsi */
#define D_WRITE L64854_WRITE /* 1 = dev -> mem */
#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */
#define D_EN_CNT 0x00002000 /* enable byte counter */
#define D_TC 0x00004000 /* terminal count */
#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */
#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
#define D_DIAG 0x00100000 /* disable fifo drain on addr */
#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
#define D_FASTER 0x00400000 /* 3 clocks per transfer */
#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
#define D_EN_NEXT 0x01000000 /* enable auto next address */
#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */
#define D_DSBL_PARITY_CHK \
0x02000000 /* disable checking for parity on bus (default 1:fas) */
#define D_A_LOADED 0x04000000 /* address loaded */
#define D_NA_LOADED 0x08000000 /* next address loaded */
#define D_HW_RESET_FAS366 \
0x08000000 /* hardware reset FAS366 (fas) */
#define D_DEV_ID L64854_DEVID /* device ID */
#define DMAREV_0 0x00000000 /* Sunray DMA */
#define DMAREV_ESC 0x40000000 /* DMA ESC array */
#define DMAREV_1 0x80000000 /* 'DMA' */
#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
#define DMAREV_2 0xa0000000 /* 'DMA2' */
#define DMAREV_HME 0xb0000000 /* 'HME' */
/*
* revisions 0,1 and ESC have different bits.
*/
#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */
#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
#define DDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
"b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \
"b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \
"b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \
"b\32ALOADED\0b\33NALOADED\0"
/*
* ENET DMA control bits.
*/
#define E_INT_PEND L64854_INT_PEND /* interrupt pending */
#define E_ERR_PEND L64854_ERR_PEND /* error pending */
#define E_DRAINING L64854_DRAINING /* fifo draining */
#define E_INT_EN L64854_INT_EN /* interrupt enable */
#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define E_RESET L64854_RESET /* reset ENET */
#define E_reserved1 0x00000300 /* */
#define E_DRAIN 0x00000400 /* force Ecache drain */
#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */
#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */
#define E_reserved2 0x00006000 /* */
#define E_ILACC 0x00008000 /* ... */
#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */
#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */
#define E_reserved3 0x00100000 /* */
#define E_LOOP_TEST 0x00200000 /* loopback mode */
#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */
#define E_reserved4 0x0c800000 /* */
#define E_DEV_ID L64854_DEVID /* ID bits */
#define EDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \
"b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \
"b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \
"b\25LOOPTEST\0b\26TP\0"
/*
* PP DMA control bits.
*/
#define P_INT_PEND L64854_INT_PEND /* interrupt pending */
#define P_ERR_PEND L64854_ERR_PEND /* error pending */
#define P_DRAINING L64854_DRAINING /* fifo draining */
#define P_INT_EN L64854_INT_EN /* interrupt enable */
#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
#define P_RESET L64854_RESET /* reset PP */
#define P_WRITE L64854_WRITE /* 1: xfer to memory */
#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */
#define P_reserved1 0x00001c00 /* */
#define P_EN_CNT 0x00002000 /* enable counter */
#define P_TC 0x00004000 /* terminal count */
#define P_reserved2 0x00038000 /* */
#define P_DIAG 0x00100000 /* ... */
#define P_reserved3 0x00600000 /* */
#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */
#define P_EN_NEXT 0x01000000 /* enable DMA chaining */
#define P_DMA_ON 0x02000000 /* DMA xfers enabled */
#define P_A_LOADED 0x04000000 /* addr and byte count valid */
#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */
#define P_DEV_ID L64854_DEVID /* ID bits */
#define PDMACSR_BITS "\177\020" \
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
"b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \
"b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0"

114
sys/sparc64/sbus/lsi64854var.h Normal file
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/* $NetBSD: lsi64854var.h,v 1.4 2001/03/29 02:58:39 petrov Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
struct lsi64854_softc {
device_t sc_dev;
const char *dv_name;
int sc_rid;
struct resource *sc_res;
bus_space_handle_t sc_regh;
bus_space_tag_t sc_regt;
u_int sc_rev; /* revision */
int sc_burst; /* max suported burst size */
int sc_channel;
#define L64854_CHANNEL_SCSI 1
#define L64854_CHANNEL_ENET 2
#define L64854_CHANNEL_PP 3
void *sc_client;
int sc_active; /* DMA active ? */
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
bus_dma_tag_t sc_parent_dmat;
bus_dma_tag_t sc_buffer_dmat;
int sc_datain;
size_t sc_dmasize;
caddr_t *sc_dmaaddr;
size_t *sc_dmalen;
void (*reset)(struct lsi64854_softc *);/* reset routine */
int (*setup)(struct lsi64854_softc *, caddr_t *, size_t *,
int, size_t *); /* DMA setup */
int (*intr)(void *); /* interrupt handler */
int (*sc_intrchain)(void *); /* next handler in intr chain */
void *sc_intrchainarg; /* arg for next intr handler */
u_int sc_dmactl;
};
#define L64854_GCSR(sc) \
(bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR))
#define L64854_SCSR(sc, csr) \
bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR, csr)
/*
* DMA engine interface functions.
*/
#define DMA_RESET(sc) (((sc)->reset)(sc))
#define DMA_INTR(sc) (((sc)->intr)(sc))
#define DMA_SETUP(sc, a, l, d, s) (((sc)->setup)(sc, a, l, d, s))
#define DMA_ISACTIVE(sc) ((sc)->sc_active)
#define DMA_ENINTR(sc) do { \
u_int32_t csr = L64854_GCSR(sc); \
csr |= L64854_INT_EN; \
L64854_SCSR(sc, csr); \
} while (0)
#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
#define DMA_GO(sc) do { \
u_int32_t csr = L64854_GCSR(sc); \
csr |= D_EN_DMA; \
L64854_SCSR(sc, csr); \
sc->sc_active = 1; \
} while (0)
void lsi64854_attach(struct lsi64854_softc *);
int lsi64854_scsi_intr(void *);
int lsi64854_enet_intr(void *);
int lsi64854_pp_intr(void *);