The whitespace crusader strikes!
This commit is contained in:
parent
4fb65f044c
commit
c3aedce23c
@ -111,7 +111,7 @@ static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
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static int bfe_miibus_readreg (device_t, int, int);
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static int bfe_miibus_writereg (device_t, int, int, int);
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static void bfe_miibus_statchg (device_t);
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static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
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static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
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u_long, const int);
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static void bfe_get_config (struct bfe_softc *sc);
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static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
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@ -161,7 +161,7 @@ DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
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DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
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/*
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* Probe for a Broadcom 4401 chip.
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* Probe for a Broadcom 4401 chip.
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*/
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static int
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bfe_probe(device_t dev)
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@ -180,12 +180,12 @@ bfe_probe(device_t dev)
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if ((pci_get_vendor(dev) == t->bfe_vid) &&
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(pci_get_device(dev) == t->bfe_did)) {
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device_set_desc_copy(dev, t->bfe_name);
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return(0);
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return (0);
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}
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t++;
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}
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return(ENXIO);
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return (ENXIO);
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}
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static int
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@ -199,7 +199,7 @@ bfe_dma_alloc(device_t dev)
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/* parent tag */
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error = bus_dma_tag_create(NULL, /* parent */
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PAGE_SIZE, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR_32BIT, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAXBSIZE, /* maxsize */
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@ -213,7 +213,7 @@ bfe_dma_alloc(device_t dev)
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error = bus_dma_tag_create(sc->bfe_parent_tag,
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BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE,
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BUS_SPACE_MAXADDR,
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BUS_SPACE_MAXADDR,
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BUS_SPACE_MAXADDR,
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NULL, NULL,
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BFE_TX_LIST_SIZE,
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1,
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@ -224,7 +224,7 @@ bfe_dma_alloc(device_t dev)
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if (error) {
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device_printf(dev, "could not allocate dma tag\n");
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return(ENOMEM);
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return (ENOMEM);
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}
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/* tag for RX ring */
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@ -242,7 +242,7 @@ bfe_dma_alloc(device_t dev)
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if (error) {
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device_printf(dev, "could not allocate dma tag\n");
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return(ENOMEM);
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return (ENOMEM);
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}
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/* tag for mbufs */
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@ -260,7 +260,7 @@ bfe_dma_alloc(device_t dev)
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if (error) {
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device_printf(dev, "could not allocate dma tag\n");
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return(ENOMEM);
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return (ENOMEM);
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}
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/* pre allocate dmamaps for RX list */
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@ -269,7 +269,7 @@ bfe_dma_alloc(device_t dev)
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&sc->bfe_rx_ring[i].bfe_map);
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if (error) {
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device_printf(dev, "cannot create DMA map for RX\n");
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return(ENOMEM);
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return (ENOMEM);
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}
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}
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@ -279,7 +279,7 @@ bfe_dma_alloc(device_t dev)
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&sc->bfe_tx_ring[i].bfe_map);
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if (error) {
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device_printf(dev, "cannot create DMA map for TX\n");
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return(ENOMEM);
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return (ENOMEM);
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}
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}
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@ -288,7 +288,7 @@ bfe_dma_alloc(device_t dev)
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BUS_DMA_NOWAIT, &sc->bfe_rx_map);
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if(error)
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return(ENOMEM);
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return (ENOMEM);
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bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
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error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
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@ -296,26 +296,26 @@ bfe_dma_alloc(device_t dev)
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bfe_dma_map, &sc->bfe_rx_dma, 0);
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if(error)
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return(ENOMEM);
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return (ENOMEM);
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bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
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error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
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error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
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BUS_DMA_NOWAIT, &sc->bfe_tx_map);
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if (error)
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return(ENOMEM);
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if (error)
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return (ENOMEM);
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error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
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sc->bfe_tx_list, sizeof(struct bfe_desc),
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error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
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sc->bfe_tx_list, sizeof(struct bfe_desc),
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bfe_dma_map, &sc->bfe_tx_dma, 0);
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if(error)
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return(ENOMEM);
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return (ENOMEM);
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bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
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bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
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return(0);
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return (0);
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}
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static int
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@ -442,7 +442,7 @@ bfe_attach(device_t dev)
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fail:
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if(error)
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bfe_release_resources(sc);
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return(error);
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return (error);
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}
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static int
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@ -473,7 +473,7 @@ bfe_detach(device_t dev)
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BFE_UNLOCK(sc);
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mtx_destroy(&sc->bfe_mtx);
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return(0);
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return (0);
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}
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/*
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@ -487,7 +487,7 @@ bfe_shutdown(device_t dev)
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sc = device_get_softc(dev);
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BFE_LOCK(sc);
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bfe_stop(sc);
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bfe_stop(sc);
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BFE_UNLOCK(sc);
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return;
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@ -501,10 +501,10 @@ bfe_miibus_readreg(device_t dev, int phy, int reg)
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sc = device_get_softc(dev);
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if(phy != sc->bfe_phyaddr)
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return(0);
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return (0);
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bfe_readphy(sc, reg, &ret);
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return(ret);
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return (ret);
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}
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static int
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@ -514,10 +514,10 @@ bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
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sc = device_get_softc(dev);
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if(phy != sc->bfe_phyaddr)
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return(0);
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bfe_writephy(sc, reg, val);
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return (0);
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bfe_writephy(sc, reg, val);
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return(0);
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return (0);
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}
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static void
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@ -530,7 +530,7 @@ static void
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bfe_tx_ring_free(struct bfe_softc *sc)
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{
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int i;
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for(i = 0; i < BFE_TX_LIST_CNT; i++) {
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if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
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m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
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@ -565,14 +565,14 @@ bfe_rx_ring_free(struct bfe_softc *sc)
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}
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static int
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static int
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bfe_list_rx_init(struct bfe_softc *sc)
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{
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int i;
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for(i = 0; i < BFE_RX_LIST_CNT; i++) {
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if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
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return ENOBUFS;
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if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
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return (ENOBUFS);
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}
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bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
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@ -580,7 +580,7 @@ bfe_list_rx_init(struct bfe_softc *sc)
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sc->bfe_rx_cons = 0;
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return(0);
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return (0);
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}
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static int
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@ -592,12 +592,12 @@ bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
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u_int32_t ctrl;
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if ((c < 0) || (c >= BFE_RX_LIST_CNT))
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return(EINVAL);
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return (EINVAL);
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if(m == NULL) {
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m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
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if(m == NULL)
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return(ENOBUFS);
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return (ENOBUFS);
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m->m_len = m->m_pkthdr.len = MCLBYTES;
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}
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else
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@ -611,7 +611,7 @@ bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
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sc->bfe_rx_cnt = c;
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d = &sc->bfe_rx_list[c];
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r = &sc->bfe_rx_ring[c];
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bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
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bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
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MCLBYTES, bfe_dma_map_desc, d, 0);
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bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
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@ -623,7 +623,7 @@ bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
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d->bfe_ctrl = ctrl;
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r->bfe_mbuf = m;
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bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
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return(0);
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return (0);
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}
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static void
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@ -643,7 +643,7 @@ bfe_get_config(struct bfe_softc *sc)
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sc->bfe_phyaddr = eeprom[90] & 0x1f;
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sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
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sc->bfe_core_unit = 0;
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sc->bfe_core_unit = 0;
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sc->bfe_dma_offset = BFE_PCI_DMA;
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}
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@ -667,7 +667,7 @@ bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
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pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
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}
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static void
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static void
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bfe_clear_stats(struct bfe_softc *sc)
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{
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u_long reg;
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@ -683,7 +683,7 @@ bfe_clear_stats(struct bfe_softc *sc)
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BFE_UNLOCK(sc);
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}
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static int
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static int
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bfe_resetphy(struct bfe_softc *sc)
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{
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u_int32_t val;
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@ -695,10 +695,10 @@ bfe_resetphy(struct bfe_softc *sc)
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if (val & BMCR_RESET) {
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printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
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BFE_UNLOCK(sc);
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return ENXIO;
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return (ENXIO);
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}
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BFE_UNLOCK(sc);
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return 0;
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return (0);
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}
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static void
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@ -722,7 +722,7 @@ bfe_chip_halt(struct bfe_softc *sc)
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static void
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bfe_chip_reset(struct bfe_softc *sc)
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{
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u_int32_t val;
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u_int32_t val;
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BFE_LOCK(sc);
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@ -739,7 +739,7 @@ bfe_chip_reset(struct bfe_softc *sc)
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bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
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CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
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sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
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if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
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if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
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bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
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100, 0);
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CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
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@ -760,25 +760,25 @@ bfe_chip_reset(struct bfe_softc *sc)
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/* Internal or external PHY? */
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val = CSR_READ_4(sc, BFE_DEVCTRL);
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if(!(val & BFE_IPP))
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if(!(val & BFE_IPP))
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CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
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else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
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BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
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DELAY(100);
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}
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/* Enable CRC32 generation and set proper LED modes */
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BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
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/* Enable CRC32 generation and set proper LED modes */
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BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
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/* Reset or clear powerdown control bit */
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BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
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/* Reset or clear powerdown control bit */
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BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
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CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
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CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
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BFE_LAZY_FC_MASK));
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/*
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/*
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* We don't want lazy interrupts, so just send them at
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* the end of a frame, please
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* the end of a frame, please
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*/
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BFE_OR(sc, BFE_RCV_LAZY, 0);
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@ -789,14 +789,14 @@ bfe_chip_reset(struct bfe_softc *sc)
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/* Set watermark XXX - magic */
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CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
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/*
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/*
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* Initialise DMA channels
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* - not forgetting dma addresses need to be added to BFE_PCI_DMA
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* - not forgetting dma addresses need to be added to BFE_PCI_DMA
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*/
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CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
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CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
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CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
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CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
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BFE_RX_CTRL_ENABLE);
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CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
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@ -812,7 +812,7 @@ bfe_core_disable(struct bfe_softc *sc)
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if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
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return;
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/*
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/*
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* Set reject, wait for it set, then wait for the core to stop
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* being busy, then set reset and reject and enable the clocks.
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*/
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@ -859,7 +859,7 @@ bfe_core_reset(struct bfe_softc *sc)
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DELAY(10);
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}
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static void
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static void
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bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
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{
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u_int32_t val;
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@ -878,7 +878,7 @@ bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
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bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
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}
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static void
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static void
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bfe_set_rx_mode(struct bfe_softc *sc)
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{
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struct ifnet *ifp = &sc->arpcom.ac_if;
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@ -1002,7 +1002,7 @@ bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
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}
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static int
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bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
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bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
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u_long timeout, const int clear)
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{
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u_long i;
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@ -1018,17 +1018,17 @@ bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
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}
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if (i == timeout) {
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printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
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"%x to %s.\n", sc->bfe_unit, bit, reg,
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"%x to %s.\n", sc->bfe_unit, bit, reg,
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(clear ? "clear" : "set"));
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return -1;
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return (-1);
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}
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return 0;
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return (0);
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}
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static int
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bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
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{
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int err;
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int err;
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|
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BFE_LOCK(sc);
|
||||
/* Clear MII ISR */
|
||||
@ -1042,7 +1042,7 @@ bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
|
||||
*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
|
||||
|
||||
BFE_UNLOCK(sc);
|
||||
return err;
|
||||
return (err);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -1061,10 +1061,10 @@ bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
|
||||
status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
|
||||
BFE_UNLOCK(sc);
|
||||
|
||||
return status;
|
||||
return (status);
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* XXX - I think this is handled by the PHY driver, but it can't hurt to do it
|
||||
* twice
|
||||
*/
|
||||
@ -1076,7 +1076,7 @@ bfe_setupphy(struct bfe_softc *sc)
|
||||
|
||||
/* Enable activity LED */
|
||||
bfe_readphy(sc, 26, &val);
|
||||
bfe_writephy(sc, 26, val & 0x7fff);
|
||||
bfe_writephy(sc, 26, val & 0x7fff);
|
||||
bfe_readphy(sc, 26, &val);
|
||||
|
||||
/* Enable traffic meter LED mode */
|
||||
@ -1084,10 +1084,10 @@ bfe_setupphy(struct bfe_softc *sc)
|
||||
bfe_writephy(sc, 27, val | (1 << 6));
|
||||
|
||||
BFE_UNLOCK(sc);
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
static void
|
||||
bfe_stats_update(struct bfe_softc *sc)
|
||||
{
|
||||
u_long reg;
|
||||
@ -1221,7 +1221,7 @@ bfe_intr(void *xsc)
|
||||
istat = CSR_READ_4(sc, BFE_ISTAT);
|
||||
imask = CSR_READ_4(sc, BFE_IMASK);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Defer unsolicited interrupts - This is necessary because setting the
|
||||
* chips interrupt mask register to 0 doesn't actually stop the
|
||||
* interrupts
|
||||
@ -1257,7 +1257,7 @@ bfe_intr(void *xsc)
|
||||
if(istat & BFE_ISTAT_TX)
|
||||
bfe_txeof(sc);
|
||||
|
||||
/* We have packets pending, fire them out */
|
||||
/* We have packets pending, fire them out */
|
||||
if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
||||
bfe_start(ifp);
|
||||
|
||||
@ -1269,12 +1269,12 @@ bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
|
||||
{
|
||||
struct bfe_desc *d = NULL;
|
||||
struct bfe_data *r = NULL;
|
||||
struct mbuf *m;
|
||||
struct mbuf *m;
|
||||
u_int32_t frag, cur, cnt = 0;
|
||||
int chainlen = 0;
|
||||
|
||||
if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
|
||||
return(ENOBUFS);
|
||||
return (ENOBUFS);
|
||||
|
||||
/*
|
||||
* Count the number of frags in this chain to see if
|
||||
@ -1282,15 +1282,15 @@ bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
|
||||
* by all packets, we'll m_defrag long chains so that they
|
||||
* do not use up the entire list, even if they would fit.
|
||||
*/
|
||||
for(m = m_head; m != NULL; m = m->m_next)
|
||||
for(m = m_head; m != NULL; m = m->m_next)
|
||||
chainlen++;
|
||||
|
||||
|
||||
if ((chainlen > BFE_TX_LIST_CNT / 4) ||
|
||||
if ((chainlen > BFE_TX_LIST_CNT / 4) ||
|
||||
((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) {
|
||||
m = m_defrag(m_head, M_DONTWAIT);
|
||||
if (m == NULL)
|
||||
return(ENOBUFS);
|
||||
if (m == NULL)
|
||||
return (ENOBUFS);
|
||||
m_head = m;
|
||||
}
|
||||
|
||||
@ -1306,7 +1306,7 @@ bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
|
||||
for(m = m_head; m != NULL; m = m->m_next) {
|
||||
if(m->m_len != 0) {
|
||||
if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
|
||||
return(ENOBUFS);
|
||||
return (ENOBUFS);
|
||||
|
||||
d = &sc->bfe_tx_list[cur];
|
||||
r = &sc->bfe_tx_ring[cur];
|
||||
@ -1324,7 +1324,7 @@ bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
|
||||
d->bfe_ctrl |= BFE_DESC_EOT;
|
||||
|
||||
bus_dmamap_load(sc->bfe_tag,
|
||||
r->bfe_map, mtod(m, void*), m->m_len,
|
||||
r->bfe_map, mtod(m, void*), m->m_len,
|
||||
bfe_dma_map_desc, d, 0);
|
||||
bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
|
||||
BUS_DMASYNC_PREREAD);
|
||||
@ -1336,7 +1336,7 @@ bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
|
||||
}
|
||||
|
||||
if (m != NULL)
|
||||
return(ENOBUFS);
|
||||
return (ENOBUFS);
|
||||
|
||||
sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
|
||||
sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
|
||||
@ -1362,7 +1362,7 @@ bfe_start(struct ifnet *ifp)
|
||||
|
||||
BFE_LOCK(sc);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Not much point trying to send if the link is down
|
||||
* or we have nothing to send.
|
||||
*/
|
||||
@ -1381,7 +1381,7 @@ bfe_start(struct ifnet *ifp)
|
||||
if(m_head == NULL)
|
||||
break;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Pack the data into the tx ring. If we dont have
|
||||
* enough room, let the chip drain the ring.
|
||||
*/
|
||||
@ -1472,7 +1472,7 @@ bfe_ifmedia_upd(struct ifnet *ifp)
|
||||
mii_mediachg(mii);
|
||||
|
||||
BFE_UNLOCK(sc);
|
||||
return(0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1526,12 +1526,12 @@ bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
|
||||
command);
|
||||
break;
|
||||
default:
|
||||
error = ether_ioctl(ifp, command, data);
|
||||
error = ether_ioctl(ifp, command, data);
|
||||
break;
|
||||
}
|
||||
|
||||
BFE_UNLOCK(sc);
|
||||
return error;
|
||||
return (error);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1576,7 +1576,7 @@ bfe_tick(void *xsc)
|
||||
|
||||
mii_tick(mii);
|
||||
if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
|
||||
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
|
||||
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
|
||||
sc->bfe_link++;
|
||||
|
||||
BFE_UNLOCK(sc);
|
||||
|
@ -59,11 +59,11 @@
|
||||
#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
|
||||
#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
|
||||
#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\
|
||||
BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
|
||||
BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
|
||||
|
||||
#define BFE_IMASK 0x00000024 /* Interrupt Mask */
|
||||
#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \
|
||||
BFE_ISTAT_TX)
|
||||
BFE_ISTAT_TX)
|
||||
|
||||
#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
|
||||
#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
|
||||
@ -408,7 +408,7 @@
|
||||
#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
|
||||
#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
|
||||
#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
|
||||
BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
|
||||
BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
|
||||
|
||||
#define BFE_MCAST_TBL_SIZE 32
|
||||
#define BFE_PCI_DMA 0x40000000
|
||||
@ -433,16 +433,16 @@
|
||||
#define BFE_TX_QLEN 256
|
||||
|
||||
#define CSR_READ_4(sc, reg) \
|
||||
bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg)
|
||||
bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg)
|
||||
|
||||
#define CSR_WRITE_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val)
|
||||
bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val)
|
||||
|
||||
#define BFE_OR(sc, name, val) \
|
||||
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
|
||||
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
|
||||
|
||||
#define BFE_AND(sc, name, val) \
|
||||
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
|
||||
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
|
||||
|
||||
#define BFE_LOCK(scp) mtx_lock(&sc->bfe_mtx)
|
||||
#define BFE_UNLOCK(scp) mtx_unlock(&sc->bfe_mtx)
|
||||
@ -486,7 +486,7 @@ struct bfe_hw_stats {
|
||||
u_int32_t rx_pause_pkts, rx_nonpause_pkts;
|
||||
};
|
||||
|
||||
struct bfe_softc
|
||||
struct bfe_softc
|
||||
{
|
||||
struct arpcom arpcom; /* interface info */
|
||||
device_t bfe_dev;
|
||||
@ -524,7 +524,7 @@ struct bfe_softc
|
||||
char *bfe_vpd_readonly;
|
||||
};
|
||||
|
||||
struct bfe_type
|
||||
struct bfe_type
|
||||
{
|
||||
u_int16_t bfe_vid;
|
||||
u_int16_t bfe_did;
|
||||
|
Loading…
x
Reference in New Issue
Block a user