Remove these files as they now live in sys/dev/dpt/
This commit is contained in:
Matthew N. Dodd
parent
c0de9fc637
commit
c3c2c94e00
@ -1,261 +0,0 @@
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/*
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* Copyright (c) 1997 by Matthew N. Dodd <winter@jurai.net>
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Credits: Based on and part of the DPT driver for FreeBSD written and
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* maintained by Simon Shapiro <shimon@simon-shapiro.org>
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*/
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/*
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* $FreeBSD$
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*/
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#include "eisa.h"
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#if NEISA > 0
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#include "opt_dpt.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/dpt/dpt.h>
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#include <i386/eisa/eisaconf.h>
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#include <i386/eisa/dpt_eisa.h>
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#include <machine/clock.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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/* Function Prototypes */
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static const char *dpt_eisa_match(eisa_id_t);
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static int
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dpt_eisa_probe(device_t dev)
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{
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const char *desc;
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u_int32_t io_base;
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u_int intdef;
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u_int irq;
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int shared;
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desc = dpt_eisa_match(eisa_get_id(dev));
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if (!desc)
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return (ENXIO);
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device_set_desc(dev, desc);
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io_base = (eisa_get_slot(dev) * EISA_SLOT_SIZE)
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+ DPT_EISA_SLOT_OFFSET;
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eisa_add_iospace(dev, io_base, DPT_EISA_IOSIZE, RESVADDR_NONE);
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outb((DPT_EISA_CFENABLE + io_base), 0xf8);
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intdef = inb(DPT_EISA_INTDEF + io_base);
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irq = intdef & DPT_EISA_INT_NUM_MASK;
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shared = (intdef & DPT_EISA_INT_LEVEL)
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? EISA_TRIGGER_LEVEL : EISA_TRIGGER_EDGE;
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switch (irq) {
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case DPT_EISA_INT_NUM_11:
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irq = 11;
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break;
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case DPT_EISA_INT_NUM_15:
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irq = 15;
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break;
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case DPT_EISA_INT_NUM_14:
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irq = 14;
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break;
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default:
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device_printf(dev, "dpt at slot %d: illegal irq setting %d\n",
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eisa_get_slot(dev), irq);
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irq = 0;
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break;
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}
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if (irq == 0)
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return (ENXIO);
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eisa_add_intr(dev, irq, shared);
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return 0;
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}
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static int
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dpt_eisa_attach(device_t dev)
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{
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dpt_softc_t *dpt;
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struct resource *io = 0;
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struct resource *irq = 0;
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int unit = device_get_unit(dev);
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int s;
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int rid;
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void *ih;
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rid = 0;
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io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
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0, ~0, 1, RF_ACTIVE);
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if (!io) {
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device_printf(dev, "No I/O space?!\n");
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return ENOMEM;
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}
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dpt = dpt_alloc(unit, rman_get_bustag(io),
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rman_get_bushandle(io) + DPT_EISA_EATA_REG_OFFSET);
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if (dpt == NULL)
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goto bad;
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/* Allocate a dmatag representing the capabilities of this attachment */
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/* XXX Should be a child of the EISA bus dma tag */
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if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
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/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
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/*nsegments*/BUS_SPACE_UNRESTRICTED,
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/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
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/*flags*/0, &dpt->parent_dmat) != 0) {
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dpt_free(dpt);
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goto bad;
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}
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rid = 0;
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irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
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0, ~0, 1, RF_ACTIVE);
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if (!irq) {
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device_printf(dev, "No irq?!\n");
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goto bad;
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}
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s = splcam();
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if (dpt_init(dpt) != 0) {
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dpt_free(dpt);
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goto bad;
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}
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/* Register with the XPT */
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dpt_attach(dpt);
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bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih);
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splx(s);
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return 0;
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bad:
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if (io)
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bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
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if (irq)
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bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
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return -1;
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}
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static const char *
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dpt_eisa_match(type)
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eisa_id_t type;
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{
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switch (type) {
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case DPT_EISA_DPT2402 :
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return ("DPT PM2012A/9X");
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break;
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case DPT_EISA_DPTA401 :
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return ("DPT PM2012B/9X");
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break;
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case DPT_EISA_DPTA402 :
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return ("DPT PM2012B2/9X");
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break;
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case DPT_EISA_DPTA410 :
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return ("DPT PM2x22A/9X");
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break;
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case DPT_EISA_DPTA411 :
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return ("DPT Spectre");
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break;
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case DPT_EISA_DPTA412 :
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return ("DPT PM2021A/9X");
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break;
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case DPT_EISA_DPTA420 :
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return ("DPT Smart Cache IV (PM2042)");
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break;
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case DPT_EISA_DPTA501 :
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return ("DPT PM2012B1/9X");
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break;
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case DPT_EISA_DPTA502 :
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return ("DPT PM2012Bx/9X");
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break;
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case DPT_EISA_DPTA701 :
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return ("DPT PM2011B1/9X");
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break;
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case DPT_EISA_DPTBC01 :
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return ("DPT PM3011/7X ESDI");
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break;
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case DPT_EISA_NEC8200 :
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return ("NEC EATA SCSI");
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break;
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case DPT_EISA_ATT2408 :
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return ("ATT EATA SCSI");
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break;
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default:
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break;
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}
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return (NULL);
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}
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static device_method_t dpt_eisa_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, dpt_eisa_probe),
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DEVMETHOD(device_attach, dpt_eisa_attach),
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{ 0, 0 }
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};
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static driver_t dpt_eisa_driver = {
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"dpt",
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dpt_eisa_methods,
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1, /* unused */
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};
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static devclass_t dpt_devclass;
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DRIVER_MODULE(dpt, eisa, dpt_eisa_driver, dpt_devclass, 0, 0);
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#endif /* NEISA > 0 */
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@ -1,66 +0,0 @@
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/**
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* Copyright (c) 1997 by Matthew N. Dodd <winter@jurai.net>
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Credits: Based on and part of the DPT driver for FreeBSD written and
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* maintained by Simon Shapiro <shimon@simon-shapiro.org>
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*/
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/*
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* $FreeBSD$
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*/
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#define DPT_EISA_SLOT_OFFSET 0xc00
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#define DPT_EISA_IOSIZE 0x100
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#define DPT_EISA_CFENABLE 0x8f
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#define DPT_EISA_INTDEF 0x90
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#define DPT_EISA_INT_LEVEL 0x04
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#define DPT_EISA_INT_NUM_MASK 0x38
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#define DPT_EISA_INT_NUM_11 0x08
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#define DPT_EISA_INT_NUM_15 0x10
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#define DPT_EISA_INT_NUM_14 0x20
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#define DPT_EISA_EATA_REG_OFFSET 0x88
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#define ISA_PRIMARY_WD_ADDRESS 0x1f8
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#define DPT_EISA_DPT2402 0x12142402
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#define DPT_EISA_DPTA401 0x1214A401
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#define DPT_EISA_DPTA402 0x1214A402
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#define DPT_EISA_DPTA410 0x1214A410
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#define DPT_EISA_DPTA411 0x1214A411
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#define DPT_EISA_DPTA412 0x1214A412
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#define DPT_EISA_DPTA420 0x1214A420
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#define DPT_EISA_DPTA501 0x1214A501
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#define DPT_EISA_DPTA502 0x1214A502
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#define DPT_EISA_DPTA701 0x1214A701
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#define DPT_EISA_DPTBC01 0x1214BC01
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#define DPT_EISA_NEC8200 0x12148200
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#define DPT_EISA_ATT2408 0x12142408
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@ -1,186 +0,0 @@
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/*
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* Copyright (c) 1997 by Simon Shapiro
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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*/
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/*
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* dptpci.c: PCI Bus Attachment for DPT SCSI HBAs
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*/
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#ident "$FreeBSD$"
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#include "opt_dpt.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/kernel.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <machine/bus_memio.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/dpt/dpt.h>
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#include <pci/dpt_pci.h>
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#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
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#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
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#define ISA_PRIMARY_WD_ADDRESS 0x1f8
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/* Global variables */
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/* Function Prototypes */
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static const char *dpt_pci_probe(pcici_t tag, pcidi_t type);
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static void dpt_pci_attach(pcici_t config_id, int unit);
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extern struct cdevsw dpt_cdevsw;
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static struct pci_device dpt_pci_driver =
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{
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"dpt",
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dpt_pci_probe,
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dpt_pci_attach,
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&dpt_unit,
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NULL
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};
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COMPAT_PCI_DRIVER(dpt_pci, dpt_pci_driver);
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/*
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* Probe the PCI device.
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* Some of this work will have to be duplicated in _attach
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* because we do not know for sure how the two relate.
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*/
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static const char *
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dpt_pci_probe(pcici_t tag, pcidi_t type)
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{
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u_int32_t class;
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#ifndef PCI_COMMAND_MASTER_ENABLE
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#define PCI_COMMAND_MASTER_ENABLE 0x00000004
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#endif
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#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
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#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
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#endif
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class = pci_conf_read(tag, PCI_CLASS_REG);
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if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID
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&& (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE
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&& (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI)
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return ("DPT Caching SCSI RAID Controller");
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return (NULL);
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}
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static void
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dpt_pci_attach(pcici_t config_id, int unit)
|
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{
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dpt_softc_t *dpt;
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vm_offset_t vaddr;
|
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#ifdef DPT_ALLOW_MEMIO
|
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vm_offset_t paddr;
|
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#endif
|
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u_int16_t io_base;
|
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bus_space_tag_t tag;
|
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bus_space_handle_t bsh;
|
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u_int32_t command;
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int s;
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vaddr = NULL;
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command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
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#ifdef DPT_ALLOW_MEMIO
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if ((command & PCI_COMMAND_MEM_ENABLE) == 0
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|| (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
|
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#endif
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if ((command & PCI_COMMAND_IO_ENABLE) == 0
|
||||
|| (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0)
|
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return;
|
||||
|
||||
/*
|
||||
* If the DPT is mapped as an IDE controller,
|
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* let it be IDE controller
|
||||
*/
|
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if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) {
|
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#ifdef DPT_DEBUG_WARN
|
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printf("dpt%d: Mapped as an IDE controller. "
|
||||
"Disabling SCSI setup\n", unit);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/* XXX Should be passed in by parent bus */
|
||||
/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
|
||||
if (vaddr != 0) {
|
||||
tag = I386_BUS_SPACE_MEM;
|
||||
bsh = vaddr + 0x10;
|
||||
} else {
|
||||
tag = I386_BUS_SPACE_IO;
|
||||
bsh = io_base + 0x10;
|
||||
}
|
||||
|
||||
if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL)
|
||||
return; /* XXX PCI code should take return status */
|
||||
|
||||
/* Allocate a dmatag representing the capabilities of this attachment */
|
||||
/* XXX Should be a child of the PCI bus dma tag */
|
||||
if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
|
||||
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
||||
/*highaddr*/BUS_SPACE_MAXADDR,
|
||||
/*filter*/NULL, /*filterarg*/NULL,
|
||||
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
|
||||
/*nsegments*/BUS_SPACE_UNRESTRICTED,
|
||||
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
|
||||
/*flags*/0, &dpt->parent_dmat) != 0) {
|
||||
dpt_free(dpt);
|
||||
return;
|
||||
}
|
||||
|
||||
if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
|
||||
dpt_free(dpt);
|
||||
return;
|
||||
}
|
||||
|
||||
s = splcam();
|
||||
if (dpt_init(dpt) != 0) {
|
||||
dpt_free(dpt);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Register with the XPT */
|
||||
dpt_attach(dpt);
|
||||
splx(s);
|
||||
}
|
||||
@ -1,207 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1997 by Simon Shapiro
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ident "$FreeBSD$"
|
||||
|
||||
#define DPT_VENDOR_ID 0x00001044
|
||||
#define DPT_DEVICE_ID 0x0000a400
|
||||
|
||||
/* The following are taken, shamelessly from Linux include/linux/pci.h */
|
||||
|
||||
/*
|
||||
* Under PCI, each device has 256 bytes of configuration address space,
|
||||
* of which the first 64 bytes are standardized as follows:
|
||||
*/
|
||||
#define PCI_VENDOR_ID 0x00 /* 16 bits */
|
||||
#define PCI_DEVICE_ID 0x02 /* 16 bits */
|
||||
#define PCI_COMMAND 0x04 /* 16 bits */
|
||||
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
|
||||
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
|
||||
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
|
||||
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
|
||||
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
|
||||
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
|
||||
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
|
||||
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
|
||||
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
|
||||
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
|
||||
|
||||
#define PCI_STATUS 0x06 /* 16 bits */
|
||||
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
|
||||
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
|
||||
|
||||
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
|
||||
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
|
||||
#ifndef PCI_STATUS_DEVSEL_MASK
|
||||
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
|
||||
#define PCI_STATUS_DEVSEL_FAST 0x000
|
||||
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
|
||||
#define PCI_STATUS_DEVSEL_SLOW 0x400
|
||||
#endif
|
||||
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
|
||||
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
|
||||
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
|
||||
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
|
||||
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
|
||||
|
||||
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
|
||||
* revision */
|
||||
#define PCI_REVISION_ID 0x08 /* Revision ID */
|
||||
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
|
||||
#define PCI_CLASS_DEVICE 0x0a /* Device class */
|
||||
|
||||
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
|
||||
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
|
||||
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
|
||||
#define PCI_BIST 0x0f /* 8 bits */
|
||||
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
|
||||
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
|
||||
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
|
||||
|
||||
/*
|
||||
* Base addresses specify locations in memory or I/O space.
|
||||
* Decoded size can be determined by writing a value of
|
||||
* 0xffffffff to the register, and reading it back. Only
|
||||
* 1 bits are decoded.
|
||||
*/
|
||||
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
|
||||
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
|
||||
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
|
||||
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
|
||||
#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
|
||||
/* bit 1 is reserved if address_space = 1 */
|
||||
|
||||
#define PCI_CARDBUS_CIS 0x28
|
||||
#define PCI_SUBSYSTEM_ID 0x2c
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2e
|
||||
#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
|
||||
#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, bits 31..11
|
||||
* are address, 10..2 are reserved */
|
||||
|
||||
/* 0x34-0x3b are reserved */
|
||||
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
|
||||
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
|
||||
#define PCI_MIN_GNT 0x3e /* 8 bits */
|
||||
#define PCI_MAX_LAT 0x3f /* 8 bits */
|
||||
|
||||
#define PCI_CLASS_NOT_DEFINED 0x0000
|
||||
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
|
||||
|
||||
#define PCI_BASE_CLASS_STORAGE 0x01
|
||||
#define PCI_CLASS_STORAGE_SCSI 0x0100
|
||||
#define PCI_CLASS_STORAGE_IDE 0x0101
|
||||
#define PCI_CLASS_STORAGE_FLOPPY 0x0102
|
||||
#define PCI_CLASS_STORAGE_IPI 0x0103
|
||||
#define PCI_CLASS_STORAGE_RAID 0x0104
|
||||
#define PCI_CLASS_STORAGE_OTHER 0x0180
|
||||
|
||||
#define PCI_BASE_CLASS_NETWORK 0x02
|
||||
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
|
||||
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
|
||||
#define PCI_CLASS_NETWORK_FDDI 0x0202
|
||||
#define PCI_CLASS_NETWORK_ATM 0x0203
|
||||
#define PCI_CLASS_NETWORK_OTHER 0x0280
|
||||
|
||||
#define PCI_BASE_CLASS_DISPLAY 0x03
|
||||
#define PCI_CLASS_DISPLAY_VGA 0x0300
|
||||
#define PCI_CLASS_DISPLAY_XGA 0x0301
|
||||
#define PCI_CLASS_DISPLAY_OTHER 0x0380
|
||||
|
||||
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
|
||||
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
|
||||
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
|
||||
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
|
||||
|
||||
#define PCI_BASE_CLASS_MEMORY 0x05
|
||||
#define PCI_CLASS_MEMORY_RAM 0x0500
|
||||
#define PCI_CLASS_MEMORY_FLASH 0x0501
|
||||
#define PCI_CLASS_MEMORY_OTHER 0x0580
|
||||
|
||||
#define PCI_BASE_CLASS_BRIDGE 0x06
|
||||
#define PCI_CLASS_BRIDGE_HOST 0x0600
|
||||
#define PCI_CLASS_BRIDGE_ISA 0x0601
|
||||
#define PCI_CLASS_BRIDGE_EISA 0x0602
|
||||
#define PCI_CLASS_BRIDGE_MC 0x0603
|
||||
#define PCI_CLASS_BRIDGE_PCI 0x0604
|
||||
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
|
||||
#define PCI_CLASS_BRIDGE_NUBUS 0x0606
|
||||
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
|
||||
#define PCI_CLASS_BRIDGE_OTHER 0x0680
|
||||
|
||||
|
||||
#define PCI_BASE_CLASS_COMMUNICATION 0x07
|
||||
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
|
||||
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
|
||||
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
|
||||
|
||||
#define PCI_BASE_CLASS_SYSTEM 0x08
|
||||
#define PCI_CLASS_SYSTEM_PIC 0x0800
|
||||
#define PCI_CLASS_SYSTEM_DMA 0x0801
|
||||
#define PCI_CLASS_SYSTEM_TIMER 0x0802
|
||||
#define PCI_CLASS_SYSTEM_RTC 0x0803
|
||||
#define PCI_CLASS_SYSTEM_OTHER 0x0880
|
||||
|
||||
#define PCI_BASE_CLASS_INPUT 0x09
|
||||
#define PCI_CLASS_INPUT_KEYBOARD 0x0900
|
||||
#define PCI_CLASS_INPUT_PEN 0x0901
|
||||
#define PCI_CLASS_INPUT_MOUSE 0x0902
|
||||
#define PCI_CLASS_INPUT_OTHER 0x0980
|
||||
|
||||
#define PCI_BASE_CLASS_DOCKING 0x0a
|
||||
#define PCI_CLASS_DOCKING_GENERIC 0x0a00
|
||||
#define PCI_CLASS_DOCKING_OTHER 0x0a01
|
||||
|
||||
#define PCI_BASE_CLASS_PROCESSOR 0x0b
|
||||
#define PCI_CLASS_PROCESSOR_386 0x0b00
|
||||
#define PCI_CLASS_PROCESSOR_486 0x0b01
|
||||
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
|
||||
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
|
||||
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
|
||||
#define PCI_CLASS_PROCESSOR_CO 0x0b40
|
||||
|
||||
#define PCI_BASE_CLASS_SERIAL 0x0c
|
||||
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
|
||||
#define PCI_CLASS_SERIAL_ACCESS 0x0c01
|
||||
#define PCI_CLASS_SERIAL_SSA 0x0c02
|
||||
#define PCI_CLASS_SERIAL_USB 0x0c03
|
||||
#define PCI_CLASS_SERIAL_FIBER 0x0c04
|
||||
|
||||
#define PCI_CLASS_OTHERS 0xff
|
||||
Loading…
Reference in New Issue
Block a user