Update with last year of work.
This commit is contained in:
Sam Leffler
parent
05f1e03f00
commit
c42a7b7e25
3948
sys/dev/ath/if_ath.c
3948
sys/dev/ath/if_ath.c
File diff suppressed because it is too large
Load Diff
@ -41,43 +41,27 @@ __FBSDID("$FreeBSD$");
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* PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
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*/
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#include "opt_inet.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/errno.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/ethernet.h>
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#include <net/if_llc.h>
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#include <net/if_arp.h>
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#include <net80211/ieee80211.h>
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#include <net80211/ieee80211_crypto.h>
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#include <net80211/ieee80211_node.h>
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#include <net80211/ieee80211_proto.h>
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#include <net80211/ieee80211_var.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#endif
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#include <dev/ath/if_athvar.h>
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#include <contrib/dev/ath/ah.h>
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@ -92,7 +76,7 @@ struct ath_pci_softc {
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struct ath_softc sc_sc;
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struct resource *sc_sr; /* memory resource */
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struct resource *sc_irq; /* irq resource */
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void *sc_ih; /* intererupt handler */
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void *sc_ih; /* interrupt handler */
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u_int8_t sc_saved_intline;
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u_int8_t sc_saved_cachelinesz;
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u_int8_t sc_saved_lattimer;
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@ -106,7 +90,7 @@ ath_pci_probe(device_t dev)
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const char* devname;
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devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
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if (devname) {
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if (devname != NULL) {
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device_set_desc(dev, devname);
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return 0;
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}
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@ -185,7 +169,7 @@ ath_pci_attach(device_t dev)
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NULL, NULL, /* filter, filterarg */
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0x3ffff, /* maxsize XXX */
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ATH_MAX_SCATTER, /* nsegments */
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0xffff, /* maxsegsize XXX */
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BUS_SPACE_MAXADDR, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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NULL, /* lockfunc */
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NULL, /* lockarg */
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@ -300,3 +284,4 @@ DRIVER_MODULE(if_ath, cardbus, ath_pci_driver, ath_devclass, 0, 0);
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MODULE_VERSION(if_ath, 1);
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MODULE_DEPEND(if_ath, ath_hal, 1, 1, 1); /* Atheros HAL */
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MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
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MODULE_DEPEND(if_ath, ath_rate, 1, 1, 1); /* rate control algorithm */
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@ -46,10 +46,13 @@ struct ath_stats {
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u_int32_t ast_watchdog; /* device reset by watchdog */
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u_int32_t ast_hardware; /* fatal hardware error interrupts */
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u_int32_t ast_bmiss; /* beacon miss interrupts */
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u_int32_t ast_bstuck; /* beacon stuck interrupts */
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u_int32_t ast_rxorn; /* rx overrun interrupts */
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u_int32_t ast_rxeol; /* rx eol interrupts */
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u_int32_t ast_txurn; /* tx underrun interrupts */
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u_int32_t ast_mib; /* mib interrupts */
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u_int32_t ast_intrcoal; /* interrupts coalesced */
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u_int32_t ast_tx_packets; /* packet sent on the interface */
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u_int32_t ast_tx_mgmt; /* management frames transmitted */
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u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
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u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
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@ -78,11 +81,17 @@ struct ath_stats {
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u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
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u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
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u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
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u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
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u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
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u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
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u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
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u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
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u_int32_t ast_rx_packets; /* packet recv on the interface */
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u_int32_t ast_rx_mgt; /* management frames received */
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u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
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int8_t ast_tx_rssi; /* tx rssi of last ack */
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int8_t ast_rx_rssi; /* rx rssi from histogram */
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u_int32_t ast_be_xmit; /* beacons transmitted */
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u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
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u_int32_t ast_per_cal; /* periodic calibration calls */
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u_int32_t ast_per_calfail;/* periodic calibration failed */
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@ -90,15 +99,25 @@ struct ath_stats {
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u_int32_t ast_rate_calls; /* rate control checks */
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u_int32_t ast_rate_raise; /* rate control raised xmit rate */
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u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
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u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
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u_int32_t ast_ant_txswitch;/* tx antenna switches */
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u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
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u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
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};
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#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
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struct ath_diag {
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char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
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u_int ad_id;
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caddr_t ad_data;
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u_int ad_size;
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char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
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u_int16_t ad_id;
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#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
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#define ATH_DIAG_IN 0x4000 /* copy in parameters */
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#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
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#define ATH_DIAG_ID 0x0fff
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u_int16_t ad_in_size; /* pack to fit, yech */
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caddr_t ad_in_data;
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caddr_t ad_out_data;
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u_int ad_out_size;
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};
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#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
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140
sys/dev/ath/if_athrate.h
Normal file
140
sys/dev/ath/if_athrate.h
Normal file
@ -0,0 +1,140 @@
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/*-
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* Copyright (c) 2004 Sam Leffler, Errno Consulting
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* Copyright (c) 2004 Video54 Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_RATECTRL_H_
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#define _ATH_RATECTRL_H_
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/*
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* Interface definitions for transmit rate control modules for the
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* Atheros driver.
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*
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* A rate control module is responsible for choosing the transmit rate
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* for each data frame. Management+control frames are always sent at
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* a fixed rate.
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*
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* Only one module may be present at a time; the driver references
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* rate control interfaces by symbol name. If multiple modules are
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* to be supported we'll need to switch to a registration-based scheme
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* as is currently done, for example, for authentication modules.
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*
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* An instance of the rate control module is attached to each device
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* at attach time and detached when the device is destroyed. The module
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* may associate data with each device and each node (station). Both
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* sets of storage are opaque except for the size of the per-node storage
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* which must be provided when the module is attached.
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*
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* The rate control module is notified for each state transition and
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* station association/reassociation. Otherwise it is queried for a
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* rate for each outgoing frame and provided status from each transmitted
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* frame. Any ancillary processing is the responsibility of the module
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* (e.g. if periodic processing is required then the module should setup
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* it's own timer).
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*
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* In addition to the transmit rate for each frame the module must also
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* indicate the number of attempts to make at the specified rate. If this
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* number is != ATH_TXMAXTRY then an additional callback is made to setup
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* additional transmit state. The rate control code is assumed to write
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* this additional data directly to the transmit descriptor.
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*/
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struct ath_softc;
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struct ath_node;
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struct ath_desc;
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struct ath_ratectrl {
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size_t arc_space; /* space required for per-node state */
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};
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/*
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* Attach/detach a rate control module.
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*/
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struct ath_ratectrl *ath_rate_attach(struct ath_softc *);
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void ath_rate_detach(struct ath_ratectrl *);
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/*
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* State storage handling.
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*/
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/*
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* Initialize per-node state already allocated for the specified
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* node; this space can be assumed initialized to zero.
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*/
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void ath_rate_node_init(struct ath_softc *, struct ath_node *);
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/*
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* Cleanup any per-node state prior to the node being reclaimed.
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*/
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void ath_rate_node_cleanup(struct ath_softc *, struct ath_node *);
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/*
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* Update rate control state on station associate/reassociate
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* (when operating as an ap or for nodes discovered when operating
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* in ibss mode).
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*/
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void ath_rate_newassoc(struct ath_softc *, struct ath_node *,
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int isNewAssociation);
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/*
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* Update/reset rate control state for 802.11 state transitions.
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* Important mostly as the analog to ath_rate_newassoc when operating
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* in station mode.
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*/
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void ath_rate_newstate(struct ath_softc *, enum ieee80211_state);
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/*
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* Transmit handling.
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*/
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/*
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* Return the transmit info for a data packet. If multi-rate state
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* is to be setup then try0 should contain a value other than ATH_TXMATRY
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* and ath_rate_setupxtxdesc will be called after deciding if the frame
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* can be transmitted with multi-rate retry.
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*/
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void ath_rate_findrate(struct ath_softc *, struct ath_node *,
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HAL_BOOL shortPreamble, size_t frameLen,
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u_int8_t *rix, int *try0, u_int8_t *txrate);
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/*
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* Setup any extended (multi-rate) descriptor state for a data packet.
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* The rate index returned by ath_rate_findrate is passed back in.
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*/
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void ath_rate_setupxtxdesc(struct ath_softc *, struct ath_node *,
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struct ath_desc *, HAL_BOOL shortPreamble, u_int8_t rix);
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/*
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* Update rate control state for a packet associated with the
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* supplied transmit descriptor. The routine is invoked both
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* for packets that were successfully sent and for those that
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* failed (consult the descriptor for details).
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*/
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void ath_rate_tx_complete(struct ath_softc *, struct ath_node *,
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const struct ath_desc *);
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#endif /* _ATH_RATECTRL_H_ */
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@ -47,73 +47,150 @@
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#include <contrib/dev/ath/ah.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/ath/if_athioctl.h>
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#include <dev/ath/if_athrate.h>
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#define ATH_TIMEOUT 1000
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#define ATH_RXBUF 40 /* number of RX buffers */
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#define ATH_TXBUF 60 /* number of TX buffers */
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#define ATH_TXDESC 8 /* number of descriptors per buffer */
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#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
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#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
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struct ath_recv_hist {
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int arh_ticks; /* sample time by system clock */
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u_int8_t arh_rssi; /* rssi */
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u_int8_t arh_antenna; /* antenna */
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};
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#define ATH_RHIST_SIZE 16 /* number of samples */
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#define ATH_RHIST_NOTIME (~0)
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/* driver-specific node */
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/* driver-specific node state */
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struct ath_node {
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struct ieee80211_node an_node; /* base class */
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u_int an_tx_ok; /* tx ok pkt */
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u_int an_tx_err; /* tx !ok pkt */
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u_int an_tx_retr; /* tx retry count */
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int an_tx_upper; /* tx upper rate req cnt */
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u_int an_tx_antenna; /* antenna for last good frame */
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u_int an_rx_antenna; /* antenna for last rcvd frame */
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struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE];
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u_int an_rx_hist_next;/* index of next ``free entry'' */
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u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
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u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */
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u_int32_t an_avgrssi; /* average rssi over all rx frames */
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HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
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/* variable-length rate control state follows */
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};
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#define ATH_NODE(_n) ((struct ath_node *)(_n))
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#define ATH_NODE(ni) ((struct ath_node *)(ni))
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#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
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#define ATH_RSSI_LPF_LEN 10
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#define ATH_RSSI_DUMMY_MARKER 0x127
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#define ATH_EP_MUL(x, mul) ((x) * (mul))
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#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
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#define ATH_LPF_RSSI(x, y, len) \
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((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
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#define ATH_RSSI_LPF(x, y) do { \
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if ((y) >= -20) \
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x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
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} while (0)
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struct ath_buf {
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TAILQ_ENTRY(ath_buf) bf_list;
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STAILQ_ENTRY(ath_buf) bf_list;
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int bf_nseg;
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bus_dmamap_t bf_dmamap; /* DMA map of the buffer */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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bus_addr_t bf_daddr; /* physical addr of desc */
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bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
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struct mbuf *bf_m; /* mbuf for buf */
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struct ieee80211_node *bf_node; /* pointer to the node */
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bus_size_t bf_mapsize;
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#define ATH_MAX_SCATTER 64
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bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
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};
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typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
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/*
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* DMA state for tx/rx descriptors.
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*/
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struct ath_descdma {
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const char* dd_name;
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struct ath_desc *dd_desc; /* descriptors */
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bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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bus_addr_t dd_desc_len; /* size of dd_desc */
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bus_dma_segment_t dd_dseg;
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bus_dma_tag_t dd_dmat; /* bus DMA tag */
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bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
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struct ath_buf *dd_bufptr; /* associated buffers */
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};
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/*
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* Data transmit queue state. One of these exists for each
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* hardware transmit queue. Packets sent to us from above
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* are assigned to queues based on their priority. Not all
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* devices support a complete set of hardware transmit queues.
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* For those devices the array sc_ac2q will map multiple
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* priorities to fewer hardware queues (typically all to one
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* hardware queue).
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*/
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struct ath_txq {
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u_int axq_qnum; /* hardware q number */
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u_int axq_depth; /* queue depth (stat only) */
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u_int axq_intrcnt; /* interrupt count */
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u_int32_t *axq_link; /* link ptr in last TX desc */
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STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
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struct mtx axq_lock; /* lock on q and link */
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};
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#define ATH_TXQ_LOCK_INIT(_sc, _tq) \
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mtx_init(&(_tq)->axq_lock, \
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device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
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#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
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#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
|
||||
#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
|
||||
#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
|
||||
|
||||
#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
|
||||
STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
|
||||
(_tq)->axq_depth++; \
|
||||
} while (0)
|
||||
#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
|
||||
STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
|
||||
(_tq)->axq_depth--; \
|
||||
} while (0)
|
||||
|
||||
struct ath_softc {
|
||||
struct arpcom sc_arp; /* interface common */
|
||||
struct ath_stats sc_stats; /* interface statistics */
|
||||
struct ieee80211com sc_ic; /* IEEE 802.11 common */
|
||||
int sc_regdomain;
|
||||
int sc_countrycode;
|
||||
int sc_debug;
|
||||
void (*sc_recv_mgmt)(struct ieee80211com *,
|
||||
struct mbuf *,
|
||||
struct ieee80211_node *,
|
||||
int, int, u_int32_t);
|
||||
int (*sc_newstate)(struct ieee80211com *,
|
||||
enum ieee80211_state, int);
|
||||
void (*sc_node_free)(struct ieee80211com *,
|
||||
struct ieee80211_node *);
|
||||
void (*sc_node_copy)(struct ieee80211com *,
|
||||
struct ieee80211_node *,
|
||||
const struct ieee80211_node *);
|
||||
void (*sc_node_free)(struct ieee80211_node *);
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_st; /* bus space tag */
|
||||
bus_space_handle_t sc_sh; /* bus space handle */
|
||||
bus_dma_tag_t sc_dmat; /* bus DMA tag */
|
||||
struct mtx sc_mtx; /* master lock (recursive) */
|
||||
struct ath_hal *sc_ah; /* Atheros HAL */
|
||||
struct ath_ratectrl *sc_rc; /* tx rate control support */
|
||||
void (*sc_setdefantenna)(struct ath_softc *, u_int);
|
||||
unsigned int sc_invalid : 1,/* disable hardware accesses */
|
||||
sc_doani : 1,/* dynamic noise immunity */
|
||||
sc_probing : 1;/* probing AP on beacon miss */
|
||||
sc_mrretry : 1, /* multi-rate retry support */
|
||||
sc_softled : 1, /* enable LED gpio status */
|
||||
sc_splitmic: 1, /* split TKIP MIC keys */
|
||||
sc_needmib : 1, /* enable MIB stats intr */
|
||||
sc_hasdiversity : 1,/* rx diversity available */
|
||||
sc_diversity : 1,/* enable rx diversity */
|
||||
sc_hasveol : 1, /* tx VEOL support */
|
||||
sc_hastpc : 1; /* per-packet TPC support */
|
||||
/* rate tables */
|
||||
const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
|
||||
const HAL_RATE_TABLE *sc_currates; /* current rate table */
|
||||
enum ieee80211_phymode sc_curmode; /* current phy mode */
|
||||
u_int16_t sc_curtxpow; /* current tx power limit */
|
||||
HAL_CHANNEL sc_curchan; /* current h/w channel */
|
||||
u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
|
||||
u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */
|
||||
u_int8_t sc_protrix; /* protection rate index */
|
||||
u_int sc_txantenna; /* tx antenna (fixed or auto) */
|
||||
HAL_INT sc_imask; /* interrupt mask copy */
|
||||
u_int sc_keymax; /* size of key cache */
|
||||
u_int8_t sc_keymap[16]; /* bit map of key cache use */
|
||||
|
||||
u_int32_t sc_beacons; /* beacon count for LED mgmt */
|
||||
u_int16_t sc_ledstate; /* LED on/off state */
|
||||
u_int16_t sc_ledpin; /* GPIO pin for driving LED */
|
||||
|
||||
struct bpf_if *sc_drvbpf;
|
||||
union {
|
||||
@ -127,37 +204,45 @@ struct ath_softc {
|
||||
} u_rx_rt;
|
||||
int sc_rx_th_len;
|
||||
|
||||
struct ath_desc *sc_desc; /* TX/RX descriptors */
|
||||
bus_dma_segment_t sc_dseg;
|
||||
bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */
|
||||
bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */
|
||||
bus_addr_t sc_desc_len; /* size of sc_desc */
|
||||
|
||||
struct task sc_fataltask; /* fatal int processing */
|
||||
struct task sc_rxorntask; /* rxorn int processing */
|
||||
|
||||
TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */
|
||||
struct ath_descdma sc_rxdma; /* RX descriptos */
|
||||
ath_bufhead sc_rxbuf; /* receive buffer */
|
||||
u_int32_t *sc_rxlink; /* link ptr in last RX desc */
|
||||
struct task sc_rxtask; /* rx int processing */
|
||||
struct task sc_rxorntask; /* rxorn int processing */
|
||||
u_int8_t sc_defant; /* current default antenna */
|
||||
u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
|
||||
|
||||
u_int sc_txhalq; /* HAL q for outgoing frames */
|
||||
u_int32_t *sc_txlink; /* link ptr in last TX desc */
|
||||
int sc_tx_timer; /* transmit timeout */
|
||||
TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */
|
||||
struct ath_descdma sc_txdma; /* TX descriptors */
|
||||
ath_bufhead sc_txbuf; /* transmit buffer */
|
||||
struct mtx sc_txbuflock; /* txbuf lock */
|
||||
TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */
|
||||
struct mtx sc_txqlock; /* lock on txq and txlink */
|
||||
int sc_tx_timer; /* transmit timeout */
|
||||
u_int sc_txqsetup; /* h/w queues setup */
|
||||
u_int sc_txintrperiod;/* tx interrupt batching */
|
||||
struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
|
||||
struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
|
||||
struct task sc_txtask; /* tx int processing */
|
||||
|
||||
struct ath_descdma sc_bdma; /* beacon descriptors */
|
||||
ath_bufhead sc_bbuf; /* beacon buffers */
|
||||
u_int sc_bhalq; /* HAL q for outgoing beacons */
|
||||
struct ath_buf *sc_bcbuf; /* beacon buffer */
|
||||
struct ath_buf *sc_bufptr; /* allocated buffer ptr */
|
||||
u_int sc_bmisscount; /* missed beacon transmits */
|
||||
u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
|
||||
struct ath_txq *sc_cabq; /* tx q for cab frames */
|
||||
struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
|
||||
struct task sc_bmisstask; /* bmiss int processing */
|
||||
struct task sc_bstucktask; /* stuck beacon processing */
|
||||
enum {
|
||||
OK, /* no change needed */
|
||||
UPDATE, /* update pending */
|
||||
COMMIT /* beacon sent, commit change */
|
||||
} sc_updateslot; /* slot time update fsm */
|
||||
|
||||
struct callout sc_cal_ch; /* callout handle for cals */
|
||||
struct callout sc_scan_ch; /* callout handle for scan */
|
||||
struct ath_stats sc_stats; /* interface statistics */
|
||||
};
|
||||
#define sc_if sc_arp.ac_if
|
||||
#define sc_tx_th u_tx_rt.th
|
||||
#define sc_rx_th u_rx_rt.th
|
||||
|
||||
@ -169,6 +254,8 @@ struct ath_softc {
|
||||
#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
||||
#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
|
||||
|
||||
#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
|
||||
|
||||
#define ATH_TXBUF_LOCK_INIT(_sc) \
|
||||
mtx_init(&(_sc)->sc_txbuflock, \
|
||||
device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
|
||||
@ -178,14 +265,6 @@ struct ath_softc {
|
||||
#define ATH_TXBUF_LOCK_ASSERT(_sc) \
|
||||
mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
|
||||
|
||||
#define ATH_TXQ_LOCK_INIT(_sc) \
|
||||
mtx_init(&(_sc)->sc_txqlock, \
|
||||
device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
|
||||
#define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock)
|
||||
#define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock)
|
||||
#define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock)
|
||||
#define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED)
|
||||
|
||||
int ath_attach(u_int16_t, struct ath_softc *);
|
||||
int ath_detach(struct ath_softc *);
|
||||
void ath_resume(struct ath_softc *);
|
||||
@ -196,17 +275,16 @@ void ath_intr(void *);
|
||||
/*
|
||||
* HAL definitions to comply with local coding convention.
|
||||
*/
|
||||
#define ath_hal_detach(_ah) \
|
||||
((*(_ah)->ah_detach)((_ah)))
|
||||
#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
|
||||
((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
|
||||
#define ath_hal_getratetable(_ah, _mode) \
|
||||
((*(_ah)->ah_getRateTable)((_ah), (_mode)))
|
||||
#define ath_hal_getregdomain(_ah) \
|
||||
((*(_ah)->ah_getRegDomain)((_ah)))
|
||||
#define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode
|
||||
#define ath_hal_getmac(_ah, _mac) \
|
||||
((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
|
||||
#define ath_hal_detach(_ah) \
|
||||
((*(_ah)->ah_detach)((_ah)))
|
||||
#define ath_hal_setmac(_ah, _mac) \
|
||||
((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
|
||||
#define ath_hal_intrset(_ah, _mask) \
|
||||
((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
|
||||
#define ath_hal_intrget(_ah) \
|
||||
@ -219,10 +297,12 @@ void ath_intr(void *);
|
||||
((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
|
||||
#define ath_hal_setpower(_ah, _mode, _sleepduration) \
|
||||
((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
|
||||
#define ath_hal_keycachesize(_ah) \
|
||||
((*(_ah)->ah_getKeyCacheSize)((_ah)))
|
||||
#define ath_hal_keyreset(_ah, _ix) \
|
||||
((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
|
||||
#define ath_hal_keyset(_ah, _ix, _pk) \
|
||||
((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE))
|
||||
#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
|
||||
((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
|
||||
#define ath_hal_keyisvalid(_ah, _ix) \
|
||||
(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
|
||||
#define ath_hal_keysetmac(_ah, _ix, _mac) \
|
||||
@ -249,6 +329,8 @@ void ath_intr(void *);
|
||||
((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
|
||||
#define ath_hal_gettxbuf(_ah, _q) \
|
||||
((*(_ah)->ah_getTxDP)((_ah), (_q)))
|
||||
#define ath_hal_numtxpending(_ah, _q) \
|
||||
((*(_ah)->ah_numTxPending)((_ah), (_q)))
|
||||
#define ath_hal_getrxbuf(_ah) \
|
||||
((*(_ah)->ah_getRxDP)((_ah)))
|
||||
#define ath_hal_txstart(_ah, _q) \
|
||||
@ -259,17 +341,18 @@ void ath_intr(void *);
|
||||
((*(_ah)->ah_perCalibration)((_ah), (_chan)))
|
||||
#define ath_hal_setledstate(_ah, _state) \
|
||||
((*(_ah)->ah_setLedState)((_ah), (_state)))
|
||||
#define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \
|
||||
((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod)))
|
||||
#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
|
||||
((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
|
||||
#define ath_hal_beaconreset(_ah) \
|
||||
((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
|
||||
#define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \
|
||||
((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \
|
||||
(_dc), (_cc)))
|
||||
#define ath_hal_beacontimers(_ah, _bs) \
|
||||
((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
|
||||
#define ath_hal_setassocid(_ah, _bss, _associd) \
|
||||
((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0))
|
||||
#define ath_hal_setopmode(_ah, _opmode) \
|
||||
((*(_ah)->ah_setPCUConfig)((_ah), (_opmode)))
|
||||
((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
|
||||
#define ath_hal_phydisable(_ah) \
|
||||
((*(_ah)->ah_phyDisable)((_ah)))
|
||||
#define ath_hal_setopmode(_ah) \
|
||||
((*(_ah)->ah_setPCUConfig)((_ah)))
|
||||
#define ath_hal_stoptxdma(_ah, _qnum) \
|
||||
((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
|
||||
#define ath_hal_stoppcurecv(_ah) \
|
||||
@ -278,27 +361,90 @@ void ath_intr(void *);
|
||||
((*(_ah)->ah_startPcuReceive)((_ah)))
|
||||
#define ath_hal_stopdmarecv(_ah) \
|
||||
((*(_ah)->ah_stopDmaReceive)((_ah)))
|
||||
#define ath_hal_dumpstate(_ah) \
|
||||
((*(_ah)->ah_dumpState)((_ah)))
|
||||
#define ath_hal_getdiagstate(_ah, _id, _data, _size) \
|
||||
((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size)))
|
||||
#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
|
||||
((*(_ah)->ah_getDiagState)((_ah), (_id), \
|
||||
(_indata), (_insize), (_outdata), (_outsize)))
|
||||
#define ath_hal_setuptxqueue(_ah, _type, _irq) \
|
||||
((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
|
||||
#define ath_hal_resettxqueue(_ah, _q) \
|
||||
((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
|
||||
#define ath_hal_releasetxqueue(_ah, _q) \
|
||||
((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
|
||||
#define ath_hal_hasveol(_ah) \
|
||||
((*(_ah)->ah_hasVEOL)((_ah)))
|
||||
#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
|
||||
((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
|
||||
#define ath_hal_settxqueueprops(_ah, _q, _qi) \
|
||||
((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
|
||||
#define ath_hal_getrfgain(_ah) \
|
||||
((*(_ah)->ah_getRfGain)((_ah)))
|
||||
#define ath_hal_rxmonitor(_ah) \
|
||||
((*(_ah)->ah_rxMonitor)((_ah)))
|
||||
#define ath_hal_getdefantenna(_ah) \
|
||||
((*(_ah)->ah_getDefAntenna)((_ah)))
|
||||
#define ath_hal_setdefantenna(_ah, _ant) \
|
||||
((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
|
||||
#define ath_hal_rxmonitor(_ah, _arg) \
|
||||
((*(_ah)->ah_rxMonitor)((_ah), (_arg)))
|
||||
#define ath_hal_mibevent(_ah, _stats) \
|
||||
((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
|
||||
#define ath_hal_setslottime(_ah, _us) \
|
||||
((*(_ah)->ah_setSlotTime)((_ah), (_us)))
|
||||
#define ath_hal_getslottime(_ah) \
|
||||
((*(_ah)->ah_getSlotTime)((_ah)))
|
||||
#define ath_hal_setacktimeout(_ah, _us) \
|
||||
((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
|
||||
#define ath_hal_getacktimeout(_ah) \
|
||||
((*(_ah)->ah_getAckTimeout)((_ah)))
|
||||
#define ath_hal_setctstimeout(_ah, _us) \
|
||||
((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
|
||||
#define ath_hal_getctstimeout(_ah) \
|
||||
((*(_ah)->ah_getCTSTimeout)((_ah)))
|
||||
#define ath_hal_getcapability(_ah, _cap, _param, _result) \
|
||||
((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
|
||||
#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
|
||||
((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
|
||||
#define ath_hal_ciphersupported(_ah, _cipher) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
|
||||
#define ath_hal_getregdomain(_ah, _prd) \
|
||||
ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
|
||||
#define ath_hal_getcountrycode(_ah, _pcc) \
|
||||
(*(_pcc) = (_ah)->ah_countryCode)
|
||||
#define ath_hal_tkipsplit(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_hwphycounters(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_hasdiversity(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_getdiversity(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
|
||||
#define ath_hal_setdiversity(_ah, _v) \
|
||||
ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
|
||||
#define ath_hal_getdiag(_ah, _pv) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
|
||||
#define ath_hal_setdiag(_ah, _v) \
|
||||
ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
|
||||
#define ath_hal_getnumtxqueues(_ah, _pv) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
|
||||
#define ath_hal_hasveol(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_hastxpowlimit(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_settxpowlimit(_ah, _pow) \
|
||||
((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
|
||||
#define ath_hal_gettxpowlimit(_ah, _ppow) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
|
||||
#define ath_hal_getmaxtxpow(_ah, _ppow) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
|
||||
#define ath_hal_gettpscale(_ah, _scale) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
|
||||
#define ath_hal_settpscale(_ah, _v) \
|
||||
ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
|
||||
#define ath_hal_hastpc(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_gettpc(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
|
||||
#define ath_hal_settpc(_ah, _v) \
|
||||
ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
|
||||
#define ath_hal_hasbursting(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
|
||||
|
||||
#define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \
|
||||
_rate, _antmode) \
|
||||
((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \
|
||||
(_flen), (_hlen), (_rate), (_antmode)))
|
||||
#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
|
||||
((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
|
||||
#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
|
||||
@ -309,13 +455,22 @@ void ath_intr(void *);
|
||||
((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
|
||||
(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
|
||||
(_flags), (_rtsrate), (_rtsdura)))
|
||||
#define ath_hal_setupxtxdesc(_ah, _ds, _short, \
|
||||
#define ath_hal_setupxtxdesc(_ah, _ds, \
|
||||
_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
|
||||
((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \
|
||||
((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
|
||||
(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
|
||||
#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \
|
||||
((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last)))
|
||||
#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
|
||||
((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
|
||||
#define ath_hal_txprocdesc(_ah, _ds) \
|
||||
((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
|
||||
#define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \
|
||||
_gatingds, _txOpLimit, _ctsDuration) \
|
||||
((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \
|
||||
(_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration)))
|
||||
|
||||
#define ath_hal_gpioCfgOutput(_ah, _gpio) \
|
||||
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
|
||||
#define ath_hal_gpioset(_ah, _gpio, _b) \
|
||||
((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
|
||||
|
||||
#endif /* _DEV_ATH_ATHVAR_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user