Resolv the remaining conflicting symbols between omap4 and am335x, and
add omap4/pandaboard into the GENERIC kernel.
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3cf1f0c347
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c49cf11473
@ -43,6 +43,7 @@ files "../nvidia/tegra124/files.tegra124"
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files "../qemu/files.qemu"
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files "../ti/files.ti"
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files "../ti/am335x/files.am335x"
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files "../ti/omap4/files.omap4"
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options SOC_ALLWINNER_A10
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options SOC_ALLWINNER_A13
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@ -53,6 +54,7 @@ options SOC_ALLWINNER_A83T
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options SOC_ALLWINNER_H3
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options SOC_BCM2836
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options SOC_TI_AM335X
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options SOC_OMAP4
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options SCHED_ULE # ULE scheduler
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options SMP # Enable multiple cores
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@ -80,6 +82,7 @@ device pmu
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# ARM Generic Timer
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device generic_timer
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device mpcore_timer
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# MMC/SD/SDIO Card slot support
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device sdhci # SD controller
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@ -129,6 +132,9 @@ device ti_i2c
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device am335x_pmic # AM335x Power Management IC (TPC65217)
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device am335x_rtc # RTC support (power management only)
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#define am335x_dmtpps # Pulse Per Second capture driver
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device twl # TI TWLX0X0/TPS659x0 Power Management
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device twl_vreg # twl voltage regulation
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device twl_clks # twl external clocks
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# GPIO
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device gpio
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@ -214,9 +220,12 @@ device ti_pruss
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# Mailbox support
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device ti_mbox
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# DMA controller
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device ti_sdma
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# Extensible Firmware Interface
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options EFI
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# Flattened Device Tree
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options FDT # Configure using FDT/DTB data
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makeoptions MODULES_EXTRA="dtb/allwinner dtb/am335x dtb/nvidia dtb/rpi"
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makeoptions MODULES_EXTRA="dtb/allwinner dtb/am335x dtb/nvidia dtb/rpi dtb/omap4"
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@ -293,7 +293,7 @@ const static struct ti_pinmux_padconf ti_padconf_devmap[] = {
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{ .ballname = NULL },
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};
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const struct ti_pinmux_device ti_pinmux_dev = {
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const struct ti_pinmux_device ti_am335x_pinmux_dev = {
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.padconf_muxmode_mask = 0x7,
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.padconf_sate_mask = 0x78,
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.padstate = ti_padstate_devmap,
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@ -42,4 +42,6 @@
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#define PADCONF_INPUT_PULLDOWN (RXACTIVE)
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#define PADCONF_INPUT_PULLUP_SLOW (PADCONF_INPUT_PULLUP | SLEWCTRL)
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extern const struct ti_pinmux_device ti_am335x_pinmux_dev;
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#endif /* AM335X_SCM_PADCONF_H */
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@ -295,7 +295,7 @@ const static struct ti_pinmux_padconf ti_padconf_devmap[] = {
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{ .ballname = NULL },
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};
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const struct ti_pinmux_device ti_pinmux_dev = {
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const struct ti_pinmux_device omap4_pinmux_dev = {
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.padconf_muxmode_mask = CONTROL_PADCONF_MUXMODE_MASK,
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.padconf_sate_mask = CONTROL_PADCONF_SATE_MASK,
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.padstate = ti_padstate_devmap,
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@ -78,4 +78,6 @@
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| CONTROL_PADCONF_OFF_PULL_ENABLE)
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#define PADCONF_PIN_OFF_WAKEUPENABLE CONTROL_PADCONF_WAKEUP_ENABLE
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extern const struct ti_pinmux_device omap4_pinmux_dev;
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#endif /* OMAP4_SCM_PADCONF_H */
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@ -139,7 +139,7 @@ static platform_method_t omap4_methods[] = {
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#endif
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PLATFORMMETHOD_END,
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};
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FDT_PLATFORM_DEF(omap4, "omap4", 0, "ti,omap4430", 0);
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FDT_PLATFORM_DEF(omap4, "omap4", 0, "ti,omap4430", 200);
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#endif
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#if defined(SOC_TI_AM335X)
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@ -54,6 +54,9 @@ __FBSDID("$FreeBSD$");
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <arm/ti/omap4/omap4_scm_padconf.h>
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#include <arm/ti/am335x/am335x_scm_padconf.h>
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#include <arm/ti/ti_cpuid.h>
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#include "ti_pinmux.h"
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struct pincfg {
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@ -85,7 +88,7 @@ static struct ti_pinmux_softc *ti_pinmux_sc;
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* files and is specific to the given SoC platform. Each entry in the array
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* corresponds to an individual pin.
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*/
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extern const struct ti_pinmux_device ti_pinmux_dev;
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static const struct ti_pinmux_device *ti_pinmux_dev;
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/**
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@ -101,7 +104,7 @@ ti_pinmux_padconf_from_name(const char *ballname)
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{
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const struct ti_pinmux_padconf *padconf;
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padconf = ti_pinmux_dev.padconf;
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padconf = ti_pinmux_dev->padconf;
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while (padconf->ballname != NULL) {
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if (strcmp(ballname, padconf->ballname) == 0)
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return(padconf);
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@ -134,7 +137,7 @@ ti_pinmux_padconf_set_internal(struct ti_pinmux_softc *sc,
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uint16_t reg_val;
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/* populate the new value for the PADCONF register */
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reg_val = (uint16_t)(state & ti_pinmux_dev.padconf_sate_mask);
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reg_val = (uint16_t)(state & ti_pinmux_dev->padconf_sate_mask);
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/* find the new mode requested */
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for (mode = 0; mode < 8; mode++) {
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@ -151,7 +154,7 @@ ti_pinmux_padconf_set_internal(struct ti_pinmux_softc *sc,
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}
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/* set the mux mode */
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reg_val |= (uint16_t)(mode & ti_pinmux_dev.padconf_muxmode_mask);
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reg_val |= (uint16_t)(mode & ti_pinmux_dev->padconf_muxmode_mask);
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if (bootverbose)
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device_printf(sc->sc_dev, "setting internal %x for %s\n",
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@ -226,11 +229,11 @@ ti_pinmux_padconf_get(const char *padname, const char **muxmode,
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/* save the state */
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if (state)
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*state = (reg_val & ti_pinmux_dev.padconf_sate_mask);
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*state = (reg_val & ti_pinmux_dev->padconf_sate_mask);
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/* save the mode */
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if (muxmode)
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*muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev.padconf_muxmode_mask)];
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*muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev->padconf_muxmode_mask)];
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return (0);
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}
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@ -259,7 +262,7 @@ ti_pinmux_padconf_set_gpiomode(uint32_t gpio, unsigned int state)
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return (ENXIO);
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/* find the gpio pin in the padconf array */
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padconf = ti_pinmux_dev.padconf;
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padconf = ti_pinmux_dev->padconf;
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while (padconf->ballname != NULL) {
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if (padconf->gpio_pin == gpio)
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break;
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@ -269,10 +272,10 @@ ti_pinmux_padconf_set_gpiomode(uint32_t gpio, unsigned int state)
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return (EINVAL);
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/* populate the new value for the PADCONF register */
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reg_val = (uint16_t)(state & ti_pinmux_dev.padconf_sate_mask);
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reg_val = (uint16_t)(state & ti_pinmux_dev->padconf_sate_mask);
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/* set the mux mode */
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reg_val |= (uint16_t)(padconf->gpio_mode & ti_pinmux_dev.padconf_muxmode_mask);
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reg_val |= (uint16_t)(padconf->gpio_mode & ti_pinmux_dev->padconf_muxmode_mask);
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/* write the register value (16-bit writes) */
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ti_pinmux_write_2(ti_pinmux_sc, padconf->reg_off, reg_val);
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@ -304,7 +307,7 @@ ti_pinmux_padconf_get_gpiomode(uint32_t gpio, unsigned int *state)
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return (ENXIO);
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/* find the gpio pin in the padconf array */
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padconf = ti_pinmux_dev.padconf;
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padconf = ti_pinmux_dev->padconf;
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while (padconf->ballname != NULL) {
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if (padconf->gpio_pin == gpio)
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break;
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@ -317,12 +320,12 @@ ti_pinmux_padconf_get_gpiomode(uint32_t gpio, unsigned int *state)
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reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off);
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/* check to make sure the pins is configured as GPIO in the first state */
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if ((reg_val & ti_pinmux_dev.padconf_muxmode_mask) != padconf->gpio_mode)
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if ((reg_val & ti_pinmux_dev->padconf_muxmode_mask) != padconf->gpio_mode)
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return (EINVAL);
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/* read and store the reset of the state, i.e. pull-up, pull-down, etc */
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if (state)
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*state = (reg_val & ti_pinmux_dev.padconf_sate_mask);
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*state = (reg_val & ti_pinmux_dev->padconf_sate_mask);
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return (0);
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}
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@ -381,6 +384,22 @@ ti_pinmux_probe(device_t dev)
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__func__);
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return (EEXIST);
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}
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switch (ti_chip()) {
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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ti_pinmux_dev = &omap4_pinmux_dev;
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break;
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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ti_pinmux_dev = &ti_am335x_pinmux_dev;
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break;
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#endif
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default:
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printf("Unknown CPU in pinmux\n");
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return (ENXIO);
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}
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device_set_desc(dev, "TI Pinmux Module");
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return (BUS_PROBE_DEFAULT);
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