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Pre 4.0 tidy up.

Browse Source 
Collect together the components of several drivers and export eisa from
the i386-only area (It's not, it's on some alphas too).  The code hasn't
been updated to work on the Alpha yet, but that can come later.

Repository copies were done a while ago.
Moving these now keeps them in consistant place across the 4.x series
as the newbusification progresses.

Submitted by:   mdodd
This commit is contained in:
Peter Wemm 2000-01-14 07:14:17 +00:00
parent cfc5d9f44e
commit c5191a983c
34 changed files with 36 additions and 10166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
sys/conf/files
View File

@ -93,9 +93,13 @@ ddb/db_trap.c optional ddb
ddb/db_variables.c optional ddb
ddb/db_watch.c optional ddb
ddb/db_write_cmd.c optional ddb
dev/advansys/adv_eisa.c optional adv eisa
dev/advansys/adv_isa.c optional adv isa
dev/advansys/adv_pci.c optional adv pci
dev/advansys/advansys.c optional adv
dev/advansys/advlib.c optional adv
dev/advansys/advmcode.c optional adv
dev/advansys/adw_pci.c optional adw pci
dev/advansys/adwcam.c optional adw
dev/advansys/adwlib.c optional adw
dev/advansys/adwmcode.c optional adw
@ -105,8 +109,13 @@ dev/amr/amr.c optional amr
dev/aha/aha.c optional aha
dev/aha/aha_isa.c optional aha isa
dev/aha/aha_mca.c optional aha mca
dev/ahb/ahb.c optional ahb eisa
dev/aic/aic.c optional aic
dev/aic/aic_isa.c optional aic isa
dev/aic7xxx/ahc_eisa.c optional ahc eisa \
dependency "aic7xxx_reg.h $S/dev/aic7xxx/ahc_eisa.c"
dev/aic7xxx/ahc_pci.c optional ahc pci \
dependency "aic7xxx_reg.h $S/dev/aic7xxx/ahc_pci.c"
dev/aic7xxx/aic7xxx.c optional ahc \
dependency "aic7xxx_{reg,seq}.h"
dev/aic7xxx/93cx6.c optional ahc
@ -128,6 +137,7 @@ dev/ep/if_ep_eisa.c optional ep eisa
dev/ep/if_ep_mca.c optional ep mca
dev/ep/if_ep_pccard.c optional ep card
dev/en/midway.c optional en
dev/ex/if_ex.c optional ex
dev/hea/eni.c optional hea
dev/hea/eni_buffer.c optional hea
dev/hea/eni_globals.c optional hea
@ -205,10 +215,12 @@ power_if.h optional pccard \
clean "power_if.h"
dev/pcic/i82365.c optional pcic pccard
dev/pcic/i82365_isa.c optional pcic pccard
dev/pdq/pdq.c optional fea
dev/pdq/pdq_ifsubr.c optional fea
dev/pdq/pdq.c optional fpa
dev/pdq/pdq_ifsubr.c optional fpa
dev/pdq/if_fea.c optional fea eisa
dev/pdq/if_fpa.c optional fea pci
dev/pdq/pdq.c optional fea eisa
dev/pdq/pdq_ifsubr.c optional fea eisa
dev/pdq/pdq.c optional fpa pci
dev/pdq/pdq_ifsubr.c optional fpa pci
ppbus_if.o optional ppbus \
dependency "ppbus_if.c ppbus_if.h" \
compile-with "${NORMAL_C}" \
@ -306,6 +318,8 @@ dev/vinum/vinumstate.c optional vinum
dev/vinum/vinumutil.c optional vinum
dev/vn/vn.c optional vn
dev/vx/if_vx.c optional vx
dev/vx/if_vx_eisa.c optional vx eisa
dev/vx/if_vx_pci.c optional vx pci
dev/xe/if_xe.c optional xe
gnu/ext2fs/ext2_alloc.c optional ext2fs
gnu/ext2fs/ext2_balloc.c optional ext2fs
@ -764,10 +778,6 @@ pccard/pccard_nbk.c optional card
pccard/pcic.c optional pcic card
pci/amd.c optional amd
pci/pcic_p.c optional pcic pci
pci/adv_pci.c optional adv pci
pci/adw_pci.c optional adw pci
pci/ahc_pci.c optional ahc pci \
dependency "aic7xxx_reg.h $S/pci/ahc_pci.c"
dev/bktr/bktr_core.c optional bktr pci
dev/bktr/bktr_i2c.c optional bktr pci
dev/bktr/bktr_card.c optional bktr pci
@ -781,7 +791,6 @@ pci/if_ar_p.c optional ar pci
pci/if_dc.c optional dc
pci/if_de.c optional de
pci/if_en_pci.c optional en pci
pci/if_fpa.c optional fpa pci
pci/if_fxp.c optional fxp
pci/if_lnc_p.c optional lnc pci
pci/if_mn.c optional mn
@ -795,7 +804,6 @@ pci/if_ti.c optional ti
pci/if_tl.c optional tl
pci/if_tx.c optional tx
pci/if_vr.c optional vr
pci/if_vx_pci.c optional vx pci
pci/if_wb.c optional wb
pci/if_wx.c optional wx
pci/if_xl.c optional xl

11
sys/conf/files.i386
View File

@ -72,6 +72,7 @@ dev/ata/atapi-tape.c optional atapist
dev/ed/if_ed.c optional ed
dev/ed/if_ed_isa.c optional ed isa
dev/ed/if_ed_pccard.c optional ed card
dev/eisa/eisaconf.c optional eisa
dev/fb/fb.c optional fb
dev/fb/fb.c optional vga
dev/fb/splash.c optional splash
@ -131,13 +132,6 @@ gnu/i386/isa/dgb.c optional dgb
gnu/i386/isa/dgm.c optional dgm
gnu/i386/isa/sound/awe_wave.c optional awe
i386/apm/apm.c optional apm
i386/eisa/adv_eisa.c optional adv
i386/eisa/ahb.c optional ahb
i386/eisa/ahc_eisa.c optional eisa ahc \
dependency "aic7xxx_reg.h $S/i386/eisa/ahc_eisa.c"
i386/eisa/eisaconf.c optional eisa
i386/eisa/if_fea.c optional fea
i386/eisa/if_vx_eisa.c optional vx
i386/i386/atomic.c standard \
compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}"
i386/i386/autoconf.c standard
@ -199,7 +193,6 @@ i386/ibcs2/ibcs2_util.c optional ibcs2
i386/ibcs2/ibcs2_xenix.c optional ibcs2
i386/ibcs2/ibcs2_xenix_sysent.c optional ibcs2
i386/ibcs2/imgact_coff.c optional ibcs2
i386/isa/adv_isa.c optional adv
i386/isa/asc.c optional asc
i386/isa/atapi-cd.c optional wcd \
warning "The wcd driver is obsolete. Please use the atapicd driver!"
@ -219,9 +212,7 @@ i386/isa/if_ar.c optional ar
i386/isa/if_cs.c optional cs
i386/isa/if_cx.c optional cx
i386/isa/if_el.c optional el
i386/isa/if_ex.c optional ex
i386/isa/if_fe.c optional fe
i386/isa/if_ie.c optional ie
i386/isa/if_le.c optional le
i386/isa/if_lnc.c optional lnc
i386/isa/if_rdp.c optional rdp

11
sys/conf/files.pc98
View File

@ -66,6 +66,7 @@ dev/ata/atapi-all.c optional atapist
dev/ata/atapi-cd.c optional atapicd
dev/ata/atapi-fd.c optional atapifd
dev/ata/atapi-tape.c optional atapist
dev/eisa/eisaconf.c optional eisa
dev/fb/fb.c optional fb
dev/fb/fb.c optional gdc
dev/fb/splash.c optional splash
@ -114,13 +115,6 @@ gnu/i386/isa/dgb.c optional dgb
gnu/i386/isa/dgm.c optional dgm
gnu/i386/isa/sound/awe_wave.c optional awe
i386/apm/apm.c optional apm
#i386/eisa/adv_eisa.c optional adv
i386/eisa/ahb.c optional ahb
i386/eisa/ahc_eisa.c optional eisa ahc \
dependency "aic7xxx_reg.h $S/i386/eisa/ahc_eisa.c"
i386/eisa/eisaconf.c optional eisa
i386/eisa/if_fea.c optional fea
i386/eisa/if_vx_eisa.c optional vx
i386/i386/atomic.c standard \
compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}"
i386/i386/autoconf.c standard
@ -187,7 +181,6 @@ i386/isa/bs/bs.c optional bs
i386/isa/bs/bsfunc.c optional bs
i386/isa/bs/bshw.c optional bs
i386/isa/bs/bsif.c optional bs
#i386/isa/adv_isa.c optional adv
i386/isa/asc.c optional asc
i386/isa/atapi-cd.c optional wcd
pc98/pc98/atapi.c optional wdc
@ -207,9 +200,7 @@ i386/isa/if_cs.c optional cs
i386/isa/if_cx.c optional cx
pc98/pc98/if_ed.c optional ed
i386/isa/if_el.c optional el
i386/isa/if_ex.c optional ex
i386/isa/if_fe.c optional fe
i386/isa/if_ie.c optional ie
i386/isa/if_le.c optional le
i386/isa/if_lnc.c optional lnc
i386/isa/if_rdp.c optional rdp

2
sys/dev/advansys/adv_eisa.c
View File

@ -49,7 +49,7 @@
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <dev/advansys/advansys.h>

4
sys/dev/ahb/ahb.c
View File

@ -53,9 +53,9 @@
#include <cam/scsi/scsi_message.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <i386/eisa/ahbreg.h>
#include <dev/ahb/ahbreg.h>
#define ccb_ecb_ptr spriv_ptr0
#define ccb_ahb_ptr spriv_ptr1

2
sys/dev/aic7xxx/ahc_eisa.c
View File

@ -43,7 +43,7 @@
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>

2
sys/dev/buslogic/bt_eisa.c
View File

@ -43,7 +43,7 @@
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <dev/buslogic/btreg.h>

2
sys/dev/dpt/dpt_eisa.c
View File

@ -58,7 +58,7 @@
#include <dev/dpt/dpt.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <machine/clock.h>

2
sys/dev/eisa/eisaconf.c
View File

@ -46,7 +46,7 @@
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
typedef struct resvaddr {
u_long addr; /* start address */

2
sys/dev/ep/if_ep_eisa.c
View File

@ -40,7 +40,7 @@
#include <machine/clock.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <dev/ep/if_epreg.h>
#include <dev/ep/if_epvar.h>

2
sys/dev/ex/if_ex.c
View File

@ -68,7 +68,7 @@
#include <isa/isavar.h>
#include <isa/pnpvar.h>
#include <i386/isa/if_exreg.h>
#include <dev/ex/if_exreg.h>
#ifdef EXDEBUG
# define Start_End 1

6
sys/dev/ie/if_ie.c
View File

@ -136,9 +136,9 @@ iomem and and with 0xffff.
#include <i386/isa/isa_device.h>
#include <i386/isa/ic/i82586.h>
#include <i386/isa/icu.h>
#include <i386/isa/if_iereg.h>
#include <i386/isa/if_ie507.h>
#include <i386/isa/if_iee16.h>
#include <dev/ie/if_iereg.h>
#include <dev/ie/if_ie507.h>
#include <dev/ie/if_iee16.h>
#include <i386/isa/elink.h>
#include <net/bpf.h>

2
sys/dev/pdq/if_fea.c
View File

@ -43,7 +43,7 @@
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <dev/pdq/pdqvar.h>
#include <dev/pdq/pdqreg.h>

3
sys/dev/vx/if_vx_eisa.c
View File

@ -26,6 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "eisa.h"
@ -48,7 +49,7 @@
#include <net/if.h>
#include <net/if_arp.h>
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
#include <dev/vx/if_vxreg.h>

352
sys/i386/eisa/adv_eisa.c
View File

@ -1,352 +0,0 @@
/*
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* Single Channel Products:
* ABP742 - Bus-Master EISA (240 CDB)
*
* Dual Channel Products:
* ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
*
* Copyright (c) 1997 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "eisa.h"
#if NEISA > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/advansys/advansys.h>
#define EISA_DEVICE_ID_ADVANSYS_740 0x04507400
#define EISA_DEVICE_ID_ADVANSYS_750 0x04507500
#define ADV_EISA_SLOT_OFFSET 0xc00
#define ADV_EISA_OFFSET_CHAN1 0x30
#define ADV_EISA_OFFSET_CHAN2 0x50
#define ADV_EISA_IOSIZE 0x100
#define ADV_EISA_ROM_BIOS_ADDR_REG 0x86
#define ADV_EISA_IRQ_BURST_LEN_REG 0x87
#define ADV_EISA_IRQ_MASK 0x07
#define ADV_EISA_IRQ_10 0x00
#define ADV_EISA_IRQ_11 0x01
#define ADV_EISA_IRQ_12 0x02
#define ADV_EISA_IRQ_14 0x04
#define ADV_EISA_IRQ_15 0x05
#define ADV_EISA_MAX_DMA_ADDR (0x07FFFFFFL)
#define ADV_EISA_MAX_DMA_COUNT (0x07FFFFFFL)
/*
* The overrun buffer shared amongst all EISA adapters.
*/
static u_int8_t* overrun_buf;
static bus_dma_tag_t overrun_dmat;
static bus_dmamap_t overrun_dmamap;
static bus_addr_t overrun_physbase;
static const char *adveisamatch(eisa_id_t type);
static const char*
adveisamatch(eisa_id_t type)
{
switch (type & ~0xF) {
case EISA_DEVICE_ID_ADVANSYS_740:
return ("AdvanSys ABP-740/742 SCSI adapter");
break;
case EISA_DEVICE_ID_ADVANSYS_750:
return ("AdvanSys ABP-750/752 SCSI adapter");
break;
default:
break;
}
return (NULL);
}
static int
adveisaprobe(device_t dev)
{
const char *desc;
u_int32_t iobase;
u_int8_t irq;
desc = adveisamatch(eisa_get_id(dev));
if (!desc)
return (ENXIO);
device_set_desc(dev, desc);
iobase = (eisa_get_slot(dev) * EISA_SLOT_SIZE)
+ ADV_EISA_SLOT_OFFSET;
eisa_add_iospace(dev, iobase, ADV_EISA_IOSIZE, RESVADDR_NONE);
irq = inb(iobase + ADV_EISA_IRQ_BURST_LEN_REG);
irq &= ADV_EISA_IRQ_MASK;
switch (irq) {
case 0:
case 1:
case 2:
case 4:
case 5:
break;
default:
printf("adv at slot %d: illegal "
"irq setting %d\n", eisa_get_slot(dev),
irq);
return ENXIO;
}
eisa_add_intr(dev, irq + 10, EISA_TRIGGER_LEVEL);
return 0;
}
static int
adveisaattach(device_t dev)
{
struct adv_softc *adv;
struct adv_softc *adv_b;
struct resource *io;
struct resource *irq;
int unit = device_get_unit(dev);
int rid, error;
void *ih;
adv_b = NULL;
rid = 0;
io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
0, ~0, 1, RF_ACTIVE);
if (!io) {
device_printf(dev, "No I/O space?!\n");
return ENOMEM;
}
rid = 0;
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
if (!irq) {
device_printf(dev, "No irq?!\n");
bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
return ENOMEM;
}
switch (eisa_get_id(dev) & ~0xF) {
case EISA_DEVICE_ID_ADVANSYS_750:
adv_b = adv_alloc(unit, rman_get_bustag(io),
rman_get_bushandle(io) + ADV_EISA_OFFSET_CHAN2);
if (adv_b == NULL)
goto bad;
/*
* Allocate a parent dmatag for all tags created
* by the MI portions of the advansys driver
*/
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
/*boundary*/0,
/*lowaddr*/ADV_EISA_MAX_DMA_ADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/BUS_SPACE_UNRESTRICTED,
/*maxsegsz*/ADV_EISA_MAX_DMA_COUNT,
/*flags*/0,
&adv_b->parent_dmat);
if (error != 0) {
printf("%s: Could not allocate DMA tag - error %d\n",
adv_name(adv_b), error);
adv_free(adv_b);
goto bad;
}
adv_b->init_level++;
/* FALLTHROUGH */
case EISA_DEVICE_ID_ADVANSYS_740:
adv = adv_alloc(unit, rman_get_bustag(io),
rman_get_bushandle(io) + ADV_EISA_OFFSET_CHAN1);
if (adv == NULL) {
if (adv_b != NULL)
adv_free(adv_b);
goto bad;
}
/*
* Allocate a parent dmatag for all tags created
* by the MI portions of the advansys driver
*/
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
/*boundary*/0,
/*lowaddr*/ADV_EISA_MAX_DMA_ADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/BUS_SPACE_UNRESTRICTED,
/*maxsegsz*/ADV_EISA_MAX_DMA_COUNT,
/*flags*/0,
&adv->parent_dmat);
if (error != 0) {
printf("%s: Could not allocate DMA tag - error %d\n",
adv_name(adv), error);
adv_free(adv);
goto bad;
}
adv->init_level++;
break;
default:
printf("adveisaattach: Unknown device type!\n");
goto bad;
break;
}
if (overrun_buf == NULL) {
/* Need to allocate our overrun buffer */
if (bus_dma_tag_create(adv->parent_dmat,
/*alignment*/8,
/*boundary*/0,
ADV_EISA_MAX_DMA_ADDR,
BUS_SPACE_MAXADDR,
/*filter*/NULL,
/*filterarg*/NULL,
ADV_OVERRUN_BSIZE,
/*nsegments*/1,
BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0,
&overrun_dmat) != 0) {
adv_free(adv);
goto bad;
}
if (bus_dmamem_alloc(overrun_dmat,
(void **)&overrun_buf,
BUS_DMA_NOWAIT,
&overrun_dmamap) != 0) {
bus_dma_tag_destroy(overrun_dmat);
adv_free(adv);
goto bad;
}
/* And permanently map it in */
bus_dmamap_load(overrun_dmat, overrun_dmamap,
overrun_buf, ADV_OVERRUN_BSIZE,
adv_map, &overrun_physbase,
/*flags*/0);
}
/*
* Now that we know we own the resources we need, do the
* card initialization.
*/
/*
* Stop the chip.
*/
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
adv->chip_version = EISA_REVISION_ID(eisa_get_id(dev))
+ ADV_CHIP_MIN_VER_EISA - 1;
if (adv_init(adv) != 0) {
adv_free(adv);
if (adv_b != NULL)
adv_free(adv_b);
return(-1);
}
adv->max_dma_count = ADV_EISA_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_EISA_MAX_DMA_ADDR;
if (adv_b != NULL) {
/*
* Stop the chip.
*/
ADV_OUTB(adv_b, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv_b, ADV_CHIP_STATUS, 0);
adv_b->chip_version = EISA_REVISION_ID(eisa_get_id(dev))
+ ADV_CHIP_MIN_VER_EISA - 1;
if (adv_init(adv_b) != 0) {
adv_free(adv_b);
} else {
adv_b->max_dma_count = ADV_EISA_MAX_DMA_COUNT;
adv_b->max_dma_addr = ADV_EISA_MAX_DMA_ADDR;
}
}
/*
* Enable our interrupt handler.
*/
bus_setup_intr(dev, irq, INTR_TYPE_CAM, adv_intr, adv, &ih);
/* Attach sub-devices - always succeeds */
adv_attach(adv);
if (adv_b != NULL)
adv_attach(adv_b);
return 0;
bad:
bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
return -1;
}
static device_method_t adv_eisa_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, adveisaprobe),
DEVMETHOD(device_attach, adveisaattach),
{ 0, 0 }
};
static driver_t adv_eisa_driver = {
"adv",
adv_eisa_methods,
1, /* unused */
};
static devclass_t adv_devclass;
DRIVER_MODULE(adv, eisa, adv_eisa_driver, adv_devclass, 0, 0);
#endif /* NEISA > 0 */

1364
sys/i386/eisa/ahb.c
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283
sys/i386/eisa/ahbreg.h
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@ -1,283 +0,0 @@
/*
* Hardware structure definitions for the Adaptec 174X CAM SCSI device driver.
*
* Copyright (c) 1998 Justin T. Gibbs
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/* Resource Constatns */
#define AHB_NECB 64
#define AHB_NSEG 32
/* AHA1740 EISA ID, IO port range size, and offset from slot base */
#define EISA_DEVICE_ID_ADAPTEC_1740 0x04900000
#define AHB_EISA_IOSIZE 0x100
#define AHB_EISA_SLOT_OFFSET 0xc00
/* AHA1740 EISA board control registers (Offset from slot base) */
#define EBCTRL 0x084
#define CDEN 0x01
/*
* AHA1740 EISA board mode registers (Offset from slot base)
*/
#define PORTADDR 0x0C0
#define PORTADDR_ENHANCED 0x80
#define BIOSADDR 0x0C1
#define INTDEF 0x0C2
#define INT9 0x00
#define INT10 0x01
#define INT11 0x02
#define INT12 0x03
#define INT14 0x05
#define INT15 0x06
#define INTLEVEL 0x08
#define INTEN 0x10
#define SCSIDEF 0x0C3
#define HSCSIID 0x0F /* our SCSI ID */
#define RSTBUS 0x10
#define BUSDEF 0x0C4
#define B0uS 0x00 /* give up bus immediatly */
#define B4uS 0x01 /* delay 4uSec. */
#define B8uS 0x02 /* delay 8uSec. */
#define RESV0 0x0C5
#define RESV1 0x0C6
#define EXTENDED_TRANS 0x01
#define RESV2 0x0C7
/*
* AHA1740 ENHANCED mode mailbox control regs (Offset from slot base)
*/
#define MBOXOUT0 0x0D0
#define MBOXOUT1 0x0D1
#define MBOXOUT2 0x0D2
#define MBOXOUT3 0x0D3
#define ATTN 0x0D4
#define ATTN_TARGMASK 0x0F
#define ATTN_IMMED 0x10
#define ATTN_STARTECB 0x40
#define ATTN_ABORTECB 0x50
#define ATTN_TARG_RESET 0x80
#define CONTROL 0x0D5
#define CNTRL_SET_HRDY 0x20
#define CNTRL_CLRINT 0x40
#define CNTRL_HARD_RST 0x80
#define INTSTAT 0x0D6
#define INTSTAT_TARGET_MASK 0x0F
#define INTSTAT_MASK 0xF0
#define INTSTAT_ECB_OK 0x10 /* ECB Completed w/out error */
#define INTSTAT_ECB_CMPWRETRY 0x50 /* ECB Completed w/retries */
#define INTSTAT_HW_ERR 0x70 /* Adapter Hardware Failure */
#define INTSTAT_IMMED_OK 0xA0 /* Immediate command complete */
#define INTSTAT_ECB_CMPWERR 0xC0 /* ECB Completed w/error */
#define INTSTAT_AEN_OCCURED 0xD0 /* Async Event Notification */
#define INTSTAT_IMMED_ERR 0xE0 /* Immediate command failed */
#define HOSTSTAT 0x0D7
#define HOSTSTAT_MBOX_EMPTY 0x04
#define HOSTSTAT_INTPEND 0x02
#define HOSTSTAT_BUSY 0x01
#define MBOXIN0 0x0D8
#define MBOXIN1 0x0D9
#define MBOXIN2 0x0DA
#define MBOXIN3 0x0DB
#define STATUS2 0x0DC
#define STATUS2_HOST_READY 0x01
typedef enum {
IMMED_RESET = 0x000080,
IMMED_DEVICE_CLEAR_QUEUE = 0x000480,
IMMED_ADAPTER_CLEAR_QUEUE = 0x000880,
IMMED_RESUME = 0x200090
} immed_cmd;
struct ecb_status {
/* Status Flags */
u_int16_t no_error :1, /* Completed with no error */
data_underrun :1,
:1,
ha_queue_full :1,
spec_check :1,
data_overrun :1,
chain_halted :1,
intr_issued :1,
status_avail :1, /* status bytes 14-31 are valid */
sense_stored :1,
:1,
init_requied :1,
major_error :1,
:1,
extended_ca :1,
:1;
/* Host Status */
u_int8_t ha_status;
u_int8_t scsi_status;
int32_t resid_count;
u_int32_t resid_addr;
u_int16_t addit_status;
u_int8_t sense_len;
u_int8_t unused[9];
u_int8_t cdb[6];
};
typedef enum {
HS_OK = 0x00,
HS_CMD_ABORTED_HOST = 0x04,
HS_CMD_ABORTED_ADAPTER = 0x05,
HS_FIRMWARE_LOAD_REQ = 0x08,
HS_TARGET_NOT_ASSIGNED = 0x0A,
HS_SEL_TIMEOUT = 0x11,
HS_DATA_RUN_ERR = 0x12,
HS_UNEXPECTED_BUSFREE = 0x13,
HS_INVALID_PHASE = 0x14,
HS_INVALID_OPCODE = 0x16,
HS_INVALID_CMD_LINK = 0x17,
HS_INVALID_ECB_PARAM = 0x18,
HS_DUP_TCB_RECEIVED = 0x19,
HS_REQUEST_SENSE_FAILED = 0x1A,
HS_TAG_MSG_REJECTED = 0x1C,
HS_HARDWARE_ERR = 0x20,
HS_ATN_TARGET_FAILED = 0x21,
HS_SCSI_RESET_ADAPTER = 0x22,
HS_SCSI_RESET_INCOMING = 0x23,
HS_PROGRAM_CKSUM_ERROR = 0x80
} host_status;
typedef enum {
ECBOP_NOP = 0x00,
ECBOP_INITIATOR_SCSI_CMD = 0x01,
ECBOP_RUN_DIAGNOSTICS = 0x05,
ECBOP_INITIALIZE_SCSI = 0x06, /* Set syncrate/disc/parity */
ECBOP_READ_SENSE = 0x08,
ECBOP_DOWNLOAD_FIRMWARE = 0x09,
ECBOP_READ_HA_INQDATA = 0x0a,
ECBOP_TARGET_SCSI_CMD = 0x10
} ecb_op;
struct ha_inquiry_data {
struct scsi_inquiry_data scsi_data;
u_int8_t release_date[8];
u_int8_t release_time[8];
u_int16_t firmware_cksum;
u_int16_t reserved;
u_int16_t target_data[16];
};
struct hardware_ecb {
u_int16_t opcode;
u_int16_t flag_word1;
#define FW1_LINKED_CMD 0x0001
#define FW1_DISABLE_INTR 0x0080
#define FW1_SUPPRESS_URUN_ERR 0x0400
#define FW1_SG_ECB 0x1000
#define FW1_ERR_STATUS_BLK_ONLY 0x4000
#define FW1_AUTO_REQUEST_SENSE 0x8000
u_int16_t flag_word2;
#define FW2_LUN_MASK 0x0007
#define FW2_TAG_ENB 0x0008
#define FW2_TAG_TYPE 0x0030
#define FW2_TAG_TYPE_SHIFT 4
#define FW2_DISABLE_DISC 0x0040
#define FW2_CHECK_DATA_DIR 0x0100
#define FW2_DATA_DIR_IN 0x0200
#define FW2_SUPRESS_TRANSFER 0x0400
#define FW2_CALC_CKSUM 0x0800
#define FW2_RECOVERY_ECB 0x4000
#define FW2_NO_RETRY_ON_BUSY 0x8000
u_int16_t reserved;
u_int32_t data_ptr;
u_int32_t data_len;
u_int32_t status_ptr;
u_int32_t link_ptr;
u_int32_t reserved2;
u_int32_t sense_ptr;
u_int8_t sense_len;
u_int8_t cdb_len;
u_int16_t cksum;
u_int8_t cdb[12];
};
typedef struct {
u_int32_t addr;
u_int32_t len;
} ahb_sg_t;
typedef enum {
ECB_FREE = 0x0,
ECB_ACTIVE = 0x1,
ECB_DEVICE_RESET = 0x2,
ECB_SCSIBUS_RESET = 0x4,
ECB_RELEASE_SIMQ = 0x8
} ecb_state;
struct ecb {
struct hardware_ecb hecb;
struct ecb_status status;
struct scsi_sense_data sense;
ahb_sg_t sg_list[AHB_NSEG];
SLIST_ENTRY(ecb) links;
ecb_state state;
union ccb *ccb;
bus_dmamap_t dmamap;
};
struct ahb_softc {
bus_space_tag_t tag;
bus_space_handle_t bsh;
struct cam_sim *sim;
struct cam_path *path;
SLIST_HEAD(,ecb) free_ecbs;
LIST_HEAD(,ccb_hdr) pending_ccbs;
struct ecb *ecb_array;
u_int32_t ecb_physbase;
bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
bus_dma_tag_t ecb_dmat; /* dmat for our ecb array */
bus_dmamap_t ecb_dmamap;
volatile u_int32_t immed_cmd;
struct ecb *immed_ecb;
struct ha_inquiry_data *ha_inq_data;
u_int32_t ha_inq_physbase;
u_long unit;
u_int init_level;
u_int scsi_id;
u_int num_ecbs;
u_int extended_trans;
u_int8_t disc_permitted;
u_int8_t tags_permitted;
};

478
sys/i386/eisa/ahc_eisa.c
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@ -1,478 +0,0 @@
/*
* Product specific probe and attach routines for:
* 27/284X and aic7770 motherboard SCSI controllers
*
* Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "eisa.h"
#if NEISA > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/scsi/scsi_all.h>
#include <dev/aic7xxx/aic7xxx.h>
#include <dev/aic7xxx/93cx6.h>
#include <aic7xxx_reg.h>
#define EISA_DEVICE_ID_ADAPTEC_AIC7770 0x04907770
#define EISA_DEVICE_ID_ADAPTEC_274x 0x04907771
#define EISA_DEVICE_ID_ADAPTEC_284xB 0x04907756 /* BIOS enabled */
#define EISA_DEVICE_ID_ADAPTEC_284x 0x04907757 /* BIOS disabled*/
#define AHC_EISA_SLOT_OFFSET 0xc00
#define AHC_EISA_IOSIZE 0x100
#define INTDEF 0x5cul /* Interrupt Definition Register */
static void aha2840_load_seeprom(struct ahc_softc *ahc);
static const char *aic7770_match(eisa_id_t type);
static const char*
aic7770_match(eisa_id_t type)
{
switch (type) {
case EISA_DEVICE_ID_ADAPTEC_AIC7770:
return ("Adaptec aic7770 SCSI host adapter");
break;
case EISA_DEVICE_ID_ADAPTEC_274x:
return ("Adaptec 274X SCSI host adapter");
break;
case EISA_DEVICE_ID_ADAPTEC_284xB:
case EISA_DEVICE_ID_ADAPTEC_284x:
return ("Adaptec 284X SCSI host adapter");
break;
default:
break;
}
return (NULL);
}
static int
aic7770_probe(device_t dev)
{
const char *desc;
u_int32_t iobase;
u_int32_t irq;
u_int8_t intdef;
u_int8_t hcntrl;
int shared;
desc = aic7770_match(eisa_get_id(dev));
if (!desc)
return (ENXIO);
device_set_desc(dev, desc);
iobase = (eisa_get_slot(dev) * EISA_SLOT_SIZE)
+ AHC_EISA_SLOT_OFFSET;
/* Pause the card preseving the IRQ type */
hcntrl = inb(iobase + HCNTRL) & IRQMS;
outb(iobase + HCNTRL, hcntrl | PAUSE);
eisa_add_iospace(dev, iobase, AHC_EISA_IOSIZE, RESVADDR_NONE);
intdef = inb(INTDEF + iobase);
shared = (intdef & 0x80) ? EISA_TRIGGER_EDGE : EISA_TRIGGER_LEVEL;
irq = intdef & 0xf;
switch (irq) {
case 9:
case 10:
case 11:
case 12:
case 14:
case 15:
break;
default:
printf("aic7770 at slot %d: illegal "
"irq setting %d\n", eisa_get_slot(dev),
intdef);
irq = 0;
break;
}
if (irq == 0)
return ENXIO;
eisa_add_intr(dev, irq, shared);
return 0;
}
static int
aic7770_attach(device_t dev)
{
ahc_chip chip;
bus_dma_tag_t parent_dmat;
struct ahc_softc *ahc;
struct resource *io;
int error, rid;
rid = 0;
io = NULL;
ahc = NULL;
switch (eisa_get_id(dev)) {
case EISA_DEVICE_ID_ADAPTEC_274x:
case EISA_DEVICE_ID_ADAPTEC_AIC7770:
chip = AHC_AIC7770|AHC_EISA;
break;
case EISA_DEVICE_ID_ADAPTEC_284xB:
case EISA_DEVICE_ID_ADAPTEC_284x:
chip = AHC_AIC7770|AHC_VL;
break;
default:
printf("aic7770_attach: Unknown device type!\n");
goto bad;
}
/* XXX Should be a child of the EISA bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
/*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/MAXBSIZE,
/*nsegments*/AHC_NSEG,
/*maxsegsz*/AHC_MAXTRANSFER_SIZE,
/*flags*/BUS_DMA_ALLOCNOW, &parent_dmat);
if (error != 0) {
printf("ahc_eisa_attach: Could not allocate DMA tag "
"- error %d\n", error);
goto bad;
}
io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
0, ~0, 1, RF_ACTIVE);
if (!io) {
device_printf(dev, "No I/O space?!\n");
return ENOMEM;
}
if (!(ahc = ahc_alloc(dev, io, SYS_RES_IOPORT, rid,
parent_dmat, chip, AHC_AIC7770_FE, AHC_FNONE,
NULL)))
goto bad;
io = NULL;
ahc->channel = 'A';
ahc->channel_b = 'B';
if (ahc_reset(ahc) != 0) {
goto bad;
}
/*
* The IRQMS bit enables level sensitive interrupts. Only allow
* IRQ sharing if it's set.
*/
rid = 0;
ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
0, ~0, 1, RF_ACTIVE);
if (ahc->irq == NULL) {
device_printf(dev, "Can't allocate interrupt\n");
goto bad;
}
ahc->irq_res_type = SYS_RES_IRQ;
/*
* Tell the user what type of interrupts we're using.
* usefull for debugging irq problems
*/
if (bootverbose) {
printf("%s: Using %s Interrupts\n",
ahc_name(ahc),
ahc->pause & IRQMS ?
"Level Sensitive" : "Edge Triggered");
}
/*
* Now that we know we own the resources we need, do the
* card initialization.
*
* First, the aic7770 card specific setup.
*/
switch (chip & (AHC_EISA|AHC_VL)) {
case AHC_EISA:
{
u_int biosctrl;
u_int scsiconf;
u_int scsiconf1;
#if DEBUG
int i;
#endif
biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL);
scsiconf = ahc_inb(ahc, SCSICONF);
scsiconf1 = ahc_inb(ahc, SCSICONF + 1);
#if DEBUG
for (i = TARG_SCSIRATE; i <= HA_274_BIOSCTRL; i+=8) {
printf("0x%x, 0x%x, 0x%x, 0x%x, "
"0x%x, 0x%x, 0x%x, 0x%x\n",
ahc_inb(ahc, i),
ahc_inb(ahc, i+1),
ahc_inb(ahc, i+2),
ahc_inb(ahc, i+3),
ahc_inb(ahc, i+4),
ahc_inb(ahc, i+5),
ahc_inb(ahc, i+6),
ahc_inb(ahc, i+7));
}
#endif
/* Get the primary channel information */
if ((biosctrl & CHANNEL_B_PRIMARY) != 0)
ahc->flags |= AHC_CHANNEL_B_PRIMARY;
if ((biosctrl & BIOSMODE) == BIOSDISABLED) {
ahc->flags |= AHC_USEDEFAULTS;
} else {
if ((ahc->features & AHC_WIDE) != 0) {
ahc->our_id = scsiconf1 & HWSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
} else {
ahc->our_id = scsiconf & HSCSIID;
ahc->our_id_b = scsiconf1 & HSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
if (scsiconf1 & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_B;
}
}
/*
* We have no way to tell, so assume extended
* translation is enabled.
*/
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
break;
}
case AHC_VL:
{
aha2840_load_seeprom(ahc);
break;
}
default:
break;
}
/*
* See if we have a Rev E or higher aic7770. Anything below a
* Rev E will have a R/O autoflush disable configuration bit.
*/
{
char *id_string;
u_int8_t sblkctl;
u_int8_t sblkctl_orig;
sblkctl_orig = ahc_inb(ahc, SBLKCTL);
sblkctl = sblkctl_orig ^ AUTOFLUSHDIS;
ahc_outb(ahc, SBLKCTL, sblkctl);
sblkctl = ahc_inb(ahc, SBLKCTL);
if (sblkctl != sblkctl_orig) {
id_string = "aic7770 >= Rev E, ";
/*
* Ensure autoflush is enabled
*/
sblkctl &= ~AUTOFLUSHDIS;
ahc_outb(ahc, SBLKCTL, sblkctl);
} else
id_string = "aic7770 <= Rev C, ";
printf("%s: %s", ahc_name(ahc), id_string);
}
/* Setup the FIFO threshold and the bus off time */
{
u_int8_t hostconf = ahc_inb(ahc, HOSTCONF);
ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
}
/*
* Generic aic7xxx initialization.
*/
if (ahc_init(ahc)) {
/*
* The board's IRQ line is not yet enabled so it's safe
* to release the irq.
*/
goto bad;
}
/*
* Enable the board's BUS drivers
*/
ahc_outb(ahc, BCTL, ENABLE);
/* Attach sub-devices - always succeeds */
ahc_attach(ahc);
return 0;
bad:
if (ahc != NULL)
ahc_free(ahc);
if (io != NULL)
bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
return -1;
}
/*
* Read the 284x SEEPROM.
*/
static void
aha2840_load_seeprom(struct ahc_softc *ahc)
{
struct seeprom_descriptor sd;
struct seeprom_config sc;
u_int16_t checksum = 0;
u_int8_t scsi_conf;
int have_seeprom;
sd.sd_tag = ahc->tag;
sd.sd_bsh = ahc->bsh;
sd.sd_control_offset = SEECTL_2840;
sd.sd_status_offset = STATUS_2840;
sd.sd_dataout_offset = STATUS_2840;
sd.sd_chip = C46;
sd.sd_MS = 0;
sd.sd_RDY = EEPROM_TF;
sd.sd_CS = CS_2840;
sd.sd_CK = CK_2840;
sd.sd_DO = DO_2840;
sd.sd_DI = DI_2840;
if (bootverbose)
printf("%s: Reading SEEPROM...", ahc_name(ahc));
have_seeprom = read_seeprom(&sd,
(u_int16_t *)&sc,
/*start_addr*/0,
sizeof(sc)/2);
if (have_seeprom) {
/* Check checksum */
int i;
int maxaddr = (sizeof(sc)/2) - 1;
u_int16_t *scarray = (u_int16_t *)&sc;
for (i = 0; i < maxaddr; i++)
checksum = checksum + scarray[i];
if (checksum != sc.checksum) {
if(bootverbose)
printf ("checksum error\n");
have_seeprom = 0;
} else if (bootverbose) {
printf("done.\n");
}
}
if (!have_seeprom) {
if (bootverbose)
printf("%s: No SEEPROM available\n", ahc_name(ahc));
ahc->flags |= AHC_USEDEFAULTS;
} else {
/*
* Put the data we've collected down into SRAM
* where ahc_init will find it.
*/
int i;
int max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
u_int16_t discenable;
discenable = 0;
for (i = 0; i < max_targ; i++){
u_int8_t target_settings;
target_settings = (sc.device_flags[i] & CFXFER) << 4;
if (sc.device_flags[i] & CFSYNCH)
target_settings |= SOFS;
if (sc.device_flags[i] & CFWIDEB)
target_settings |= WIDEXFER;
if (sc.device_flags[i] & CFDISC)
discenable |= (0x01 << i);
ahc_outb(ahc, TARG_SCSIRATE + i, target_settings);
}
ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
ahc->our_id = sc.brtime_id & CFSCSIID;
scsi_conf = (ahc->our_id & 0x7);
if (sc.adapter_control & CFSPARITY)
scsi_conf |= ENSPCHK;
if (sc.adapter_control & CFRESETB)
scsi_conf |= RESET_SCSI;
if (sc.bios_control & CF284XEXTEND)
ahc->flags |= AHC_EXTENDED_TRANS_A;
/* Set SCSICONF info */
ahc_outb(ahc, SCSICONF, scsi_conf);
if (sc.adapter_control & CF284XSTERM)
ahc->flags |= AHC_TERM_ENB_A;
}
}
static device_method_t ahc_eisa_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, aic7770_probe),
DEVMETHOD(device_attach, aic7770_attach),
{ 0, 0 }
};
static driver_t ahc_eisa_driver = {
"ahc",
ahc_eisa_methods,
1, /* unused */
};
static devclass_t ahc_devclass;
DRIVER_MODULE(ahc, eisa, ahc_eisa_driver, ahc_devclass, 0, 0);
#endif /* NEISA > 0 */

626
sys/i386/eisa/eisaconf.c
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@ -1,626 +0,0 @@
/*
* EISA bus probe and attach routines
*
* Copyright (c) 1995, 1996 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "opt_eisa.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/queue.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/limits.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
typedef struct resvaddr {
u_long addr; /* start address */
u_long size; /* size of reserved area */
int flags;
struct resource *res; /* resource manager handle */
LIST_ENTRY(resvaddr) links; /* List links */
} resvaddr_t;
LIST_HEAD(resvlist, resvaddr);
struct irq_node {
int irq_no;
int irq_trigger;
void *idesc;
TAILQ_ENTRY(irq_node) links;
};
TAILQ_HEAD(irqlist, irq_node);
struct eisa_ioconf {
int slot;
struct resvlist ioaddrs; /* list of reserved I/O ranges */
struct resvlist maddrs; /* list of reserved memory ranges */
struct irqlist irqs; /* list of reserved irqs */
};
/* To be replaced by the "super device" generic device structure... */
struct eisa_device {
eisa_id_t id;
struct eisa_ioconf ioconf;
};
/* Global variable, so UserConfig can change it. */
#define MAX_COL 79
#ifndef EISA_SLOTS
#define EISA_SLOTS 10 /* PCI clashes with higher ones.. fix later */
#endif
int num_eisa_slots = EISA_SLOTS;
static devclass_t eisa_devclass;
static void eisa_reg_print (device_t, char *, char *, int *);
static struct irq_node * eisa_find_irq(struct eisa_device *e_dev, int rid);
static struct resvaddr * eisa_find_maddr(struct eisa_device *e_dev, int rid);
static struct resvaddr * eisa_find_ioaddr(struct eisa_device *e_dev, int rid);
static int
mainboard_probe(device_t dev)
{
char *idstring;
eisa_id_t id = eisa_get_id(dev);
if (eisa_get_slot(dev) != 0)
return (ENXIO);
idstring = (char *)malloc(8 + sizeof(" (System Board)") + 1,
M_DEVBUF, M_NOWAIT);
if (idstring == NULL) {
panic("Eisa probe unable to malloc");
}
sprintf(idstring, "%c%c%c%03x%01x (System Board)",
EISA_MFCTR_CHAR0(id),
EISA_MFCTR_CHAR1(id),
EISA_MFCTR_CHAR2(id),
EISA_PRODUCT_ID(id),
EISA_REVISION_ID(id));
device_set_desc(dev, idstring);
return (0);
}
static int
mainboard_attach(device_t dev)
{
return (0);
}
static device_method_t mainboard_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, mainboard_probe),
DEVMETHOD(device_attach, mainboard_attach),
{ 0, 0 }
};
static driver_t mainboard_driver = {
"mainboard",
mainboard_methods,
1,
};
static devclass_t mainboard_devclass;
DRIVER_MODULE(mainboard, eisa, mainboard_driver, mainboard_devclass, 0, 0);
/*
** probe for EISA devices
*/
static int
eisa_probe(device_t dev)
{
int i,slot;
struct eisa_device *e_dev;
device_t child;
int eisaBase = 0xc80;
eisa_id_t eisa_id;
int devices_found = 0;
device_set_desc(dev, "EISA bus");
for (slot = 0; slot < num_eisa_slots; eisaBase+=0x1000, slot++) {
int id_size = sizeof(eisa_id);
eisa_id = 0;
for( i = 0; i < id_size; i++ ) {
outb(eisaBase,0x80 + i); /*Some cards require priming*/
eisa_id |= inb(eisaBase+i) << ((id_size-i-1)*CHAR_BIT);
}
if (eisa_id & 0x80000000)
continue; /* no EISA card in slot */
devices_found++;
/* Prepare an eisa_device_node for this slot */
e_dev = (struct eisa_device *)malloc(sizeof(*e_dev),
M_DEVBUF, M_NOWAIT);
if (!e_dev) {
device_printf(dev, "cannot malloc eisa_device");
break; /* Try to attach what we have already */
}
bzero(e_dev, sizeof(*e_dev));
e_dev->id = eisa_id;
e_dev->ioconf.slot = slot;
/* Initialize our lists of reserved addresses */
LIST_INIT(&(e_dev->ioconf.ioaddrs));
LIST_INIT(&(e_dev->ioconf.maddrs));
TAILQ_INIT(&(e_dev->ioconf.irqs));
child = device_add_child(dev, NULL, -1);
device_set_ivars(child, e_dev);
}
/*
* EISA busses themselves are not easily detectable, the easiest way
* to tell if there is an eisa bus is if we found something - there
* should be a motherboard "card" there somewhere.
*/
return devices_found ? 0 : ENXIO;
}
static void
eisa_probe_nomatch(device_t dev, device_t child)
{
u_int32_t eisa_id = eisa_get_id(child);
u_int8_t slot = eisa_get_slot(child);
device_printf(dev, "unknown card %c%c%c%03x%01x (0x%08x) at slot %d\n",
EISA_MFCTR_CHAR0(eisa_id),
EISA_MFCTR_CHAR1(eisa_id),
EISA_MFCTR_CHAR2(eisa_id),
EISA_PRODUCT_ID(eisa_id),
EISA_REVISION_ID(eisa_id),
eisa_id,
slot);
return;
}
static void
eisa_reg_print (dev, string, separator, column)
device_t dev;
char * string;
char * separator;
int * column;
{
int length = strlen(string);
length += (separator ? 2 : 1);
if (((*column) + length) >= MAX_COL) {
printf("\n");
(*column) = 0;
} else if ((*column) != 0) {
if (separator) {
printf("%c", *separator);
(*column)++;
}
printf(" ");
(*column)++;
}
if ((*column) == 0) {
(*column) += device_printf(dev, "%s", string);
} else {
(*column) += printf("%s", string);
}
return;
}
static int
eisa_print_child(device_t dev, device_t child)
{
char buf[81];
struct eisa_device * e_dev = device_get_ivars(child);
int rid;
struct irq_node * irq;
struct resvaddr * resv;
char separator = ',';
int column = 0;
int retval = 0;
if (device_get_desc(child)) {
snprintf(buf, sizeof(buf), "<%s>", device_get_desc(child));
eisa_reg_print(child, buf, NULL, &column);
}
rid = 0;
while ((resv = eisa_find_ioaddr(e_dev, rid++))) {
if ((resv->size == 1) ||
(resv->flags & RESVADDR_BITMASK)) {
snprintf(buf, sizeof(buf), "%s%lx",
((rid == 1) ? "at 0x" : "0x"),
resv->addr);
} else {
snprintf(buf, sizeof(buf), "%s%lx-0x%lx",
((rid == 1) ? "at 0x" : "0x"),
resv->addr,
(resv->addr + (resv->size - 1)));
}
eisa_reg_print(child, buf,
((rid == 2) ? &separator : NULL), &column);
}
rid = 0;
while ((resv = eisa_find_maddr(e_dev, rid++))) {
if ((resv->size == 1) ||
(resv->flags & RESVADDR_BITMASK)) {
snprintf(buf, sizeof(buf), "%s%lx",
((rid == 1) ? "at 0x" : "0x"),
resv->addr);
} else {
snprintf(buf, sizeof(buf), "%s%lx-0x%lx",
((rid == 1) ? "at 0x" : "0x"),
resv->addr,
(resv->addr + (resv->size - 1)));
}
eisa_reg_print(child, buf,
((rid == 2) ? &separator : NULL), &column);
}
rid = 0;
while ((irq = eisa_find_irq(e_dev, rid++)) != NULL) {
snprintf(buf, sizeof(buf), "irq %d (%s)", irq->irq_no,
(irq->irq_trigger ? "level" : "edge"));
eisa_reg_print(child, buf,
((rid == 1) ? &separator : NULL), &column);
}
snprintf(buf, sizeof(buf), "on %s slot %d\n",
device_get_nameunit(dev), eisa_get_slot(child));
eisa_reg_print(child, buf, NULL, &column);
return (retval);
}
static struct irq_node *
eisa_find_irq(struct eisa_device *e_dev, int rid)
{
int i;
struct irq_node *irq;
for (i = 0, irq = TAILQ_FIRST(&e_dev->ioconf.irqs);
i < rid && irq;
i++, irq = TAILQ_NEXT(irq, links))
;
if (irq)
return (irq);
else
return (NULL);
}
static struct resvaddr *
eisa_find_maddr(struct eisa_device *e_dev, int rid)
{
int i;
struct resvaddr *resv;
for (i = 0, resv = LIST_FIRST(&e_dev->ioconf.maddrs);
i < rid && resv;
i++, resv = LIST_NEXT(resv, links))
;
return resv;
}
static struct resvaddr *
eisa_find_ioaddr(struct eisa_device *e_dev, int rid)
{
int i;
struct resvaddr *resv;
for (i = 0, resv = LIST_FIRST(&e_dev->ioconf.ioaddrs);
i < rid && resv;
i++, resv = LIST_NEXT(resv, links))
;
return resv;
}
static int
eisa_read_ivar(device_t dev, device_t child, int which, u_long *result)
{
struct eisa_device *e_dev = device_get_ivars(child);
struct irq_node *irq;
switch (which) {
case EISA_IVAR_SLOT:
*result = e_dev->ioconf.slot;
break;
case EISA_IVAR_ID:
*result = e_dev->id;
break;
case EISA_IVAR_IRQ:
/* XXX only first irq */
if ((irq = eisa_find_irq(e_dev, 0)) != NULL) {
*result = irq->irq_no;
} else {
*result = -1;
}
break;
default:
return (ENOENT);
}
return (0);
}
static int
eisa_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
{
return (EINVAL);
}
static struct resource *
eisa_alloc_resource(device_t dev, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
int isdefault;
struct eisa_device *e_dev = device_get_ivars(child);
struct resource *rv, **rvp = 0;
isdefault = (device_get_parent(child) == dev
&& start == 0UL && end == ~0UL && count == 1);
switch (type) {
case SYS_RES_IRQ:
if (isdefault) {
struct irq_node * irq = eisa_find_irq(e_dev, *rid);
if (irq == NULL)
return 0;
start = end = irq->irq_no;
count = 1;
if (irq->irq_trigger == EISA_TRIGGER_LEVEL) {
flags |= RF_SHAREABLE;
} else {
flags &= ~RF_SHAREABLE;
}
}
break;
case SYS_RES_MEMORY:
if (isdefault) {
struct resvaddr *resv;
resv = eisa_find_maddr(e_dev, *rid);
if (!resv)
return 0;
start = resv->addr;
end = resv->addr + (resv->size - 1);
count = resv->size;
rvp = &resv->res;
}
break;
case SYS_RES_IOPORT:
if (isdefault) {
struct resvaddr *resv;
resv = eisa_find_ioaddr(e_dev, *rid);
if (!resv)
return 0;
start = resv->addr;
end = resv->addr + (resv->size - 1);
count = resv->size;
rvp = &resv->res;
}
break;
default:
return 0;
}
rv = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
type, rid, start, end, count, flags);
if (rvp)
*rvp = rv;
return rv;
}
static int
eisa_release_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
int rv;
struct eisa_device *e_dev = device_get_ivars(child);
struct resvaddr *resv = 0;
switch (type) {
case SYS_RES_IRQ:
if (eisa_find_irq(e_dev, rid) == NULL)
return EINVAL;
break;
case SYS_RES_MEMORY:
if (device_get_parent(child) == dev)
resv = eisa_find_maddr(e_dev, rid);
break;
case SYS_RES_IOPORT:
if (device_get_parent(child) == dev)
resv = eisa_find_ioaddr(e_dev, rid);
break;
default:
return (ENOENT);
}
rv = BUS_RELEASE_RESOURCE(device_get_parent(dev), child, type, rid, r);
if (rv == 0) {
if (resv)
resv->res = 0;
}
return rv;
}
int
eisa_add_intr(device_t dev, int irq, int trigger)
{
struct eisa_device *e_dev = device_get_ivars(dev);
struct irq_node *irq_info;
irq_info = (struct irq_node *)malloc(sizeof(*irq_info), M_DEVBUF,
M_NOWAIT);
if (irq_info == NULL)
return (1);
irq_info->irq_no = irq;
irq_info->irq_trigger = trigger;
irq_info->idesc = NULL;
TAILQ_INSERT_TAIL(&e_dev->ioconf.irqs, irq_info, links);
return 0;
}
static int
eisa_add_resvaddr(struct eisa_device *e_dev, struct resvlist *head, u_long base,
u_long size, int flags)
{
resvaddr_t *reservation;
reservation = (resvaddr_t *)malloc(sizeof(resvaddr_t),
M_DEVBUF, M_NOWAIT);
if(!reservation)
return (ENOMEM);
reservation->addr = base;
reservation->size = size;
reservation->flags = flags;
if (!head->lh_first) {
LIST_INSERT_HEAD(head, reservation, links);
}
else {
resvaddr_t *node;
for(node = head->lh_first; node; node = node->links.le_next) {
if (node->addr > reservation->addr) {
/*
* List is sorted in increasing
* address order.
*/
LIST_INSERT_BEFORE(node, reservation, links);
break;
}
if (node->addr == reservation->addr) {
/*
* If the entry we want to add
* matches any already in here,
* fail.
*/
free(reservation, M_DEVBUF);
return (EEXIST);
}
if (!node->links.le_next) {
LIST_INSERT_AFTER(node, reservation, links);
break;
}
}
}
return (0);
}
int
eisa_add_mspace(device_t dev, u_long mbase, u_long msize, int flags)
{
struct eisa_device *e_dev = device_get_ivars(dev);
return eisa_add_resvaddr(e_dev, &(e_dev->ioconf.maddrs), mbase, msize,
flags);
}
int
eisa_add_iospace(device_t dev, u_long iobase, u_long iosize, int flags)
{
struct eisa_device *e_dev = device_get_ivars(dev);
return eisa_add_resvaddr(e_dev, &(e_dev->ioconf.ioaddrs), iobase,
iosize, flags);
}
static device_method_t eisa_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, eisa_probe),
DEVMETHOD(device_attach, bus_generic_attach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_print_child, eisa_print_child),
DEVMETHOD(bus_probe_nomatch, eisa_probe_nomatch),
DEVMETHOD(bus_read_ivar, eisa_read_ivar),
DEVMETHOD(bus_write_ivar, eisa_write_ivar),
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
DEVMETHOD(bus_alloc_resource, eisa_alloc_resource),
DEVMETHOD(bus_release_resource, eisa_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
{ 0, 0 }
};
static driver_t eisa_driver = {
"eisa",
eisa_methods,
1, /* no softc */
};
DRIVER_MODULE(eisa, isab, eisa_driver, eisa_devclass, 0, 0);
DRIVER_MODULE(eisa, nexus, eisa_driver, eisa_devclass, 0, 0);

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sys/i386/eisa/eisaconf.h
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@ -1,91 +0,0 @@
/*
* EISA bus device definitions
*
* Copyright (c) 1995, 1996 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _I386_EISA_EISACONF_H_
#define _I386_EISA_EISACONF_H_ 1
#define EISA_SLOT_SIZE 0x1000
#define EISA_MFCTR_CHAR0(ID) (char)(((ID>>26) & 0x1F) | '@') /* Bits 26-30 */
#define EISA_MFCTR_CHAR1(ID) (char)(((ID>>21) & 0x1F) | '@') /* Bits 21-25 */
#define EISA_MFCTR_CHAR2(ID) (char)(((ID>>16) & 0x1F) | '@') /* Bits 16-20 */
#define EISA_MFCTR_ID(ID) (short)((ID>>16) & 0xFF) /* Bits 16-31 */
#define EISA_PRODUCT_ID(ID) (short)((ID>>4) & 0xFFF) /* Bits 4-15 */
#define EISA_REVISION_ID(ID) (u_char)(ID & 0x0F) /* Bits 0-3 */
extern int num_eisa_slots;
typedef u_int32_t eisa_id_t;
enum eisa_device_ivars {
EISA_IVAR_SLOT,
EISA_IVAR_ID,
EISA_IVAR_IRQ
};
#define EISA_TRIGGER_EDGE 0x0
#define EISA_TRIGGER_LEVEL 0x1
/*
* Simplified accessors for isa devices
*/
#define EISA_ACCESSOR(A, B, T) \
\
static __inline T eisa_get_ ## A(device_t dev) \
{ \
uintptr_t v; \
BUS_READ_IVAR(device_get_parent(dev), dev, EISA_IVAR_ ## B, &v); \
return (T) v; \
} \
\
static __inline void eisa_set_ ## A(device_t dev, T t) \
{ \
u_long v = (u_long) t; \
BUS_WRITE_IVAR(device_get_parent(dev), dev, EISA_IVAR_ ## B, v); \
}
EISA_ACCESSOR(slot, SLOT, int)
EISA_ACCESSOR(id, ID, eisa_id_t)
EISA_ACCESSOR(irq, IRQ, eisa_id_t)
int eisa_add_intr __P((device_t, int, int));
#define RESVADDR_NONE 0x00
#define RESVADDR_BITMASK 0x01 /* size is a mask of reserved
* bits at addr
*/
#define RESVADDR_RELOCATABLE 0x02
int eisa_add_iospace __P((device_t, u_long, u_long, int));
int eisa_add_mspace __P((device_t, u_long, u_long, int));
#endif /* _I386_EISA_EISACONF_H_ */

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sys/i386/eisa/if_fea.c
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@ -1,270 +0,0 @@
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software withough specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* DEC PDQ FDDI Controller
*
* This module support the DEFEA EISA FDDI Controller.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <i386/eisa/eisaconf.h>
#include <dev/pdq/pdqvar.h>
#include <dev/pdq/pdqreg.h>
static void pdq_eisa_subprobe __P((pdq_bus_t, u_int32_t, u_int32_t *, u_int32_t *, u_int32_t *));
static void pdq_eisa_devinit __P((pdq_softc_t *));
static const char * pdq_eisa_match __P((eisa_id_t));
static int pdq_eisa_probe __P((device_t));
static int pdq_eisa_attach __P((device_t));
void pdq_eisa_intr __P((void *));
static int pdq_eisa_shutdown __P((device_t));
#define DEFEA_IRQS 0x0000FBA9U
#define DEFEA_INTRENABLE 0x8 /* level interrupt */
#define DEFEA_DECODE_IRQ(n) ((DEFEA_IRQS >> ((n) << 2)) & 0x0f)
#define EISA_DEVICE_ID_DEC_DEC3001 0x10a33001
#define EISA_DEVICE_ID_DEC_DEC3002 0x10a33002
#define EISA_DEVICE_ID_DEC_DEC3003 0x10a33003
#define EISA_DEVICE_ID_DEC_DEC3004 0x10a33004
static void
pdq_eisa_subprobe(bc, iobase, maddr, msize, irq)
pdq_bus_t bc;
u_int32_t iobase;
u_int32_t *maddr;
u_int32_t *msize;
u_int32_t *irq;
{
if (irq != NULL)
*irq = DEFEA_DECODE_IRQ(PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_IO_CONFIG_STAT_0) & 3);
*maddr = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_0) << 8)
| (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_1) << 16);
*msize = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_MASK_0) + 4) << 8;
return;
}
static void
pdq_eisa_devinit (sc)
pdq_softc_t *sc;
{
pdq_uint8_t data;
/*
* Do the standard initialization for the DEFEA registers.
*/
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
#if defined(PDQ_IOMAPPED)
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
#else
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
#endif
data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
return;
}
static const char *
pdq_eisa_match (type)
eisa_id_t type;
{
switch (type) {
case EISA_DEVICE_ID_DEC_DEC3001:
case EISA_DEVICE_ID_DEC_DEC3002:
case EISA_DEVICE_ID_DEC_DEC3003:
case EISA_DEVICE_ID_DEC_DEC3004:
return ("DEC FDDIcontroller/EISA Adapter");
break;
default:
break;
}
return (NULL);
}
static int
pdq_eisa_probe (dev)
device_t dev;
{
const char *desc;
u_int32_t iobase;
u_int32_t irq;
u_int32_t maddr;
u_int32_t msize;
u_int32_t eisa_id = eisa_get_id(dev);;
desc = pdq_eisa_match(eisa_id);
if (!desc) {
return (ENXIO);
}
device_set_desc(dev, desc);
iobase = eisa_get_slot(dev) * EISA_SLOT_SIZE;
pdq_eisa_subprobe(PDQ_BUS_EISA, iobase, &maddr, &msize, &irq);
eisa_add_iospace(dev, iobase, 0x200, RESVADDR_NONE);
eisa_add_mspace(dev, maddr, msize, RESVADDR_NONE);
eisa_add_intr(dev, irq, EISA_TRIGGER_LEVEL);
return (0);
}
void
pdq_eisa_intr(xdev)
void *xdev;
{
device_t dev = (device_t) xdev;
pdq_softc_t *sc = device_get_softc(dev);
(void) pdq_interrupt(sc->sc_pdq);
return;
}
static int
pdq_eisa_attach (dev)
device_t dev;
{
pdq_softc_t *sc = device_get_softc(dev);
struct resource *io = 0;
struct resource *irq = 0;
struct resource *mspace = 0;
int rid;
void *ih;
u_int32_t m_addr, m_size;
rid = 0;
io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
0, ~0, 1, RF_ACTIVE);
if (!io) {
device_printf(dev, "No I/O space?!\n");
goto bad;
}
rid = 0;
mspace = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
0, ~0, 1, RF_ACTIVE);
if (!mspace) {
device_printf(dev, "No memory space?!\n");
goto bad;
}
rid = 0;
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
0, ~0, 1, RF_ACTIVE);
if (!irq) {
device_printf(dev, "No, irq?!\n");
goto bad;
}
m_addr = rman_get_start(mspace);
m_size = (rman_get_end(mspace) - rman_get_start(mspace)) + 1;
sc->sc_iobase = (pdq_bus_ioport_t) rman_get_start(io);
sc->sc_membase = (pdq_bus_memaddr_t) pmap_mapdev(m_addr, m_size);
sc->sc_if.if_name = "fea";
sc->sc_if.if_unit = device_get_unit(dev);
pdq_eisa_devinit(sc);
sc->sc_pdq = pdq_initialize(PDQ_BUS_EISA, sc->sc_membase,
sc->sc_if.if_name, sc->sc_if.if_unit,
(void *) sc, PDQ_DEFEA);
if (sc->sc_pdq == NULL) {
device_printf(dev, "initialization failed\n");
goto bad;
}
if (bus_setup_intr(dev, irq, INTR_TYPE_NET, pdq_eisa_intr, dev, &ih)) {
goto bad;
}
bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
pdq_ifattach(sc, NULL);
return (0);
bad:
if (io)
bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
if (irq)
bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
if (mspace)
bus_release_resource(dev, SYS_RES_MEMORY, 0, mspace);
return (-1);
}
static int
pdq_eisa_shutdown(dev)
device_t dev;
{
pdq_softc_t *sc = device_get_softc(dev);
pdq_hwreset(sc->sc_pdq);
return (0);
}
static device_method_t pdq_eisa_methods[] = {
DEVMETHOD(device_probe, pdq_eisa_probe),
DEVMETHOD(device_attach, pdq_eisa_attach),
DEVMETHOD(device_shutdown, pdq_eisa_shutdown),
{ 0, 0 }
};
static driver_t pdq_eisa_driver = {
"fea",
pdq_eisa_methods,
sizeof(pdq_softc_t),
};
static devclass_t pdq_devclass;
DRIVER_MODULE(pdq, eisa, pdq_eisa_driver, pdq_devclass, 0, 0);

201
sys/i386/eisa/if_vx_eisa.c
View File

@ -1,201 +0,0 @@
/*
* Copyright (C) 1996 Naoki Hamada <nao@tom-yam.or.jp>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include "eisa.h"
#if NEISA > 0
#include "vx.h"
#if NVX > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <i386/eisa/eisaconf.h>
#include <dev/vx/if_vxreg.h>
#define EISA_DEVICE_ID_3COM_3C592 0x506d5920
#define EISA_DEVICE_ID_3COM_3C597_TX 0x506d5970
#define EISA_DEVICE_ID_3COM_3C597_T4 0x506d5971
#define EISA_DEVICE_ID_3COM_3C597_MII 0x506d5972
#define VX_EISA_SLOT_OFFSET 0x0c80
#define VX_EISA_IOSIZE 0x000a
#define VX_RESOURCE_CONFIG 0x0008
static const char *vx_match __P((eisa_id_t type));
static const char*
vx_match(eisa_id_t type)
{
switch (type) {
case EISA_DEVICE_ID_3COM_3C592:
return "3Com 3C592 Network Adapter";
break;
case EISA_DEVICE_ID_3COM_3C597_TX:
return "3Com 3C597-TX Network Adapter";
break;
case EISA_DEVICE_ID_3COM_3C597_T4:
return "3Com 3C597-T4 Network Adapter";
break;
case EISA_DEVICE_ID_3COM_3C597_MII:
return "3Com 3C597-MII Network Adapter";
break;
default:
break;
}
return (NULL);
}
static int
vx_eisa_probe(device_t dev)
{
const char *desc;
u_long iobase;
u_long port;
desc = vx_match(eisa_get_id(dev));
if (!desc)
return (ENXIO);
device_set_desc(dev, desc);
port = eisa_get_slot(dev) * EISA_SLOT_SIZE;
iobase = port + VX_EISA_SLOT_OFFSET;
eisa_add_iospace(dev, iobase, VX_EISA_IOSIZE, RESVADDR_NONE);
eisa_add_iospace(dev, port, VX_IOSIZE, RESVADDR_NONE);
/* Set irq */
eisa_add_intr(dev, inw(iobase + VX_RESOURCE_CONFIG) >> 12,
EISA_TRIGGER_EDGE);
return (0);
}
static int
vx_eisa_attach(device_t dev)
{
struct vx_softc *sc;
int unit = device_get_unit(dev);
struct resource *io = 0;
struct resource *eisa_io = 0;
struct resource *irq = 0;
int rid;
void *ih;
/*
* The addresses are sorted in increasing order
* so we know the port to pass to the core ep
* driver comes first.
*/
rid = 0;
io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
0, ~0, 1, RF_ACTIVE);
if (!io) {
device_printf(dev, "No I/O space?!\n");
goto bad;
}
rid = 1;
eisa_io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
0, ~0, 1, RF_ACTIVE);
if (!eisa_io) {
device_printf(dev, "No I/O space?!\n");
goto bad;
}
if ((sc = vxalloc(unit)) == NULL)
goto bad;
sc->vx_io_addr = rman_get_start(io);
rid = 0;
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
0, ~0, 1, RF_ACTIVE);
if (!irq) {
device_printf(dev, "No irq?!\n");
vxfree(sc);
goto bad;
}
/* Now the registers are availible through the lower ioport */
vxattach(sc);
if (bus_setup_intr(dev, irq, INTR_TYPE_NET, vxintr, sc, &ih)) {
vxfree(sc);
goto bad;
}
return 0;
bad:
if (io)
bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
if (eisa_io)
bus_release_resource(dev, SYS_RES_IOPORT, 0, eisa_io);
if (irq)
bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
return -1;
}
static device_method_t vx_eisa_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, vx_eisa_probe),
DEVMETHOD(device_attach, vx_eisa_attach),
{ 0, 0 }
};
static driver_t vx_eisa_driver = {
"vx",
vx_eisa_methods,
1, /* unused */
};
static devclass_t vx_devclass;
DRIVER_MODULE(vx, eisa, vx_eisa_driver, vx_devclass, 0, 0);
#endif /* NVX > 0 */
#endif /* NEISA > 0 */

2
sys/i386/i386/userconfig.c
View File

@ -2616,7 +2616,7 @@ static int lineno;
#if NEISA > 0
#include <i386/eisa/eisaconf.h>
#include <dev/eisa/eisaconf.h>
static int set_num_eisa_slots(CmdParm *);

1133
sys/i386/isa/if_ex.c
View File

File diff suppressed because it is too large Load Diff

154
sys/i386/isa/if_exreg.h
View File

@ -1,154 +0,0 @@
/*
* Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Intel EtherExpress Pro/10 Ethernet driver
*/
/*
* Several constants.
*/
/* Length of an ethernet address. */
#define ETHER_ADDR_LEN 6
/* Default RAM size in board. */
#define CARD_RAM_SIZE 0x8000
/* Number of I/O ports used. */
#define EX_IOSIZE 16
/*
* Intel EtherExpress Pro (i82595 based) registers
*/
/* Common registers to all banks. */
#define CMD_REG 0
#define REG1 1
#define REG2 2
#define REG3 3
#define REG4 4
#define REG5 5
#define REG6 6
#define REG7 7
#define REG8 8
#define REG9 9
#define REG10 10
#define REG11 11
#define REG12 12
#define REG13 13
#define REG14 14
#define REG15 15
/* Definitions for command register (CMD_REG). */
#define Switch_Bank_CMD 0
#define MC_Setup_CMD 3
#define Transmit_CMD 4
#define Diagnose_CMD 7
#define Rcv_Enable_CMD 8
#define Rcv_Stop 11
#define Reset_CMD 14
#define Resume_XMT_List_CMD 28
#define Sel_Reset_CMD 30
#define Abort 0x20
#define Bank0_Sel 0x00
#define Bank1_Sel 0x40
#define Bank2_Sel 0x80
/* Bank 0 specific registers. */
#define STATUS_REG 1
#define ID_REG 2
#define Id_Mask 0x2c
#define Id_Sig 0x24
#define Counter_bits 0xc0
#define MASK_REG 3
#define Exec_Int 0x08
#define Tx_Int 0x04
#define Rx_Int 0x02
#define Rx_Stp_Int 0x01
#define All_Int 0x0f
#define RCV_BAR 4
#define RCV_BAR_Lo 4
#define RCV_BAR_Hi 5
#define RCV_STOP_REG 6
#define XMT_BAR 10
#define HOST_ADDR_REG 12 /* 16-bit register */
#define IO_PORT_REG 14 /* 16-bit register */
/* Bank 1 specific registers. */
#define TriST_INT 0x80
#define INT_NO_REG 2
#define RCV_LOWER_LIMIT_REG 8
#define RCV_UPPER_LIMIT_REG 9
#define XMT_LOWER_LIMIT_REG 10
#define XMT_UPPER_LIMIT_REG 11
/* Bank 2 specific registers. */
#define Disc_Bad_Fr 0x80
#define Tx_Chn_ErStp 0x40
#define Tx_Chn_Int_Md 0x20
#define No_SA_Ins 0x10
#define RX_CRC_InMem 0x04
#define BNC_bit 0x20
#define TPE_bit 0x04
#define I_ADDR_REG0 4
#define EEPROM_REG 10
#define Trnoff_Enable 0x10
/* EEPROM memory positions (16-bit wide). */
#define EE_IRQ_No 1
#define IRQ_No_Mask 0x07
#define EE_Eth_Addr_Lo 2
#define EE_Eth_Addr_Mid 3
#define EE_Eth_Addr_Hi 4
/* EEPROM serial interface. */
#define EESK 0x01
#define EECS 0x02
#define EEDI 0x04
#define EEDO 0x08
#define EE_READ_CMD (6 << 6)
/* Frame chain constants. */
/* Transmit header length (in board's ring buffer). */
#define XMT_HEADER_LEN 8
#define XMT_Chain_Point 4
#define XMT_Byte_Count 6
#define Done_bit 0x0080
#define Ch_bit 0x8000
/* Transmit result bits. */
#define No_Collisions_bits 0x000f
#define TX_OK_bit 0x2000
/* Receive result bits. */
#define RCV_Done 8
#define RCV_OK_bit 0x2000

2324
sys/i386/isa/if_ie.c
View File

File diff suppressed because it is too large Load Diff

19
sys/i386/isa/if_ie507.h
View File

@ -1,19 +0,0 @@
/*
* $FreeBSD$
* Definitions for 3C507
*/
#define IE507_CTRL 6 /* control port */
#define IE507_ICTRL 10 /* interrupt control */
#define IE507_ATTN 11 /* any write here sends a chan attn */
#define IE507_MADDR 14 /* shared memory configuration */
#define IE507_IRQ 15 /* IRQ configuration */
#define EL_CTRL_BNK1 0x01 /* register bank 1 */
#define EL_CTRL_IEN 0x04 /* interrupt enable */
#define EL_CTRL_INTL 0x08 /* interrupt active latch */
#define EL_CTRL_16BIT 0x10 /* bus width; clear = 8-bit, set = 16-bit */
#define EL_CTRL_LOOP 0x20 /* loopback mode */
#define EL_CTRL_NRST 0x80 /* turn off to reset */
#define EL_CTRL_RESET (EL_CTRL_LOOP)
#define EL_CTRL_NORMAL (EL_CTRL_NRST | EL_CTRL_IEN | EL_CTRL_BNK1)

80
sys/i386/isa/if_iee16.h
View File

@ -1,80 +0,0 @@
/*
* Copyright (c) 1993, 1994, 1995
* Rodney W. Grimes, Milwaukie, Oregon 97222. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer as
* the first lines of this file unmodified.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Rodney W. Grimes.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* Definitions for EtherExpress 16
*/
#define IEE16_ATTN 0x06 /* channel attention control */
#define IEE16_IRQ 0x07 /* IRQ configuration */
#define IEE16_IRQ_ENABLE 0x08 /* enable board interrupts */
#define IEE16_MEMDEC 0x0a /* memory decode */
#define IEE16_MCTRL 0x0b /* memory control */
#define IEE16_MCTRL_FMCS16 0x10 /* MEMCS16- for F000 */
#define IEE16_MPCTRL 0x0c /* memory page control */
#define IEE16_CONFIG 0x0d /* config register */
#define IEE16_BART_LOOPBACK 0x02 /* loopback, 0=none, 1=loopback */
#define IEE16_BART_IOCHRDY_LATE 0x10 /* iochrdy late control bit */
#define IEE16_BART_IO_TEST_EN 0x20 /* enable iochrdy timing test */
#define IEE16_BART_IO_RESULT 0x40 /* result of the iochrdy test */
#define IEE16_BART_MCS16_TEST 0x80 /* enable memcs16 select test */
#define IEE16_ECTRL 0x0e /* eeprom control */
#define IEE16_ECTRL_EESK 0x01 /* EEPROM clock bit */
#define IEE16_ECTRL_EECS 0x02 /* EEPROM chip select */
#define IEE16_ECTRL_EEDI 0x04 /* EEPROM data in bit */
#define IEE16_ECTRL_EEDO 0x08 /* EEPROM data out bit */
#define IEE16_RESET_ASIC 0x40 /* reset ASIC (bart) pin */
#define IEE16_RESET_586 0x80 /* reset 82586 pin */
#define IEE16_ECTRL_MASK 0xb2 /* and'ed with ECTRL to enable read */
#define IEE16_MECTRL 0x0f /* memory control, 0xe000 seg 'W' */
#define IEE16_ID_PORT 0x0f /* auto-id port 'R' */
#define IEE16_ID 0xbaba /* known id of EE16 */
#define IEE16_EEPROM_READ 0x06 /* EEPROM read opcode */
#define IEE16_EEPROM_OPSIZE1 0x03 /* size of EEPROM opcodes */
#define IEE16_EEPROM_ADDR_SIZE 0x06 /* size of EEPROM address */
/* Locations in the EEPROM */
#define IEE16_EEPROM_CONFIG1 0x00 /* Configuration register 1 */
#define IEE16_EEPROM_IRQ 0xE000 /* Encoded IRQ */
#define IEE16_EEPROM_IRQ_SHIFT 13 /* To shift IRQ to lower bits */
#define IEE16_EEPROM_LOCK_ADDR 0x01 /* contains the lock bit */
#define IEE16_EEPROM_LOCKED 0x01 /* means that it is locked */
#define IEE16_EEPROM_ENET_LOW 0x02 /* Ethernet address, low word */
#define IEE16_EEPROM_ENET_MID 0x03 /* Ethernet address, middle word */
#define IEE16_EEPROM_ENET_HIGH 0x04 /* Ethernet address, high word */

24
sys/i386/isa/if_iereg.h
View File

@ -1,24 +0,0 @@
/*
* $FreeBSD$
* definitions for AT&T StarLAN 10 etc...
*/
#define IEATT_RESET 0 /* any write here resets the 586 */
#define IEATT_ATTN 1 /* any write here sends a Chan attn */
#define IEATT_REVISION 6 /* read here to figure out this board */
#define IEATT_ATTRIB 7 /* more information about this board */
#define SL_BOARD(x) ((x) & 0x0f)
#define SL_REV(x) ((x) >> 4)
#define SL1_BOARD 0
#define SL10_BOARD 1
#define EN100_BOARD 2
#define SLFIBER_BOARD 3
#define SL_ATTR_WIDTH 0x04 /* bus width: clear -> 8-bit */
#define SL_ATTR_SPEED 0x08 /* medium speed: clear -> 10 Mbps */
#define SL_ATTR_CODING 0x10 /* encoding: clear -> Manchester */
#define SL_ATTR_HBW 0x20 /* host bus width: clear -> 16-bit */
#define SL_ATTR_TYPE 0x40 /* medium type: clear -> Ethernet */
#define SL_ATTR_BOOTROM 0x80 /* set -> boot ROM present */

5
sys/i386/isa/isa_compat.h
View File

@ -35,7 +35,6 @@
#include "cx.h"
#include "el.h"
#include "fe.h"
#include "ie.h"
#include "le.h"
#include "lnc.h"
#include "rdp.h"
@ -94,7 +93,6 @@ extern struct isa_driver csdriver;
extern struct isa_driver cxdriver;
extern struct isa_driver eldriver;
extern struct isa_driver fedriver;
extern struct isa_driver iedriver;
extern struct isa_driver ledriver;
extern struct isa_driver lncdriver;
extern struct isa_driver rdpdriver;
@ -229,9 +227,6 @@ static struct old_isa_driver old_drivers[] = {
/* NET */
#if NIE > 0
{ INTR_TYPE_NET, &iedriver },
#endif
#if NLE > 0
{ INTR_TYPE_NET, &ledriver },
#endif

274
sys/pci/adv_pci.c
View File

@ -1,274 +0,0 @@
/*
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* Connectivity Products:
* ABP920 - Bus-Master PCI (16 CDB)
* ABP930 - Bus-Master PCI (16 CDB) *
* ABP930U - Bus-Master PCI Ultra (16 CDB)
* ABP930UA - Bus-Master PCI Ultra (16 CDB)
* ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
* ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
*
* Single Channel Products:
* ABP940 - Bus-Master PCI (240 CDB)
* ABP940U - Bus-Master PCI Ultra (240 CDB)
* ABP970 - Bus-Master PCI MAC/PC (240 CDB)
* ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
*
* Dual Channel Products:
* ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
*
* Footnotes:
* * This board has been sold by SIIG as the Fast SCSI Pro PCI.
* ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
*
* Copyright (c) 1997 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <pci/pcireg.h>
#include <pci/pcivar.h>
#include <dev/advansys/advansys.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
#define PCI_DEVICE_ID_ADVANSYS_ULTRA 0x130010CD
#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
static const char* advpciprobe(pcici_t tag, pcidi_t type);
static void advpciattach(pcici_t config_id, int unit);
/*
* The overrun buffer shared amongst all PCI adapters.
*/
static u_int8_t* overrun_buf;
static bus_dma_tag_t overrun_dmat;
static bus_dmamap_t overrun_dmamap;
static bus_addr_t overrun_physbase;
static struct pci_device adv_pci_driver = {
"adv",
advpciprobe,
advpciattach,
&adv_unit,
NULL
};
COMPAT_PCI_DRIVER (adv_pci, adv_pci_driver);
static const char*
advpciprobe(pcici_t tag, pcidi_t type)
{
int rev = pci_conf_read(tag, PCI_CLASS_REG) & 0xff;
switch (type) {
case PCI_DEVICE_ID_ADVANSYS_1200A:
return ("AdvanSys ASC1200A SCSI controller");
case PCI_DEVICE_ID_ADVANSYS_1200B:
return ("AdvanSys ASC1200B SCSI controller");
case PCI_DEVICE_ID_ADVANSYS_ULTRA:
if (rev == PCI_DEVICE_REV_ADVANSYS_3150)
return ("AdvanSys ASC3150 Ultra SCSI controller");
else
return ("AdvanSys ASC3050 Ultra SCSI controller");
break;
default:
break;
}
return (NULL);
}
static void
advpciattach(pcici_t config_id, int unit)
{
u_int16_t io_port;
struct adv_softc *adv;
u_int32_t id;
u_int32_t command;
int error;
/*
* Determine the chip version.
*/
id = pci_cfgread(config_id, PCI_ID_REG, /*bytes*/4);
command = pci_cfgread(config_id, PCIR_COMMAND, /*bytes*/1);
/*
* These cards do not allow memory mapped accesses, so we must
* ensure that I/O accesses are available or we won't be able
* to talk to them.
*/
if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
!= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
pci_cfgwrite(config_id, PCIR_COMMAND, command, /*bytes*/1);
}
/*
* Early chips can't handle non-zero latency timer settings.
*/
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
pci_cfgwrite(config_id, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
}
if (pci_map_port(config_id, PCI_BASEADR0, &io_port) == 0)
return;
if (adv_find_signature(I386_BUS_SPACE_IO, io_port) == 0)
return;
adv = adv_alloc(unit, I386_BUS_SPACE_IO, io_port);
if (adv == NULL)
return;
/* Allocate a dmatag for our transfer DMA maps */
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
/*boundary*/0,
/*lowaddr*/ADV_PCI_MAX_DMA_ADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/BUS_SPACE_UNRESTRICTED,
/*maxsegsz*/ADV_PCI_MAX_DMA_COUNT,
/*flags*/0,
&adv->parent_dmat);
if (error != 0) {
printf("%s: Could not allocate DMA tag - error %d\n",
adv_name(adv), error);
adv_free(adv);
return;
}
adv->init_level++;
if (overrun_buf == NULL) {
/* Need to allocate our overrun buffer */
if (bus_dma_tag_create(adv->parent_dmat,
/*alignment*/8, /*boundary*/0,
ADV_PCI_MAX_DMA_ADDR, BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
ADV_OVERRUN_BSIZE, /*nsegments*/1,
BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
&overrun_dmat) != 0) {
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
return;
}
if (bus_dmamem_alloc(overrun_dmat,
(void **)&overrun_buf,
BUS_DMA_NOWAIT,
&overrun_dmamap) != 0) {
bus_dma_tag_destroy(overrun_dmat);
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
return;
}
/* And permanently map it in */
bus_dmamap_load(overrun_dmat, overrun_dmamap,
overrun_buf, ADV_OVERRUN_BSIZE,
adv_map, &overrun_physbase,
/*flags*/0);
}
adv->overrun_physbase = overrun_physbase;
/*
* Stop the chip.
*/
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
adv->type = ADV_PCI;
/*
* Setup active negation and signal filtering.
*/
{
u_int8_t extra_cfg;
if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
adv->type |= ADV_ULTRA;
if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3150)
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
else if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
else
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
}
if (adv_init(adv) != 0) {
adv_free(adv);
return;
}
adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
#if CC_DISABLE_PCI_PARITY_INT
{
u_int16_t config_msw;
config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
config_msw &= 0xFFC0;
ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
}
#endif
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
adv->fix_asyn_xfer = ~0;
}
if ((pci_map_int(config_id, adv_intr, (void *)adv, &cam_imask)) == 0) {
adv_free(adv);
return;
}
adv_attach(adv);
}

1860
sys/pci/ahc_pci.c
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441
sys/pci/if_fpa.c
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@ -1,441 +0,0 @@
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software withough specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
/*
* DEC PDQ FDDI Controller; code for BSD derived operating systems
*
* This module supports the DEC DEFPA PCI FDDI Controller
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#if defined(__bsdi__) || defined(__NetBSD__)
#include <sys/device.h>
#endif
#include <net/if.h>
#if defined(__FreeBSD__)
#include "fpa.h"
#include <sys/eventhandler.h>
#include <net/ethernet.h>
#include <net/if_arp.h>
#include <pci/pcivar.h>
#include <dev/pdq/pdqvar.h>
#include <dev/pdq/pdqreg.h>
#elif defined(__bsdi__)
#include <i386/isa/isavar.h>
#include <i386/isa/icu.h>
#ifndef DRQNONE
#define DRQNONE 0
#endif
#if _BSDI_VERSION < 199401
#define IRQSHARE 0
#endif
#elif defined(__NetBSD__)
#include <dev/pci/pcivar.h>
#include <dev/ic/pdqvar.h>
#include <dev/ic/pdqreg.h>
#endif /* __NetBSD__ */
#define DEC_VENDORID 0x1011
#define DEFPA_CHIPID 0x000F
#define PCI_VENDORID(x) ((x) & 0xFFFF)
#define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
#define DEFPA_LATENCY 0x88
#define PCI_CFLT 0x0C /* Configuration Latency */
#define PCI_CBMA 0x10 /* Configuration Base Memory Address */
#define PCI_CBIO 0x14 /* Configuration Base I/O Address */
#if defined(__FreeBSD__)
#if NFPA < 4
#undef NFPA
#define NFPA 4
#endif
static pdq_softc_t *pdqs_pci[NFPA];
#define PDQ_PCI_UNIT_TO_SOFTC(unit) (pdqs_pci[unit])
#if BSD >= 199506
#define pdq_pci_ifwatchdog NULL
#endif
#elif defined(__bsdi__)
extern struct cfdriver fpacd;
#define PDQ_PCI_UNIT_TO_SOFTC(unit) ((pdq_softc_t *)fpacd.cd_devs[unit])
#elif defined(__NetBSD__)
extern struct cfattach fpa_ca;
extern struct cfdriver fpa_cd;
#define PDQ_PCI_UNIT_TO_SOFTC(unit) ((pdq_softc_t *)fpa_cd.cd_devs[unit])
#define pdq_pci_ifwatchdog NULL
#endif
#ifndef pdq_pci_ifwatchdog
static ifnet_ret_t
pdq_pci_ifwatchdog(
int unit)
{
pdq_ifwatchdog(&PDQ_PCI_UNIT_TO_SOFTC(unit)->sc_if);
}
#endif
#if defined(__FreeBSD__) && BSD >= 199506
static void
pdq_pci_ifintr(
void *arg)
{
(void) pdq_interrupt(((pdq_softc_t *) arg)->sc_pdq);
}
#else
static int
pdq_pci_ifintr(
void *arg)
{
pdq_softc_t * const sc = (pdq_softc_t *) arg;
#ifdef __FreeBSD__
return pdq_interrupt(sc->sc_pdq);
#elif defined(__bsdi__) || defined(__NetBSD__)
(void) pdq_interrupt(sc->sc_pdq);
return 1;
#endif
}
#endif /* __FreeBSD && BSD */
#if defined(__FreeBSD__)
static void pdq_pci_shutdown(void *, int);
/*
* This is the PCI configuration support. Since the PDQ is available
* on both EISA and PCI boards, one must be careful in how defines the
* PDQ in the config file.
*/
static const char *
pdq_pci_probe(
pcici_t config_id,
pcidi_t device_id)
{
if (PCI_VENDORID(device_id) == DEC_VENDORID &&
PCI_CHIPID(device_id) == DEFPA_CHIPID)
return "Digital DEFPA PCI FDDI Controller";
return NULL;
}
static void
pdq_pci_attach(
pcici_t config_id,
int unit)
{
pdq_softc_t *sc;
vm_offset_t va_csrs, pa_csrs;
pdq_uint32_t data;
if (unit == NFPA) {
printf("fpa%d: not configured; kernel is built for only %d device%s.\n",
unit, NFPA, NFPA == 1 ? "" : "s");
return;
}
data = pci_conf_read(config_id, PCI_CFLT);
if ((data & 0xFF00) < (DEFPA_LATENCY << 8)) {
data &= ~0xFF00;
data |= DEFPA_LATENCY << 8;
pci_conf_write(config_id, PCI_CFLT, data);
}
sc = (pdq_softc_t *) malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT);
if (sc == NULL)
return;
bzero(sc, sizeof(pdq_softc_t)); /* Zero out the softc*/
if (!pci_map_mem(config_id, PCI_CBMA, &va_csrs, &pa_csrs)) {
free((void *) sc, M_DEVBUF);
return;
}
sc->sc_if.if_name = "fpa";
sc->sc_if.if_unit = unit;
sc->sc_membase = (pdq_bus_memaddr_t) va_csrs;
sc->sc_pdq = pdq_initialize(PDQ_BUS_PCI, sc->sc_membase,
sc->sc_if.if_name, sc->sc_if.if_unit,
(void *) sc, PDQ_DEFPA);
if (sc->sc_pdq == NULL) {
free((void *) sc, M_DEVBUF);
return;
}
bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
pdqs_pci[unit] = sc;
pdq_ifattach(sc, pdq_pci_ifwatchdog);
pci_map_int(config_id, pdq_pci_ifintr, (void*) sc, &net_imask);
EVENTHANDLER_REGISTER(shutdown_post_sync, pdq_pci_shutdown, sc,
SHUTDOWN_PRI_DEFAULT);
}
static void
pdq_pci_shutdown(
void *sc,
int howto)
{
pdq_hwreset(((pdq_softc_t *)sc)->sc_pdq);
}
static u_long pdq_pci_count;
static struct pci_device fpadevice = {
"fpa",
pdq_pci_probe,
pdq_pci_attach,
&pdq_pci_count,
NULL
};
COMPAT_PCI_DRIVER (fpa, fpadevice);
#elif defined(__bsdi__)
static int
pdq_pci_match(
pci_devaddr_t *pa)
{
int irq;
int id;
id = pci_inl(pa, PCI_VENDOR_ID);
if (PCI_VENDORID(id) != DEC_VENDORID || PCI_CHIPID(id) != DEFPA_CHIPID)
return 0;
irq = pci_inl(pa, PCI_I_LINE) & 0xFF;
if (irq == 0 || irq >= 16)
return 0;
return 1;
}
int
pdq_pci_probe(
struct device *parent,
struct cfdata *cf,
void *aux)
{
struct isa_attach_args *ia = (struct isa_attach_args *) aux;
pdq_uint32_t irq, data;
pci_devaddr_t *pa;
pa = pci_scan(pdq_pci_match);
if (pa == NULL)
return 0;
irq = (1 << (pci_inl(pa, PCI_I_LINE) & 0xFF));
if (ia->ia_irq != IRQUNK && irq != ia->ia_irq) {
printf("fpa%d: error: desired IRQ of %d does not match device's actual IRQ of %d\n",
cf->cf_unit,
ffs(ia->ia_irq) - 1, ffs(irq) - 1);
return 0;
}
if (ia->ia_irq == IRQUNK) {
(void) isa_irqalloc(irq);
ia->ia_irq = irq;
}
/* PCI bus masters don't use host DMA channels */
ia->ia_drq = DRQNONE;
/* Get the memory base address; assume the BIOS set it up correctly */
ia->ia_maddr = (caddr_t) (pci_inl(pa, PCI_CBMA) & ~7);
pci_outl(pa, PCI_CBMA, 0xFFFFFFFF);
ia->ia_msize = ((~pci_inl(pa, PCI_CBMA)) | 7) + 1;
pci_outl(pa, PCI_CBMA, (int) ia->ia_maddr);
/* Disable I/O space access */
pci_outl(pa, PCI_COMMAND, pci_inl(pa, PCI_COMMAND) & ~1);
ia->ia_iobase = 0;
ia->ia_iosize = 0;
/* Make sure the latency timer is what the DEFPA likes */
data = pci_inl(pa, PCI_CFLT);
if ((data & 0xFF00) < (DEFPA_LATENCY << 8)) {
data &= ~0xFF00;
data |= DEFPA_LATENCY << 8;
pci_outl(pa, PCI_CFLT, data);
}
ia->ia_irq |= IRQSHARE;
return 1;
}
void
pdq_pci_attach(
struct device *parent,
struct device *self,
void *aux)
{
pdq_softc_t *sc = (pdq_softc_t *) self;
register struct isa_attach_args *ia = (struct isa_attach_args *) aux;
register struct ifnet *ifp = &sc->sc_if;
int i;
sc->sc_if.if_unit = sc->sc_dev.dv_unit;
sc->sc_if.if_name = "fpa";
sc->sc_if.if_flags = 0;
sc->sc_membase = (pdq_bus_memaddr_t) mapphys((vm_offset_t)ia->ia_maddr, ia->ia_msize);
sc->sc_pdq = pdq_initialize(PDQ_BUS_PCI, sc->sc_membase,
sc->sc_if.if_name, sc->sc_if.if_unit,
(void *) sc, PDQ_DEFPA);
if (sc->sc_pdq == NULL) {
printf("fpa%d: initialization failed\n", sc->sc_if.if_unit);
return;
}
bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
pdq_ifattach(sc, pdq_pci_ifwatchdog);
isa_establish(&sc->sc_id, &sc->sc_dev);
sc->sc_ih.ih_fun = pdq_pci_ifintr;
sc->sc_ih.ih_arg = (void *)sc;
intr_establish(ia->ia_irq, &sc->sc_ih, DV_NET);
sc->sc_ats.func = (void (*)(void *)) pdq_hwreset;
sc->sc_ats.arg = (void *) sc->sc_pdq;
atshutdown(&sc->sc_ats, ATSH_ADD);
}
struct cfdriver fpacd = {
0, "fpa", pdq_pci_probe, pdq_pci_attach,
#if _BSDI_VERSION >= 199401
DV_IFNET,
#endif
sizeof(pdq_softc_t)
};
#elif defined(__NetBSD__)
static int
pdq_pci_match(
struct device *parent,
void *match,
void *aux)
{
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
if (PCI_VENDORID(pa->pa_id) != DEC_VENDORID)
return 0;
if (PCI_CHIPID(pa->pa_id) == DEFPA_CHIPID)
return 1;
return 0;
}
static void
pdq_pci_attach(
struct device * const parent,
struct device * const self,
void * const aux)
{
pdq_softc_t * const sc = (pdq_softc_t *) self;
struct pci_attach_args * const pa = (struct pci_attach_args *) aux;
pdq_uint32_t data;
pci_intr_handle_t intrhandle;
const char *intrstr;
#ifdef PDQ_IOMAPPED
bus_io_addr_t iobase;
bus_io_size_t iosize;
#else
bus_mem_addr_t membase;
bus_mem_size_t memsize;
#endif
data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFLT);
if ((data & 0xFF00) < (DEFPA_LATENCY << 8)) {
data &= ~0xFF00;
data |= DEFPA_LATENCY << 8;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_CFLT, data);
}
sc->sc_bc = pa->pa_bc;
bcopy(sc->sc_dev.dv_xname, sc->sc_if.if_xname, IFNAMSIZ);
sc->sc_if.if_flags = 0;
sc->sc_if.if_softc = sc;
#ifdef PDQ_IOMAPPED
if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_CBIO, &iobase, &iosize)
|| bus_io_map(pa->pa_bc, iobase, iosize, &sc->sc_iobase))
return;
#else
if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_CBMA, &membase, &memsize, NULL)
|| bus_mem_map(pa->pa_bc, membase, memsize, 0, &sc->sc_membase))
return;
#endif
sc->sc_pdq = pdq_initialize(sc->sc_bc, sc->sc_membase,
sc->sc_if.if_xname, 0,
(void *) sc, PDQ_DEFPA);
if (sc->sc_pdq == NULL) {
printf("%s: initialization failed\n", sc->sc_dev.dv_xname);
return;
}
bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
pdq_ifattach(sc, pdq_pci_ifwatchdog);
if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
pa->pa_intrline, &intrhandle)) {
printf("%s: couldn't map interrupt\n", self->dv_xname);
return;
}
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, pdq_pci_ifintr, sc);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt", self->dv_xname);
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
return;
}
sc->sc_ats = shutdownhook_establish((void (*)(void *)) pdq_hwreset, sc->sc_pdq);
if (sc->sc_ats == NULL)
printf("%s: warning: couldn't establish shutdown hook\n", self->dv_xname);
if (intrstr != NULL)
printf("%s: interrupting at %s\n", self->dv_xname, intrstr);
}
struct cfattach fpa_ca = {
sizeof(pdq_softc_t), pdq_pci_match, pdq_pci_attach
};
struct cfdriver fpa_cd = {
0, "fpa", DV_IFNET
};
#endif /* __NetBSD__ */

142
sys/pci/if_vx_pci.c
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@ -1,142 +0,0 @@
/*
* Copyright (C) 1996 Naoki Hamada <nao@tom-yam.or.jp>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "vx.h"
#if NVX > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/eventhandler.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <pci/pcivar.h>
#include <dev/vx/if_vxreg.h>
static void vx_pci_shutdown(void *, int);
static const char *vx_pci_probe(pcici_t, pcidi_t);
static void vx_pci_attach(pcici_t, int unit);
static void
vx_pci_shutdown(
void *sc,
int howto)
{
vxstop(sc);
vxfree(sc);
}
static const char*
vx_pci_probe(
pcici_t config_id,
pcidi_t device_id)
{
if(device_id == 0x590010b7ul)
return "3COM 3C590 Etherlink III PCI";
if(device_id == 0x595010b7ul || device_id == 0x595110b7ul ||
device_id == 0x595210b7ul)
return "3COM 3C595 Fast Etherlink III PCI";
/*
* The (Fast) Etherlink XL adapters are now supported by
* the xl driver, which uses bus master DMA and is much
* faster. (And which also supports the 3c905B.
*/
#ifdef VORTEX_ETHERLINK_XL
if(device_id == 0x900010b7ul || device_id == 0x900110b7ul)
return "3COM 3C900 Etherlink XL PCI";
if(device_id == 0x905010b7ul || device_id == 0x905110b7ul)
return "3COM 3C905 Fast Etherlink XL PCI";
#endif
return NULL;
}
static void
vx_pci_attach(
pcici_t config_id,
int unit)
{
struct vx_softc *sc;
if (unit >= NVX) {
printf("vx%d: not configured; kernel is built for only %d device%s.\n",
unit, NVX, NVX == 1 ? "" : "s");
return;
}
if ((sc = vxalloc(unit)) == NULL) {
return;
}
sc->vx_io_addr = pci_conf_read(config_id, 0x10) & 0xffffffe0;
if (vxattach(sc) == 0) {
return;
}
/* defect check for 3C590 */
if ((pci_conf_read(config_id, 0) >> 16) == 0x5900) {
GO_WINDOW(0);
if (vxbusyeeprom(sc))
return;
outw(BASE + VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD | EEPROM_SOFT_INFO_2);
if (vxbusyeeprom(sc))
return;
if (!(inw(BASE + VX_W0_EEPROM_DATA) & NO_RX_OVN_ANOMALY)) {
printf("Warning! Defective early revision adapter!\n");
}
}
/*
* Add shutdown hook so that DMA is disabled prior to reboot. Not
* doing do could allow DMA to corrupt kernel memory during the
* reboot before the driver initializes.
*/
EVENTHANDLER_REGISTER(shutdown_post_sync, vx_pci_shutdown, sc,
SHUTDOWN_PRI_DEFAULT);
pci_map_int(config_id, vxintr, (void *) sc, &net_imask);
}
static struct pci_device vxdevice = {
"vx",
vx_pci_probe,
vx_pci_attach,
&vx_count,
NULL
};
COMPAT_PCI_DRIVER (vx, vxdevice);
#endif /* NVX */