x86 topo: add some comments, descriptions and references to documentation
Plus a minor cosmetic change. MFC after: 1 month
This commit is contained in:
Andriy Gapon
parent
b799783990
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c77702de74
@ -53,9 +53,7 @@ __FBSDID("$FreeBSD$");
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#ifdef SMP
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MALLOC_DEFINE(M_TOPO, "toponodes", "SMP topology data");
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#endif
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#ifdef SMP
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volatile cpuset_t stopped_cpus;
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volatile cpuset_t started_cpus;
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volatile cpuset_t suspended_cpus;
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@ -895,6 +893,10 @@ topo_init_root(struct topo_node *root)
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root->type = TOPO_TYPE_SYSTEM;
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}
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/*
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* Add a child node with the given ID under the given parent.
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* Do nothing if there is already a child with that ID.
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*/
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struct topo_node *
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topo_add_node_by_hwid(struct topo_node *parent, int hwid,
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topo_node_type type, uintptr_t subtype)
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@ -921,6 +923,9 @@ topo_add_node_by_hwid(struct topo_node *parent, int hwid,
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return (node);
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}
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/*
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* Find a child node with the given ID under the given parent.
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*/
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struct topo_node *
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topo_find_node_by_hwid(struct topo_node *parent, int hwid,
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topo_node_type type, uintptr_t subtype)
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@ -938,6 +943,12 @@ topo_find_node_by_hwid(struct topo_node *parent, int hwid,
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return (NULL);
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}
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/*
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* Given a node change the order of its parent's child nodes such
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* that the node becomes the firt child while preserving the cyclic
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* order of the children. In other words, the given node is promoted
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* by rotation.
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*/
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void
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topo_promote_child(struct topo_node *child)
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{
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@ -959,6 +970,10 @@ topo_promote_child(struct topo_node *child)
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}
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}
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/*
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* Iterate to the next node in the depth-first search (traversal) of
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* the topology tree.
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*/
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struct topo_node *
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topo_next_node(struct topo_node *top, struct topo_node *node)
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{
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@ -977,6 +992,10 @@ topo_next_node(struct topo_node *top, struct topo_node *node)
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return (NULL);
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}
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/*
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* Iterate to the next node in the depth-first search of the topology tree,
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* but without descending below the current node.
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*/
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struct topo_node *
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topo_next_nonchild_node(struct topo_node *top, struct topo_node *node)
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{
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@ -992,6 +1011,10 @@ topo_next_nonchild_node(struct topo_node *top, struct topo_node *node)
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return (NULL);
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}
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/*
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* Assign the given ID to the given topology node that represents a logical
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* processor.
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*/
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void
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topo_set_pu_id(struct topo_node *node, cpuid_t id)
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{
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@ -1013,6 +1036,14 @@ topo_set_pu_id(struct topo_node *node, cpuid_t id)
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}
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}
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/*
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* Check if the topology is uniform, that is, each package has the same number
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* of cores in it and each core has the same number of threads (logical
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* processors) in it. If so, calculate the number of package, the number of
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* cores per package and the number of logical processors per core.
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* 'all' parameter tells whether to include administratively disabled logical
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* processors into the analysis.
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*/
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int
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topo_analyze(struct topo_node *topo_root, int all,
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int *pkg_count, int *cores_per_pkg, int *thrs_per_core)
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@ -176,6 +176,9 @@ mask_width(u_int x)
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return (fls(x << (1 - powerof2(x))) - 1);
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}
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/*
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* Add a cache level to the cache topology description.
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*/
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static int
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add_deterministic_cache(int type, int level, int share_count)
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{
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@ -217,6 +220,16 @@ add_deterministic_cache(int type, int level, int share_count)
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return (1);
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}
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/*
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* Determine topology of processing units and caches for AMD CPUs.
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* See:
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* - AMD CPUID Specification (Publication # 25481)
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* - BKDG For AMD Family 10h Processors (Publication # 31116), section 2.15
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* - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
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* XXX At the moment the code does not recognize grouping of AMD CMT threads,
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* if supported, into cores, so each thread is treated as being in its own
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* core. In other words, each logical CPU is considered to be a core.
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*/
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static void
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topo_probe_amd(void)
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{
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@ -277,6 +290,15 @@ topo_probe_amd(void)
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}
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}
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/*
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* Determine topology of processing units for Intel CPUs
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* using CPUID Leaf 1 and Leaf 4, if supported.
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* See:
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* - Intel 64 Architecture Processor Topology Enumeration
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* - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
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* Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
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* FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
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*/
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static void
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topo_probe_intel_0x4(void)
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{
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@ -302,6 +324,15 @@ topo_probe_intel_0x4(void)
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pkg_id_shift = core_id_shift + mask_width(max_cores);
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}
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/*
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* Determine topology of processing units for Intel CPUs
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* using CPUID Leaf 11, if supported.
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* See:
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* - Intel 64 Architecture Processor Topology Enumeration
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* - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
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* Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
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* FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
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*/
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static void
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topo_probe_intel_0xb(void)
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{
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@ -342,6 +373,14 @@ topo_probe_intel_0xb(void)
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}
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}
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/*
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* Determine topology of caches for Intel CPUs.
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* See:
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* - Intel 64 Architecture Processor Topology Enumeration
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* - Intel 64 and IA-32 Architectures Software Developer’s Manual
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* Volume 2A: Instruction Set Reference, A-M,
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* CPUID instruction
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*/
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static void
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topo_probe_intel_caches(void)
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{
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@ -376,14 +415,16 @@ topo_probe_intel_caches(void)
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}
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}
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/*
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* Determine topology of processing units and caches for Intel CPUs.
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* See:
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* - Intel 64 Architecture Processor Topology Enumeration
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*/
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static void
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topo_probe_intel(void)
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{
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/*
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* See Intel(R) 64 Architecture Processor
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* Topology Enumeration article for details.
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*
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* Note that 0x1 <= cpu_high < 4 case should be
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* compatible with topo_probe_intel_0x4() logic when
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* CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
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@ -640,6 +681,12 @@ cpu_mp_announce(void)
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}
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}
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/*
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* Add a scheduling group, a group of logical processors sharing
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* a particular cache (and, thus having an affinity), to the scheduling
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* topology.
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* This function recursively works on lower level caches.
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*/
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static void
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x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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{
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@ -657,6 +704,11 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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else
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cg_root->cg_level = root->subtype;
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/*
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* Check how many core nodes we have under the given root node.
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* If we have multiple logical processors, but not multiple
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* cores, then those processors must be hardware threads.
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*/
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ncores = 0;
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node = root;
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while (node != NULL) {
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@ -673,6 +725,13 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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root->cpu_count > 1 && ncores < 2)
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cg_root->cg_flags = CG_FLAG_SMT;
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/*
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* Find out how many cache nodes we have under the given root node.
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* We ignore cache nodes that cover all the same processors as the
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* root node. Also, we do not descend below found cache nodes.
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* That is, we count top-level "non-redundant" caches under the root
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* node.
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*/
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nchildren = 0;
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node = root;
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while (node != NULL) {
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@ -689,6 +748,10 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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cg_root->cg_child = smp_topo_alloc(nchildren);
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cg_root->cg_children = nchildren;
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/*
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* Now find again the same cache nodes as above and recursively
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* build scheduling topologies for them.
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*/
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node = root;
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i = 0;
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while (node != NULL) {
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@ -705,6 +768,9 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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}
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}
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/*
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* Build the MI scheduling topology from the discovered hardware topology.
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*/
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struct cpu_group *
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cpu_topo(void)
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{
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@ -719,6 +785,9 @@ cpu_topo(void)
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}
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/*
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* Add a logical CPU to the topology.
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*/
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void
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cpu_add(u_int apic_id, char boot_cpu)
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{
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