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Clean data cache before instruction cache in armv7_icache_sync_range().

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Also ensure dsb precedes isb in all icache maintenance routines (first
do a data sync, then stall the instruction stream until it finishes).

Submitted by:	Michal Meloun
This commit is contained in:
ian 2015-03-09 14:42:25 +00:00
parent 558260a403
commit c78382ce59
1 changed files with 4 additions and 4 deletions
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8
sys/arm/arm/cpufunc_asm_armv7.S
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@ -247,8 +247,8 @@ ENTRY(armv7_idcache_wbinv_range)
add r0, r0, ip
subs r1, r1, ip
bhi .Larmv7_id_wbinv_next
isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
isb /* instruction synchronization barrier */
RET
END(armv7_idcache_wbinv_range)
@ -258,8 +258,8 @@ ENTRY_NP(armv7_icache_sync_all)
#else
mcr CP15_ICIALLU
#endif
isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
isb /* instruction synchronization barrier */
RET
END(armv7_icache_sync_all)
@ -267,13 +267,13 @@ ENTRY_NP(armv7_icache_sync_range)
ldr ip, .Larmv7_icache_line_size
ldr ip, [ip]
.Larmv7_sync_next:
mcr CP15_ICIMVAU(r0)
mcr CP15_DCCMVAC(r0)
mcr CP15_ICIMVAU(r0)
add r0, r0, ip
subs r1, r1, ip
bhi .Larmv7_sync_next
isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
isb /* instruction synchronization barrier */
RET
END(armv7_icache_sync_range)