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There is no reason to do i+dcache writeback and invalidate when changing

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the translation table (this may be left over from armv5 days).  It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.

Submitted by:	Michal Meloun
This commit is contained in:
Ian Lepore 2015-02-23 20:09:05 +00:00
parent 0ccab3af38
commit c82bcdb25e
1 changed files with 0 additions and 4 deletions
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4
sys/arm/arm/cpufunc_asm_armv7.S
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@ -72,11 +72,7 @@ __FBSDID("$FreeBSD$");
#endif
ENTRY(armv7_setttb)
stmdb sp!, {r0, lr}
bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
ldmia sp!, {r0, lr}
dsb
orr r0, r0, #PT_ATTR
mcr CP15_TTBR0(r0)
isb