Second beta release of device driver for SMC/WD 80x3 ethernet boards +
some additional comments.
This commit is contained in:
David Greenman
parent
258445a954
commit
c8378b88c6
@ -17,6 +17,13 @@
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* Modification history
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*
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* $Log: if_ed.c,v $
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* Revision 1.9 93/06/23 03:48:14 davidg
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* fixed minor typo introduced when cleaning up probe routine
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*
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* Revision 1.8 93/06/23 03:37:19 davidg
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* cleaned up/added some comments. Also improved readability of a part of
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* the probe routine.
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*
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* Revision 1.7 93/06/22 04:45:01 davidg
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* (no additional changes) Second beta release
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*
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@ -286,16 +293,31 @@ ed_probe(isa_dev)
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for (i=0; i<8; i++)
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printf("%x -> %x\n", i, inb(sc->asic_addr + i));
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#endif
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/*
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* Check 83C584 interrupt configuration register if this board has one
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* XXX - we could also check the IO address register. But why
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* bother...if we get past this, it *has* to be correct.
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*/
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if (sc->type & ED_WD_SOFTCONFIG) {
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iptr = inb(isa_dev->id_iobase + 1) & 4 |
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((inb(isa_dev->id_iobase+4) & 0x60) >> 5);
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/*
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* Assemble together the encoded interrupt number.
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*/
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iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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/*
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* Translate it using translation table, and check for correctness.
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*/
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if (ed_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq doesn't match board configured irq\n",
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isa_dev->id_unit);
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return(0);
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}
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outb(isa_dev->id_iobase+4, inb(isa_dev->id_iobase+4) | 0x80);
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/*
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* Enable the interrupt.
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*/
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outb(isa_dev->id_iobase + ED_WD_IRR,
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inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
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}
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sc->memwidth = memwidth;
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@ -659,6 +681,9 @@ ed_attach(isa_dev)
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else
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ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
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/*
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* Attach the interface
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*/
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if_attach(ifp);
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#if NBPFILTER > 0
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@ -672,9 +697,10 @@ ed_attach(isa_dev)
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while ((ifa != 0) && (ifa->ifa_addr != 0) &&
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(ifa->ifa_addr->sa_family != AF_LINK))
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ifa = ifa->ifa_next;
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/*
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* If we find an AF_LINK type entry we fill in the hardware address
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* If we find an AF_LINK type entry we fill in the hardware address.
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* This is useful for netstat(1) to keep track of which interface
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* is which.
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*/
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if ((ifa != 0) && (ifa->ifa_addr != 0)) {
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/*
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@ -742,6 +768,10 @@ ed_stop(unit)
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}
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}
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/*
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* Device timeout/watchdog routine. Entered if the device neglects to
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* generate an interrupt after a transmit has been started on it.
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*/
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int
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ed_watchdog(unit)
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int unit;
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@ -904,6 +934,9 @@ ed_init(unit)
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(void) splx(s);
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}
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/*
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* This routine actually starts the transmission on the interface
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*/
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static inline void ed_xmit(ifp)
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struct ifnet *ifp;
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{
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@ -928,13 +961,16 @@ static inline void ed_xmit(ifp)
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outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
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/*
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* Set page 0, Remote DMA complete, Transmit Packet, and Start
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* Set page 0, Remote DMA complete, Transmit Packet, and *Start*
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*/
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outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
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sc->xmit_busy = 1;
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sc->data_buffered = 0;
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/*
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* Switch buffers if we are doing double-buffered transmits
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*/
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if ((sc->txb_next == 0) && (sc->txb_cnt > 1))
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sc->txb_next = 1;
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else
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@ -966,14 +1002,24 @@ ed_start(ifp)
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u_char laar_tmp;
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outloop:
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/*
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* See if there is room to send more data (i.e. one or both of the
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* buffers is empty).
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*/
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if (sc->data_buffered)
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if (sc->xmit_busy) {
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/*
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* No room. Indicate this to the outside world
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* and exit.
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*/
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ifp->if_flags |= IFF_OACTIVE;
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return;
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} else {
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/*
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* Data is buffered, but we're not transmitting, so
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* start the xmit on the buffered data.
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* Note that ed_xmit() resets the data_buffered flag
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* before returning
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* before returning.
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*/
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ed_xmit(ifp);
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}
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@ -1104,6 +1150,10 @@ ed_start(ifp)
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m_freem(m0);
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/*
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* If we are doing double-buffering, a buffer might be free to
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* fill with another packet, so loop back to the top.
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*/
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if (sc->txb_cnt > 1)
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goto outloop;
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else {
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@ -1260,7 +1310,7 @@ edintr(unit)
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sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
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/*
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* reset watchdog timer
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* clear watchdog timer
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*/
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sc->arpcom.ac_if.if_timer = 0;
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}
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@ -1310,7 +1360,7 @@ edintr(unit)
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sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
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/*
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* reset watchdog timer
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* clear watchdog timer
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*/
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sc->arpcom.ac_if.if_timer = 0;
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@ -1698,9 +1748,15 @@ ed_ring_to_mbuf(sc,src,dst,total_len)
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if (amount == 0) { /* no more data in this mbuf, alloc another */
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/*
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* if there is enough data for an mbuf cluster, attempt
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* to allocate one of those, otherwise, a regular mbuf
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* will do.
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* If there is enough data for an mbuf cluster, attempt
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* to allocate one of those, otherwise, a regular
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* mbuf will do.
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* Note that a regular mbuf is always required, even if
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* we get a cluster - getting a cluster does not
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* allocate any mbufs, and one is needed to assign
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* the cluster to. The mbuf that has a cluster
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* extension can not be used to contain data - only
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* the cluster can contain data.
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*/
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dst = m;
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MGET(m, M_DONTWAIT, MT_DATA);
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@ -1,5 +1,14 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
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*
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* $Log: if_edreg.h,v $
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* Revision 1.2 93/06/23 03:03:05 davidg
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* added some additional definitions for the 83C584 bus interface
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* chip (SMC/WD boards)
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*
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* Revision 1.1 93/06/23 03:01:07 davidg
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* Initial revision
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*
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*/
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/*
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@ -573,13 +582,23 @@ struct ed_ring {
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#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
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#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
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#define ED_WD_ICR_IR2 0x04 /* select second set of IRQs */
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#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
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#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
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#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
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#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
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#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
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#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
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/*
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* IO Address Register (IAR)
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*/
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#define ED_WD_IAR 2
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/*
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* EEROM Address Register
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*/
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#define ED_WD_EAR 3
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/*
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* Interrupt Request Register (IRR)
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*/
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@ -590,6 +609,22 @@ struct ed_ring {
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#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
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#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
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#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
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/*
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* The three bit of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 2/9
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* 0 0 1 3
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* 0 1 0 5
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* 0 1 1 7
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* 1 0 0 10
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* 1 0 1 11
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* 1 1 0 15
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* 1 1 1 4
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*/
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#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
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#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
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#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
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/*
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@ -17,6 +17,13 @@
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* Modification history
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*
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* $Log: if_ed.c,v $
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* Revision 1.9 93/06/23 03:48:14 davidg
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* fixed minor typo introduced when cleaning up probe routine
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*
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* Revision 1.8 93/06/23 03:37:19 davidg
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* cleaned up/added some comments. Also improved readability of a part of
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* the probe routine.
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*
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* Revision 1.7 93/06/22 04:45:01 davidg
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* (no additional changes) Second beta release
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*
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@ -286,16 +293,31 @@ ed_probe(isa_dev)
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for (i=0; i<8; i++)
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printf("%x -> %x\n", i, inb(sc->asic_addr + i));
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#endif
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/*
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* Check 83C584 interrupt configuration register if this board has one
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* XXX - we could also check the IO address register. But why
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* bother...if we get past this, it *has* to be correct.
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*/
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if (sc->type & ED_WD_SOFTCONFIG) {
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iptr = inb(isa_dev->id_iobase + 1) & 4 |
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((inb(isa_dev->id_iobase+4) & 0x60) >> 5);
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/*
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* Assemble together the encoded interrupt number.
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*/
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iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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/*
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* Translate it using translation table, and check for correctness.
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*/
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if (ed_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq doesn't match board configured irq\n",
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isa_dev->id_unit);
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return(0);
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}
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outb(isa_dev->id_iobase+4, inb(isa_dev->id_iobase+4) | 0x80);
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/*
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* Enable the interrupt.
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*/
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outb(isa_dev->id_iobase + ED_WD_IRR,
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inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
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}
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sc->memwidth = memwidth;
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@ -659,6 +681,9 @@ ed_attach(isa_dev)
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else
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ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
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/*
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* Attach the interface
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*/
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if_attach(ifp);
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#if NBPFILTER > 0
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@ -672,9 +697,10 @@ ed_attach(isa_dev)
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while ((ifa != 0) && (ifa->ifa_addr != 0) &&
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(ifa->ifa_addr->sa_family != AF_LINK))
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ifa = ifa->ifa_next;
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/*
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* If we find an AF_LINK type entry we fill in the hardware address
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* If we find an AF_LINK type entry we fill in the hardware address.
|
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* This is useful for netstat(1) to keep track of which interface
|
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* is which.
|
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*/
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if ((ifa != 0) && (ifa->ifa_addr != 0)) {
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/*
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@ -742,6 +768,10 @@ ed_stop(unit)
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}
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}
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/*
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* Device timeout/watchdog routine. Entered if the device neglects to
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* generate an interrupt after a transmit has been started on it.
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*/
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int
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ed_watchdog(unit)
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int unit;
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@ -904,6 +934,9 @@ ed_init(unit)
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(void) splx(s);
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}
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/*
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* This routine actually starts the transmission on the interface
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*/
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static inline void ed_xmit(ifp)
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struct ifnet *ifp;
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{
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@ -928,13 +961,16 @@ static inline void ed_xmit(ifp)
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outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
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/*
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* Set page 0, Remote DMA complete, Transmit Packet, and Start
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* Set page 0, Remote DMA complete, Transmit Packet, and *Start*
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*/
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outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
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sc->xmit_busy = 1;
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sc->data_buffered = 0;
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/*
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* Switch buffers if we are doing double-buffered transmits
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*/
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if ((sc->txb_next == 0) && (sc->txb_cnt > 1))
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sc->txb_next = 1;
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else
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@ -966,14 +1002,24 @@ ed_start(ifp)
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u_char laar_tmp;
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outloop:
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/*
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* See if there is room to send more data (i.e. one or both of the
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* buffers is empty).
|
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*/
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if (sc->data_buffered)
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if (sc->xmit_busy) {
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/*
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* No room. Indicate this to the outside world
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* and exit.
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*/
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ifp->if_flags |= IFF_OACTIVE;
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return;
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} else {
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/*
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* Data is buffered, but we're not transmitting, so
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* start the xmit on the buffered data.
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* Note that ed_xmit() resets the data_buffered flag
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* before returning
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* before returning.
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*/
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ed_xmit(ifp);
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}
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@ -1104,6 +1150,10 @@ ed_start(ifp)
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m_freem(m0);
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/*
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* If we are doing double-buffering, a buffer might be free to
|
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* fill with another packet, so loop back to the top.
|
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*/
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if (sc->txb_cnt > 1)
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goto outloop;
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else {
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@ -1260,7 +1310,7 @@ edintr(unit)
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sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
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/*
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* reset watchdog timer
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* clear watchdog timer
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*/
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sc->arpcom.ac_if.if_timer = 0;
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}
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@ -1310,7 +1360,7 @@ edintr(unit)
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sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
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/*
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* reset watchdog timer
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* clear watchdog timer
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*/
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sc->arpcom.ac_if.if_timer = 0;
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@ -1698,9 +1748,15 @@ ed_ring_to_mbuf(sc,src,dst,total_len)
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if (amount == 0) { /* no more data in this mbuf, alloc another */
|
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/*
|
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* if there is enough data for an mbuf cluster, attempt
|
||||
* to allocate one of those, otherwise, a regular mbuf
|
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* will do.
|
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* If there is enough data for an mbuf cluster, attempt
|
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* to allocate one of those, otherwise, a regular
|
||||
* mbuf will do.
|
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* Note that a regular mbuf is always required, even if
|
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* we get a cluster - getting a cluster does not
|
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* allocate any mbufs, and one is needed to assign
|
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* the cluster to. The mbuf that has a cluster
|
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* extension can not be used to contain data - only
|
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* the cluster can contain data.
|
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*/
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dst = m;
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MGET(m, M_DONTWAIT, MT_DATA);
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@ -1,5 +1,14 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
|
||||
*
|
||||
* $Log: if_edreg.h,v $
|
||||
* Revision 1.2 93/06/23 03:03:05 davidg
|
||||
* added some additional definitions for the 83C584 bus interface
|
||||
* chip (SMC/WD boards)
|
||||
*
|
||||
* Revision 1.1 93/06/23 03:01:07 davidg
|
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* Initial revision
|
||||
*
|
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*/
|
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|
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/*
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@ -573,13 +582,23 @@ struct ed_ring {
|
||||
|
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#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
|
||||
#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
|
||||
#define ED_WD_ICR_IR2 0x04 /* select second set of IRQs */
|
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#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
|
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#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
|
||||
#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
|
||||
#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
|
||||
#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
|
||||
#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
|
||||
|
||||
/*
|
||||
* IO Address Register (IAR)
|
||||
*/
|
||||
#define ED_WD_IAR 2
|
||||
|
||||
/*
|
||||
* EEROM Address Register
|
||||
*/
|
||||
#define ED_WD_EAR 3
|
||||
|
||||
/*
|
||||
* Interrupt Request Register (IRR)
|
||||
*/
|
||||
@ -590,6 +609,22 @@ struct ed_ring {
|
||||
#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
|
||||
#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
|
||||
#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
|
||||
|
||||
/*
|
||||
* The three bit of the encoded IRQ are decoded as follows:
|
||||
*
|
||||
* IR2 IR1 IR0 IRQ
|
||||
* 0 0 0 2/9
|
||||
* 0 0 1 3
|
||||
* 0 1 0 5
|
||||
* 0 1 1 7
|
||||
* 1 0 0 10
|
||||
* 1 0 1 11
|
||||
* 1 1 0 15
|
||||
* 1 1 1 4
|
||||
*/
|
||||
#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
|
||||
#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
|
||||
#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user