Make it possible to safely use TPIDRURW from userspace.
On amd64, arm64 and i386, we have the possibility to switch between TLS areas in userspace. The nice thing about this is that it makes it easier to do light-weight threading, if we ever feel like doing that. On armv6, let's go into the same direction by making it possible to safely use the TPIDRURW register, which is intended for this purpose. Clean up the ARMv6 code to remove md_tp entirely. Simply add a dedicated field to the PCB to hold the value of TPIDRURW across context switches, like we do for any other register. As userspace currently uses the read-only TPIDRURO register, simply ensure that we keep both values in sync where possible. The system calls for modifying the read-only register will simply write the intended value into both registers, so that it lazily ends up in the PCB during the next context switch. Reviewed by: https://reviews.freebsd.org/D7951 Approved by: andrew Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D7951
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@ -81,6 +81,9 @@ ASSYM(PCB_R12, offsetof(struct pcb, pcb_regs.sf_r12));
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ASSYM(PCB_SP, offsetof(struct pcb, pcb_regs.sf_sp));
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ASSYM(PCB_LR, offsetof(struct pcb, pcb_regs.sf_lr));
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ASSYM(PCB_PC, offsetof(struct pcb, pcb_regs.sf_pc));
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#if __ARM_ARCH >= 6
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ASSYM(PCB_TPIDRURW, offsetof(struct pcb, pcb_regs.sf_tpidrurw));
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#endif
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ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
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ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
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@ -100,8 +103,8 @@ ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
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ASSYM(TD_PROC, offsetof(struct thread, td_proc));
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ASSYM(TD_MD, offsetof(struct thread, td_md));
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ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
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ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
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#if __ARM_ARCH < 6
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ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
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ASSYM(MD_RAS_START, offsetof(struct mdthread, md_ras_start));
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ASSYM(MD_RAS_END, offsetof(struct mdthread, md_ras_end));
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#endif
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@ -291,6 +291,8 @@ ENTRY(cpu_switch)
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ldr r3, [r0, #(TD_PCB)]
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add r3, #(PCB_R4)
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stmia r3, {r4-r12, sp, lr, pc}
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mrc CP15_TPIDRURW(r4)
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str r4, [r3, #(PCB_TPIDRURW - PCB_R4)]
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#ifdef INVARIANTS
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cmp r1, #0 /* new thread? */
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@ -437,9 +439,6 @@ sw1:
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cmp r3, r6
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beq 1b
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#endif
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/* Set the new tls */
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ldr r0, [r11, #(TD_MD + MD_TP)]
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mcr CP15_TPIDRURO(r0) /* write tls thread reg 2 */
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/* We have a new curthread now so make a note it */
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str r11, [r8, #PC_CURTHREAD]
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@ -452,7 +451,14 @@ sw1:
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* Restore all saved registers and return. Note that some saved
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* registers can be changed when either cpu_fork(), cpu_copy_thread(),
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* cpu_fork_kthread_handler(), or makectx() was called.
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*
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* The value of TPIDRURW is also written into TPIDRURO, as
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* userspace still uses TPIDRURO, modifying it through
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* sysarch(ARM_SET_TP, addr).
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*/
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ldr r3, [r7, #PCB_TPIDRURW]
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mcr CP15_TPIDRURW(r3) /* write tls thread reg 2 */
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mcr CP15_TPIDRURO(r3) /* write tls thread reg 3 */
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add r3, r7, #PCB_R4
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ldmia r3, {r4-r12, sp, pc}
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@ -166,10 +166,10 @@ static int
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arm32_set_tp(struct thread *td, void *args)
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{
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td->td_md.md_tp = (register_t)args;
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#if __ARM_ARCH >= 6
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set_tls(args);
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#else
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td->td_md.md_tp = (register_t)args;
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*(register_t *)ARM_TP_ADDRESS = (register_t)args;
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#endif
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return (0);
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@ -180,7 +180,7 @@ arm32_get_tp(struct thread *td, void *args)
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{
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#if __ARM_ARCH >= 6
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td->td_retval[0] = td->td_md.md_tp;
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td->td_retval[0] = (register_t)get_tls();
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#else
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td->td_retval[0] = *(register_t *)ARM_TP_ADDRESS;
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#endif
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@ -82,8 +82,8 @@ __FBSDID("$FreeBSD$");
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* struct switchframe and trapframe must both be a multiple of 8
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* for correct stack alignment.
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*/
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CTASSERT(sizeof(struct switchframe) == 48);
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CTASSERT(sizeof(struct trapframe) == 80);
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_Static_assert((sizeof(struct switchframe) % 8) == 0, "Bad alignment");
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_Static_assert((sizeof(struct trapframe) % 8) == 0, "Bad alignment");
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uint32_t initial_fpscr = VFPSCR_DN | VFPSCR_FZ;
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@ -134,6 +134,9 @@ cpu_fork(register struct thread *td1, register struct proc *p2,
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pcb2->pcb_regs.sf_r5 = (register_t)td2;
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pcb2->pcb_regs.sf_lr = (register_t)fork_trampoline;
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pcb2->pcb_regs.sf_sp = STACKALIGN(td2->td_frame);
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#if __ARM_ARCH >= 6
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pcb2->pcb_regs.sf_tpidrurw = (register_t)get_tls();
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#endif
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pcb2->pcb_vfpcpu = -1;
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pcb2->pcb_vfpstate.fpscr = initial_fpscr;
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@ -147,9 +150,7 @@ cpu_fork(register struct thread *td1, register struct proc *p2,
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/* Setup to release spin count in fork_exit(). */
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td2->td_md.md_spinlock_count = 1;
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td2->td_md.md_saved_cspr = PSR_SVC32_MODE;
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#if __ARM_ARCH >= 6
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td2->td_md.md_tp = td1->td_md.md_tp;
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#else
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#if __ARM_ARCH < 6
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td2->td_md.md_tp = *(register_t *)ARM_TP_ADDRESS;
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#endif
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}
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@ -272,16 +273,18 @@ int
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cpu_set_user_tls(struct thread *td, void *tls_base)
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{
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#if __ARM_ARCH >= 6
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td->td_pcb->pcb_regs.sf_tpidrurw = (register_t)tls_base;
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if (td == curthread)
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set_tls(tls_base);
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#else
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td->td_md.md_tp = (register_t)tls_base;
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if (td == curthread) {
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critical_enter();
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#if __ARM_ARCH >= 6
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set_tls(tls_base);
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#else
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*(register_t *)ARM_TP_ADDRESS = (register_t)tls_base;
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#endif
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critical_exit();
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}
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#endif
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return (0);
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}
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@ -117,6 +117,10 @@ struct switchframe
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register_t sf_sp;
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register_t sf_lr;
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register_t sf_pc;
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#if __ARM_ARCH >= 6
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register_t sf_tpidrurw;
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register_t sf_spare0;
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#endif
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};
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@ -103,7 +103,8 @@ get_tls(void)
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{
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void *tls;
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__asm __volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tls));
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/* TPIDRURW contains the authoritative value. */
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__asm __volatile("mrc p15, 0, %0, c13, c0, 2" : "=r" (tls));
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return (tls);
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}
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@ -111,7 +112,15 @@ static inline void
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set_tls(void *tls)
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{
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__asm __volatile("mcr p15, 0, %0, c13, c0, 3" : : "r" (tls));
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/*
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* Update both TPIDRURW and TPIDRURO. TPIDRURW needs to be written
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* first to ensure that a context switch between the two writes will
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* still give the desired result of updating both.
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*/
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__asm __volatile(
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"mcr p15, 0, %0, c13, c0, 2\n"
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"mcr p15, 0, %0, c13, c0, 3\n"
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: : "r" (tls));
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}
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#define curthread get_curthread()
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@ -53,8 +53,8 @@ struct mdthread {
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int md_ptrace_addr;
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int md_ptrace_instr_alt;
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int md_ptrace_addr_alt;
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register_t md_tp;
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#if __ARM_ARCH < 6
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register_t md_tp;
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void *md_ras_start;
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void *md_ras_end;
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#endif
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