From c8d7ed0d0537b7789105092b1d1266fc4332b45b Mon Sep 17 00:00:00 2001
From: John Baldwin <jhb@FreeBSD.org>
Date: Tue, 6 Jan 2004 19:07:08 +0000
Subject: [PATCH] - Use i8259A register defines from shared sys/dev/ic/i8259.h
 rather than   from the i386-specific icu.h. - Replace PC98 magic numbers with
 equivalent register define values along   with comments about PC-98 "quirks".

---
 sys/i386/isa/atpic.c | 31 +++++++++++++++---------
 sys/i386/isa/icu.h   | 56 --------------------------------------------
 2 files changed, 20 insertions(+), 67 deletions(-)

diff --git a/sys/i386/isa/atpic.c b/sys/i386/isa/atpic.c
index 7252cbf87a10..634128610557 100644
--- a/sys/i386/isa/atpic.c
+++ b/sys/i386/isa/atpic.c
@@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/resource.h>
 #include <machine/segments.h>
 
+#include <dev/ic/i8259.h>
 #include <i386/isa/icu.h>
 #ifdef PC98
 #include <pc98/pc98/pc98.h>
@@ -63,26 +64,34 @@ __FBSDID("$FreeBSD$");
 #define	MASTER	0
 #define	SLAVE	1
 
-/* XXX: Magic numbers */
+/*
+ * Determine the base master and slave modes not including auto EOI support.
+ * All machines that FreeBSD supports use 8086 mode.
+ */
 #ifdef PC98
-#ifdef AUTO_EOI_1
-#define	MASTER_MODE	0x1f	/* Master auto EOI, 8086 mode */
+/*
+ * PC-98 machines do not support auto EOI on the second PIC.  Also, it
+ * seems that PC-98 machine PICs use buffered mode, and the master PIC
+ * uses special fully nested mode.
+ */
+#define	BASE_MASTER_MODE	(ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
+#define	BASE_SLAVE_MODE		(ICW4_BUF | ICW4_8086)
 #else
-#define	MASTER_MODE	0x1d	/* Master 8086 mode */
+#define	BASE_MASTER_MODE	ICW4_8086
+#define	BASE_SLAVE_MODE		ICW4_8086
 #endif
-#define	SLAVE_MODE	9	/* 8086 mode */
-#else /* IBM-PC */
+
+/* Enable automatic EOI if requested. */
 #ifdef AUTO_EOI_1
-#define	MASTER_MODE	(ICW4_8086 | ICW4_AEOI)
+#define	MASTER_MODE		(BASE_MASTER_MODE | ICW4_AEOI)
 #else
-#define	MASTER_MODE	ICW4_8086
+#define	MASTER_MODE		BASE_MASTER_MODE
 #endif
 #ifdef AUTO_EOI_2
-#define	SLAVE_MODE	(ICW4_8086 | ICW4_AEOI)
+#define	SLAVE_MODE		(BASE_SLAVE_MODE | ICW4_AEOI)
 #else
-#define	SLAVE_MODE	ICW4_8086
+#define	SLAVE_MODE		BASE_SLAVE_MODE
 #endif
-#endif /* PC98 */
 
 static void	atpic_init(void *dummy);
 
diff --git a/sys/i386/isa/icu.h b/sys/i386/isa/icu.h
index 9102690d9344..e6ba7d279721 100644
--- a/sys/i386/isa/icu.h
+++ b/sys/i386/isa/icu.h
@@ -86,62 +86,6 @@
 #define	IRQ7		0x0080		/* lowest - parallel printer */
 #endif
 
-/* Initialization control word 1. Written to even address. */
-#define	ICW1_IC4	0x01		/* ICW4 present */
-#define	ICW1_SNGL	0x02		/* 1 = single, 0 = cascaded */
-#define	ICW1_ADI	0x04		/* 1 = 4, 0 = 8 byte vectors */
-#define	ICW1_LTIM	0x08		/* 1 = level trigger, 0 = edge */
-#define	ICW1_RESET	0x10		/* must be 1 */
-/* 0x20 - 0x80 - in 8080/8085 mode only */
-
-/* Initialization control word 2. Written to the odd address. */
-/* No definitions, it is the base vector of the IDT for 8086 mode */
-
-/* Initialization control word 3. Written to the odd address. */
-/* For a master PIC, bitfield indicating a slave 8259 on given input */
-/* For slave, lower 3 bits are the slave's ID binary id on master */
-
-#ifdef PC98
-/* XXX: missing pc98 bits */
-#else
-
-/* Initialization control word 4. Written to the odd address. */
-#define	ICW4_8086	0x01		/* 1 = 8086, 0 = 8080 */
-#define	ICW4_AEOI	0x02		/* 1 = Auto EOI */
-#define	ICW4_MS		0x04		/* 1 = buffered master, 0 = slave */
-#define	ICW4_BUF	0x08		/* 1 = enable buffer mode */
-#define	ICW4_SFNM	0x10		/* 1 = special fully nested mode */
-
-#endif
-
-/* Operation control words.  Written after initialization. */
-
-/* Operation control word type 1 */
-/*
- * No definitions.  Written to the odd address.  Bitmask for interrupts.
- * 1 = disabled.
- */
-
-/* Operation control word type 2.  Bit 3 (0x08) must be zero. Even address. */
-#define	OCW2_L0		0x01		/* Level */
-#define	OCW2_L1		0x02
-#define	OCW2_L2		0x04
-/* 0x08 must be 0 to select OCW2 vs OCW3 */
-/* 0x10 must be 0 to select OCW2 vs ICW1 */
-#define	OCW2_EOI	0x20		/* 1 = EOI */
-#define	OCW2_SL		0x40		/* EOI mode */
-#define	OCW2_R		0x80		/* EOI mode */
-
-/* Operation control word type 3.  Bit 3 (0x08) must be set. Even address. */
-#define	OCW3_RIS	0x01		/* 1 = read IS, 0 = read IR */
-#define	OCW3_RR		0x02		/* register read */
-#define	OCW3_P		0x04		/* poll mode command */
-/* 0x08 must be 1 to select OCW3 vs OCW2 */
-#define	OCW3_SEL	0x08		/* must be 1 */
-/* 0x10 must be 0 to select OCW3 vs ICW1 */
-#define	OCW3_SMM	0x20		/* special mode mask */
-#define	OCW3_ESMM	0x40		/* enable SMM */
-
 /*
  * Interrupt Control offset into Interrupt descriptor table (IDT)
  */