Fix interrupt assignment for non-builtin PCI devices on e450s.
This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin. To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin). Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround. Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
This commit is contained in:
Thomas Moestl
parent
b77c32a07e
commit
c944338750
@ -112,7 +112,7 @@ static struct resource *ebus_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static struct resource_list *ebus_get_resource_list(device_t, device_t);
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static struct ebus_devinfo *ebus_setup_dinfo(struct ebus_softc *,
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static struct ebus_devinfo *ebus_setup_dinfo(device_t, struct ebus_softc *,
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phandle_t, char *);
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static void ebus_destroy_dinfo(struct ebus_devinfo *);
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static int ebus_print_res(struct ebus_devinfo *);
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@ -200,7 +200,7 @@ ebus_probe(device_t dev)
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if ((OF_getprop_alloc(node, "name", 1, (void **)&cname)) == -1)
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continue;
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if ((edi = ebus_setup_dinfo(sc, node, cname)) == NULL) {
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if ((edi = ebus_setup_dinfo(dev, sc, node, cname)) == NULL) {
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device_printf(dev, "<%s>: incomplete\n", cname);
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free(cname, M_OFWPROP);
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continue;
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@ -363,7 +363,8 @@ ebus_get_resource_list(device_t dev, device_t child)
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}
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static struct ebus_devinfo *
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ebus_setup_dinfo(struct ebus_softc *sc, phandle_t node, char *name)
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ebus_setup_dinfo(device_t dev, struct ebus_softc *sc, phandle_t node,
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char *name)
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{
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struct ebus_devinfo *edi;
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struct isa_regs *reg;
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@ -398,7 +399,8 @@ ebus_setup_dinfo(struct ebus_softc *sc, phandle_t node, char *name)
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nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs),
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(void **)&intrs);
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for (i = 0; i < nintr; i++) {
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intr = ofw_bus_route_intr(node, intrs[i], ofw_pci_orb_callback);
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intr = ofw_bus_route_intr(node, intrs[i], ofw_pci_orb_callback,
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dev);
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if (intr == ORIR_NOTFOUND) {
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panic("ebus_setup_dinfo: could not map ebus "
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"interrupt %d", intrs[i]);
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@ -32,8 +32,8 @@
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#define ORIR_NOTFOUND 0xffffffff
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typedef int obr_callback_t(phandle_t, u_int8_t *, int, u_int8_t *, int,
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u_int8_t **, int *);
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u_int8_t **, int *, void *);
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u_int32_t ofw_bus_route_intr(phandle_t, int, obr_callback_t *);
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u_int32_t ofw_bus_route_intr(phandle_t, int, obr_callback_t *, void *);
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#endif /* !_MACHINE_OFW_BUS_H_ */
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@ -134,7 +134,7 @@ isa_init(device_t dev)
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if (ino > 7)
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panic("isa_init: XXX: ino too large");
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isa_ino[ino] = ofw_bus_route_intr(node, ino,
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ofw_pci_orb_callback);
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ofw_pci_orb_callback, dev);
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}
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for (nbr -= 1; nbr >= 0; nbr--) {
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@ -46,44 +46,90 @@
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#include <sparc64/pci/ofw_pci.h>
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#include <machine/bus.h>
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#include <machine/cache.h>
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#include <machine/iommureg.h>
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#include <machine/ofw_bus.h>
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#include <machine/ver.h>
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#include "pcib_if.h"
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#include "sparcbus_if.h"
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u_int8_t pci_bus_cnt;
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phandle_t *pci_bus_map;
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int pci_bus_map_sz;
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#define OPQ_NO_SWIZZLE 1
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/* Do not swizzle on a PCI bus node with no interrupt-map propery. */
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#define OPQ_NO_SWIZZLE 1
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/*
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* INOs < 255 are really intpin numbers; use a driver method to figure out
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* the real INO.
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*/
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#define OPQ_INO_CALLBACK 2
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/*
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* Do not map EBus interrupts at PCI buses, but assume that they are fully
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* specified already.
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*/
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#define OPQ_EBUS_NOMAP 4
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static struct ofw_pci_quirk {
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char *opq_model;
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int opq_quirks;
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} ofw_pci_quirks[] = {
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{ "SUNW,Ultra-4", OPQ_NO_SWIZZLE },
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{ "SUNW,Ultra-1-Engine", OPQ_NO_SWIZZLE },
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{ "SUNW,Ultra-4", OPQ_INO_CALLBACK | OPQ_EBUS_NOMAP },
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{ "SUNW,Ultra-1-Engine", OPQ_NO_SWIZZLE },
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};
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#define OPQ_NENT (sizeof(ofw_pci_quirks) / sizeof(ofw_pci_quirks[0]))
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static int pci_quirks;
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#define OFW_PCI_PCIBUS "pci"
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#define OFW_PCI_EBUS "ebus"
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#define PCI_BUS_MAP_INC 10
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int
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ofw_pci_orb_callback(phandle_t node, u_int8_t *pintptr, int pintsz,
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u_int8_t *pregptr, int pregsz, u_int8_t **rintr, int *terminate)
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u_int8_t *pregptr, int pregsz, u_int8_t **rintr, int *terminate,
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void *cookie)
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{
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device_t dev = cookie;
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struct ofw_pci_register preg;
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u_int32_t pintr, intr;
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u_int slot;
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char type[32];
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int found = 0;
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if (pintsz != sizeof(u_int32_t))
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if ((pci_quirks & OPQ_EBUS_NOMAP) != 0 &&
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OF_getprop(node, "name", type, sizeof(type)) != -1 &&
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strcmp(type, OFW_PCI_EBUS) == 0) {
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*terminate = 1;
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return (-1);
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}
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if (pintsz != sizeof(u_int32_t) || pregsz < sizeof(preg))
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return (-1);
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bcopy(pintptr, &pintr, sizeof(pintr));
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if ((pci_quirks & OPQ_NO_SWIZZLE) == 0 && pregsz >= sizeof(preg) &&
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bcopy(pregptr, &preg, sizeof(preg));
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slot = OFW_PCI_PHYS_HI_DEVICE(preg.phys_hi);
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if ((pci_quirks & OPQ_INO_CALLBACK) != 0 && pintr <= 255) {
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/*
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* The e450 has no interrupt maps at all, and it usually has
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* full interrupt numbers, including IGN, in the interrupt
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* properties. There is one exception, however: the property
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* values for external PCI devices seem to always be below 255
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* and describe the interrupt pin to be used on the slot, while
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* we have to figure out the base INO by looking at the slot
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* number (which we do using a sparcbus method).
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*
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* Of course, there is an exception to that nice rule:
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* in the ebus case, the interrupt property has the correct
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* INO (but without IGN). This is dealt with above.
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*/
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intr = SPARCBUS_GUESS_INO(dev, node, slot, pintr);
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found = intr != 255;
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*terminate = found;
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}
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if (!found && (pci_quirks & OPQ_NO_SWIZZLE) == 0 &&
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OF_getprop(node, "device_type", type, sizeof(type)) != -1 &&
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strcmp(type, OFW_PCI_PCIBUS) == 0 && pintr >= 1 && pintr <= 4) {
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/*
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@ -91,29 +137,31 @@ ofw_pci_orb_callback(phandle_t node, u_int8_t *pintptr, int pintsz,
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* PCI bridges without interrupt maps, where we apparently must
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* do the PCI swizzle and continue to map on at the parent.
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*/
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bcopy(pregptr, &preg, sizeof(preg));
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intr = (OFW_PCI_PHYS_HI_DEVICE(preg.phys_hi) + pintr + 3) %
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4 + 1;
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intr = (slot + pintr + 3) % 4 + 1;
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*terminate = 0;
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found = 1;
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}
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if (found) {
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*rintr = malloc(sizeof(intr), M_OFWPROP, M_WAITOK);
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bcopy(&intr, *rintr, sizeof(intr));
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*terminate = 0;
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return (sizeof(intr));
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}
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return (-1);
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} else
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return (-1);
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}
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u_int32_t
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ofw_pci_route_intr(phandle_t node, u_int32_t ign)
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static u_int32_t
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ofw_pci_route_intr(device_t dev, phandle_t node, u_int32_t ign)
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{
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u_int32_t rv;
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rv = ofw_bus_route_intr(node, ORIP_NOINT, ofw_pci_orb_callback);
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rv = ofw_bus_route_intr(node, ORIP_NOINT, ofw_pci_orb_callback, dev);
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if (rv == ORIR_NOTFOUND)
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return (255);
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/*
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* Some machines (notably the SPARCengine Ultra AX) have no mappings
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* at all, but use complete interrupt vector number including the IGN.
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* Catch this case and remove the IGN.
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* Some machines (notably the SPARCengine Ultra AX and the e450) have
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* no mappings at all, but use complete interrupt vector number
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* including the IGN. Catch this case and remove the IGN.
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*/
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if (rv > ign)
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rv -= ign;
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@ -273,7 +321,7 @@ ofw_pci_init(device_t dev, phandle_t bushdl, u_int32_t ign,
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}
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/* Initialize the intline registers. */
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if ((intr = ofw_pci_route_intr(node, ign)) != 255) {
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if ((intr = ofw_pci_route_intr(dev, node, ign)) != 255) {
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#ifdef OFW_PCI_DEBUG
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device_printf(dev, "%s: mapping intr for "
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"%d/%d/%d to %d (preset was %d)\n",
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@ -71,7 +71,6 @@ struct ofw_pci_bdesc {
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struct ofw_pci_bdesc *obd_super;
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};
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u_int32_t ofw_pci_route_intr(phandle_t, u_int32_t);
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obr_callback_t ofw_pci_orb_callback;
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u_int8_t ofw_pci_alloc_busno(phandle_t);
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ofw_pci_binit_t ofw_pci_binit;
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@ -26,6 +26,8 @@
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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INTERFACE sparcbus;
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HEADER {
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@ -37,10 +39,6 @@ HEADER {
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};
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CODE {
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static int sparcbus_default_intr_pending(device_t, int);
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static bus_space_handle_t sparcbus_default_get_bus_handle(device_t,
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enum sbbt_id, bus_space_handle_t childhdl, bus_space_tag_t *tag);
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static int
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sparcbus_default_intr_pending(device_t dev, int intr)
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{
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@ -48,6 +46,15 @@ CODE {
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return (SPARCBUS_INTR_PENDING(device_get_parent(dev), intr));
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}
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static u_int32_t
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sparcbus_default_guess_ino(device_t dev, phandle_t node, u_int slot,
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u_int pin)
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{
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return (SPARCBUS_GUESS_INO(device_get_parent(dev), node, slot,
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pin));
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}
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static bus_space_handle_t
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sparcbus_default_get_bus_handle(device_t dev, enum sbbt_id id,
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bus_space_handle_t childhdl, bus_space_tag_t *tag)
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@ -64,6 +71,17 @@ METHOD int intr_pending {
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int intr;
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} DEFAULT sparcbus_default_intr_pending;
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# Let the bus driver guess the INO of the device at the given slot and intpin
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# on the bus described by the node if it could not be determined from the
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# firmware properties. Returns 255 if no INO could be found (mapping will
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# continue at the parent), or the desired INO.
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METHOD u_int32_t guess_ino {
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device_t dev;
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phandle_t node;
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u_int slot;
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u_int pin;
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} DEFAULT sparcbus_default_guess_ino;
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# Get the bustag for the root bus. This is needed for ISA old-stlye
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# in[bwl]()/out[bwl]() support, where no tag retrieved from a resource is
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# passed. The returned tag is used to construct a tag for the whole ISA bus.
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@ -141,6 +141,7 @@ static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t,
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int);
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static int psycho_route_interrupt(device_t, device_t, int);
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static int psycho_intr_pending(device_t, int);
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static u_int32_t psycho_guess_ino(device_t, phandle_t, u_int, u_int);
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static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id,
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bus_space_handle_t childhdl, bus_space_tag_t *tag);
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@ -167,6 +168,7 @@ static device_method_t psycho_methods[] = {
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/* sparcbus interface */
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DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending),
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DEVMETHOD(sparcbus_guess_ino, psycho_guess_ino),
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DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle),
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{ 0, 0 }
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@ -336,7 +338,6 @@ psycho_attach(device_t dev)
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struct upa_regs *reg;
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struct ofw_pci_bdesc obd;
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struct psycho_desc *desc;
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vm_paddr_t pcictl_offs;
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phandle_t node;
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u_int64_t csr;
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u_long mlen;
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@ -374,13 +375,25 @@ psycho_attach(device_t dev)
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panic("psycho_attach: %d not enough registers", nreg);
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sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]);
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mlen = UPA_REG_SIZE(®[2]);
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pcictl_offs = UPA_REG_PHYS(®[0]);
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sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr;
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switch (sc->sc_pcictl) {
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case PSR_PCICTL0:
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sc->sc_half = 0;
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break;
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case PSR_PCICTL1:
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sc->sc_half = 1;
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break;
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default:
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panic("psycho_attach: bogus pci control register "
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"location");
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}
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} else {
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if (nreg <= 0)
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panic("psycho_attach: %d not enough registers", nreg);
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sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]);
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mlen = UPA_REG_SIZE(reg);
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pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0;
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sc->sc_pcictl = PSR_PCICTL0;
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sc->sc_half = 0;
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}
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/*
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@ -415,17 +428,14 @@ psycho_attach(device_t dev)
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sc->sc_bustag = osc->sc_bustag;
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sc->sc_bushandle = osc->sc_bushandle;
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}
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if (pcictl_offs < sc->sc_basepaddr)
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panic("psycho_attach: bogus pci control register location");
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sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr;
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csr = PSYCHO_READ8(sc, PSR_CS);
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sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
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sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6;
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device_printf(dev, "%s, impl %d, version %d, ign %#x\n",
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device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n",
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desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr),
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(int)PSYCHO_GCSR_VERS(csr), sc->sc_ign);
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(int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half);
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/*
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* Setup the PCI control register
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@ -1272,6 +1282,31 @@ psycho_intr_pending(device_t dev, int intr)
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return (diag != 0);
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}
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static u_int32_t
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psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin)
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{
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struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev);
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bus_addr_t intrmap;
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/*
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* If this is not for one of our direct children (i.e. we are mapping
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* at our node), tell the interrupt mapper to go on - we need the
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* slot number of the device or it's topmost parent bridge to guess
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* the INO.
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*/
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if (node != sc->sc_node)
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return (255);
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/*
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* Actually guess the INO. We always assume that this is a non-OBIO
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* device, and use from the slot number to determine it.
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* We only need to do this on e450s, it seems; here, the slot numbers
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* for bus A are one-based, while those for bus B seemingly have an
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* offset of 2 (hence the factor of 3 below).
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*/
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intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half);
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return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1);
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}
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static bus_space_handle_t
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psycho_get_bus_handle(device_t dev, enum sbbt_id id,
|
||||
bus_space_handle_t childhdl, bus_space_tag_t *tag)
|
||||
|
||||
@ -61,6 +61,9 @@ struct psycho_softc {
|
||||
#define PSYCHO_MODE_SABRE 1
|
||||
#define PSYCHO_MODE_PSYCHO 2
|
||||
|
||||
/* Bus A or B of a psycho pair? */
|
||||
int sc_half;
|
||||
|
||||
struct iommu_state *sc_is;
|
||||
u_int32_t sc_dvmabase;
|
||||
|
||||
|
||||
@ -160,7 +160,7 @@ ofw_bus_find_intr(u_int8_t *intr, int intrsz, u_int8_t *regs, int physsz,
|
||||
* This should work for all bus systems.
|
||||
*/
|
||||
u_int32_t
|
||||
ofw_bus_route_intr(phandle_t node, int intrp, obr_callback_t *cb)
|
||||
ofw_bus_route_intr(phandle_t node, int intrp, obr_callback_t *cb, void *cookie)
|
||||
{
|
||||
u_int8_t *reg, *intr, *tintr, *imap, *imapmsk;
|
||||
phandle_t parent;
|
||||
@ -201,7 +201,7 @@ ofw_bus_route_intr(phandle_t node, int intrp, obr_callback_t *cb)
|
||||
*/
|
||||
if (cb != NULL) {
|
||||
tisz = cb(parent, intr, isz, reg, regsz, &tintr,
|
||||
&found);
|
||||
&found, cookie);
|
||||
if (tisz != -1) {
|
||||
isz = tisz;
|
||||
free(intr, M_OFWPROP);
|
||||
|
||||
@ -26,6 +26,8 @@
|
||||
#include <sys/bus.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
INTERFACE sparcbus;
|
||||
|
||||
HEADER {
|
||||
@ -37,10 +39,6 @@ HEADER {
|
||||
};
|
||||
|
||||
CODE {
|
||||
static int sparcbus_default_intr_pending(device_t, int);
|
||||
static bus_space_handle_t sparcbus_default_get_bus_handle(device_t,
|
||||
enum sbbt_id, bus_space_handle_t childhdl, bus_space_tag_t *tag);
|
||||
|
||||
static int
|
||||
sparcbus_default_intr_pending(device_t dev, int intr)
|
||||
{
|
||||
@ -48,6 +46,15 @@ CODE {
|
||||
return (SPARCBUS_INTR_PENDING(device_get_parent(dev), intr));
|
||||
}
|
||||
|
||||
static u_int32_t
|
||||
sparcbus_default_guess_ino(device_t dev, phandle_t node, u_int slot,
|
||||
u_int pin)
|
||||
{
|
||||
|
||||
return (SPARCBUS_GUESS_INO(device_get_parent(dev), node, slot,
|
||||
pin));
|
||||
}
|
||||
|
||||
static bus_space_handle_t
|
||||
sparcbus_default_get_bus_handle(device_t dev, enum sbbt_id id,
|
||||
bus_space_handle_t childhdl, bus_space_tag_t *tag)
|
||||
@ -64,6 +71,17 @@ METHOD int intr_pending {
|
||||
int intr;
|
||||
} DEFAULT sparcbus_default_intr_pending;
|
||||
|
||||
# Let the bus driver guess the INO of the device at the given slot and intpin
|
||||
# on the bus described by the node if it could not be determined from the
|
||||
# firmware properties. Returns 255 if no INO could be found (mapping will
|
||||
# continue at the parent), or the desired INO.
|
||||
METHOD u_int32_t guess_ino {
|
||||
device_t dev;
|
||||
phandle_t node;
|
||||
u_int slot;
|
||||
u_int pin;
|
||||
} DEFAULT sparcbus_default_guess_ino;
|
||||
|
||||
# Get the bustag for the root bus. This is needed for ISA old-stlye
|
||||
# in[bwl]()/out[bwl]() support, where no tag retrieved from a resource is
|
||||
# passed. The returned tag is used to construct a tag for the whole ISA bus.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user