Merge new vendor release - 6.2.9.
Details:
o if_em.c changes:
- Added several new PCI ids.
- Check em_check_phy_reset_block() before doing SIOCSIFMEDIA ioctl.
- Don't touch TARC registers, they are now handled in shared
code in if_em_hw.c.
- Move RDH and RDT setting to the end of
em_initialize_receive_unit().
- Declare em_read_pcie_cap_reg(), now empty.
o if_em_hw.c dropped in from vendor, then restored rev. 1.15.
o if_em_hw.h dropped in from vendor, then modified:
- Added RX overrun interrupt flag to interrupt enable mask.
- Remove declarations of em_io_read(), em_io_write().
Approved by: jfv
This commit is contained in:
glebius
parent
969c298091
commit
c9b3a7eee6
@ -88,7 +88,7 @@ int em_display_debug_stats = 0;
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* Driver version
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*********************************************************************/
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char em_driver_version[] = "Version - 6.1.4 - TSO";
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char em_driver_version[] = "Version - 6.2.9";
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/*********************************************************************
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@ -154,6 +154,8 @@ static em_vendor_info_t em_vendor_info_array[] =
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{ 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
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PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE,
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PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
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@ -171,9 +173,13 @@ static em_vendor_info_t em_vendor_info_array[] =
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PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
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PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0},
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/* required last entry */
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{ 0, 0, 0, 0, 0}
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@ -877,6 +883,15 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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}
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break;
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case SIOCSIFMEDIA:
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/* Check SOL/IDER usage */
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EM_LOCK(adapter);
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if (em_check_phy_reset_block(&adapter->hw)) {
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EM_UNLOCK(adapter);
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device_printf(adapter->dev, "Media change is"
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"blocked due to SOL/IDER session.\n");
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break;
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}
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EM_UNLOCK(adapter);
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case SIOCGIFMEDIA:
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IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
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error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
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@ -2119,13 +2134,13 @@ em_allocate_pci_resources(struct adapter *adapter)
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/* Figure our where our IO BAR is ? */
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for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
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val = pci_read_config(dev, rid, 4);
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if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) {
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if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
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adapter->io_rid = rid;
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break;
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}
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rid += 4;
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/* check for 64bit BAR */
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if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT)
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if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
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rid += 4;
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}
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if (rid >= PCIR_CIS) {
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@ -2318,7 +2333,7 @@ em_hardware_init(struct adapter *adapter)
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else
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adapter->hw.fc_pause_time = 0x1000;
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adapter->hw.fc_send_xon = TRUE;
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adapter->hw.fc = em_fc_full;
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adapter->hw.fc = E1000_FC_FULL;
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if (em_init_hw(&adapter->hw) < 0) {
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device_printf(dev, "Hardware Initialization Failed");
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@ -2663,7 +2678,7 @@ fail:
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static void
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em_initialize_transmit_unit(struct adapter *adapter)
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{
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uint32_t reg_tctl, reg_tarc;
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uint32_t reg_tctl;
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uint32_t reg_tipg = 0;
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uint64_t bus_addr;
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@ -2711,24 +2726,6 @@ em_initialize_transmit_unit(struct adapter *adapter)
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if(adapter->hw.mac_type >= em_82540)
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E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay.value);
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/* Do adapter specific tweaks before we enable the transmitter. */
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if (adapter->hw.mac_type == em_82571 || adapter->hw.mac_type == em_82572) {
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reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
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reg_tarc |= (1 << 25);
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E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
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reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
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reg_tarc |= (1 << 25);
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reg_tarc &= ~(1 << 28);
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E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
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} else if (adapter->hw.mac_type == em_80003es2lan) {
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reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
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reg_tarc |= 1;
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E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
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reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
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reg_tarc |= 1;
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E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
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}
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/* Program the Transmit Control Register */
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reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
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(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
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@ -3352,10 +3349,6 @@ em_initialize_receive_unit(struct adapter *adapter)
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E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
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E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
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/* Setup the HW Rx Head and Tail Descriptor Pointers */
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E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
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E1000_WRITE_REG(&adapter->hw, RDH, 0);
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/* Setup the Receive Control Register */
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reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
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E1000_RCTL_RDMTS_HALF |
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@ -3394,6 +3387,10 @@ em_initialize_receive_unit(struct adapter *adapter)
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/* Enable Receives */
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E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
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/* Setup the HW Rx Head and Tail Descriptor Pointers */
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E1000_WRITE_REG(&adapter->hw, RDH, 0);
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E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
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}
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/*********************************************************************
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@ -3809,6 +3806,16 @@ em_pci_clear_mwi(struct em_hw *hw)
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(hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
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}
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/*
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* We may eventually really do this, but its unnecessary
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* for now so we just return unsupported.
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*/
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int32_t
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em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
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{
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return (0);
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}
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/*********************************************************************
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* 82544 Coexistence issue workaround.
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* There are 2 issues.
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@ -86,7 +86,8 @@ POSSIBILITY OF SUCH DAMAGE.
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#define EM_TIDV 64
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/*
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* EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
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* EM_TADV - Transmit Absolute Interrupt Delay Value
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* (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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@ -112,10 +113,10 @@ POSSIBILITY OF SUCH DAMAGE.
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*
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* CAUTION: When setting EM_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system event log.
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* In addition, the controller is automatically reset, restoring the
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* network connection. To eliminate the potential for the hang
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* ensure that EM_RDTR is set to 0.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that EM_RDTR is set to 0.
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*/
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#define EM_RDTR 0
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@ -207,6 +208,16 @@ POSSIBILITY OF SUCH DAMAGE.
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#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
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/* PCI Config defines */
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#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
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#define EM_BAR_TYPE_MASK 0x00000001
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#define EM_BAR_TYPE_MMEM 0x00000000
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#define EM_BAR_TYPE_IO 0x00000001
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#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
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#define EM_BAR_MEM_TYPE_MASK 0x00000006
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#define EM_BAR_MEM_TYPE_32BIT 0x00000000
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#define EM_BAR_MEM_TYPE_64BIT 0x00000004
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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@ -394,14 +405,14 @@ struct em_buffer {
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/* For 82544 PCIX Workaround */
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typedef struct _ADDRESS_LENGTH_PAIR
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{
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u_int64_t address;
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u_int32_t length;
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uint64_t address;
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uint32_t length;
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} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
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typedef struct _DESCRIPTOR_PAIR
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{
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ADDRESS_LENGTH_PAIR descriptor[4];
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u_int32_t elements;
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uint32_t elements;
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} DESC_ARRAY, *PDESC_ARRAY;
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#define EM_LOCK_INIT(_sc, _name) \
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File diff suppressed because it is too large
Load Diff
@ -1,32 +1,34 @@
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/*******************************************************************************
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Copyright (c) 2001-2005, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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Copyright (c) 2001-2005, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/* $FreeBSD$ */
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@ -98,15 +100,6 @@ typedef enum {
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em_100_full = 3
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} em_speed_duplex_type;
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/* Flow Control Settings */
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typedef enum {
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em_fc_none = 0,
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em_fc_rx_pause = 1,
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em_fc_tx_pause = 2,
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em_fc_full = 3,
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em_fc_default = 0xFF
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} em_fc_type;
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struct em_shadow_ram {
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uint16_t eeprom_word;
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boolean_t modified;
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@ -136,11 +129,13 @@ typedef enum {
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/* PCI bus widths */
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typedef enum {
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em_bus_width_unknown = 0,
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/* These PCIe values should literally match the possible return values
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* from config space */
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em_bus_width_pciex_1 = 1,
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em_bus_width_pciex_2 = 2,
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em_bus_width_pciex_4 = 4,
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em_bus_width_32,
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em_bus_width_64,
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em_bus_width_pciex_1,
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em_bus_width_pciex_2,
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em_bus_width_pciex_4,
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em_bus_width_reserved
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} em_bus_width;
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@ -309,11 +304,13 @@ typedef enum {
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#define E1000_BLK_PHY_RESET 12
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#define E1000_ERR_SWFW_SYNC 13
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#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
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(((_value) & 0xff00) >> 8))
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/* Function prototypes */
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/* Initialization */
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int32_t em_reset_hw(struct em_hw *hw);
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int32_t em_init_hw(struct em_hw *hw);
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int32_t em_id_led_init(struct em_hw * hw);
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int32_t em_set_mac_type(struct em_hw *hw);
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void em_set_media_type(struct em_hw *hw);
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@ -321,39 +318,23 @@ void em_set_media_type(struct em_hw *hw);
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int32_t em_setup_link(struct em_hw *hw);
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int32_t em_phy_setup_autoneg(struct em_hw *hw);
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void em_config_collision_dist(struct em_hw *hw);
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int32_t em_config_fc_after_link_up(struct em_hw *hw);
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int32_t em_check_for_link(struct em_hw *hw);
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int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
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int32_t em_wait_autoneg(struct em_hw *hw);
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int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex);
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int32_t em_force_mac_fc(struct em_hw *hw);
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/* PHY */
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int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
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int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
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int32_t em_phy_hw_reset(struct em_hw *hw);
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int32_t em_phy_reset(struct em_hw *hw);
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void em_phy_powerdown_workaround(struct em_hw *hw);
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int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
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int32_t em_duplex_reversal(struct em_hw *hw);
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int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
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int32_t em_init_lcd_from_nvm(struct em_hw *hw);
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int32_t em_detect_gig_phy(struct em_hw *hw);
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int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
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int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
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int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
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int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
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int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity);
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int32_t em_check_downshift(struct em_hw *hw);
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int32_t em_validate_mdi_setting(struct em_hw *hw);
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int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
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int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
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void em_phy_powerdown_workaround(struct em_hw *hw);
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/* EEPROM Functions */
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int32_t em_init_eeprom_params(struct em_hw *hw);
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boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
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int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
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int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
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int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
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/* MNG HOST IF functions */
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uint32_t em_enable_mng_pass_thru(struct em_hw *hw);
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@ -397,37 +378,24 @@ struct em_host_mng_dhcp_cookie{
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uint8_t checksum;
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};
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int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
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int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,
|
||||
uint16_t length);
|
||||
boolean_t em_check_mng_mode(struct em_hw *hw);
|
||||
boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);
|
||||
int32_t em_mng_enable_host_if(struct em_hw *hw);
|
||||
int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer,
|
||||
uint16_t length, uint16_t offset, uint8_t *sum);
|
||||
int32_t em_mng_write_cmd_header(struct em_hw* hw,
|
||||
struct em_host_mng_command_header* hdr);
|
||||
|
||||
int32_t em_mng_write_commit(struct em_hw *hw);
|
||||
|
||||
int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
|
||||
int32_t em_validate_eeprom_checksum(struct em_hw *hw);
|
||||
int32_t em_update_eeprom_checksum(struct em_hw *hw);
|
||||
int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
|
||||
int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
|
||||
int32_t em_read_mac_addr(struct em_hw * hw);
|
||||
int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
|
||||
void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
|
||||
void em_release_software_flag(struct em_hw *hw);
|
||||
int32_t em_get_software_flag(struct em_hw *hw);
|
||||
|
||||
|
||||
/* Filters (multicast, vlan, receive) */
|
||||
void em_init_rx_addrs(struct em_hw *hw);
|
||||
void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
|
||||
uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);
|
||||
void em_mta_set(struct em_hw *hw, uint32_t hash_value);
|
||||
void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
|
||||
void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
|
||||
void em_clear_vfta(struct em_hw *hw);
|
||||
|
||||
/* LED functions */
|
||||
int32_t em_setup_led(struct em_hw *hw);
|
||||
@ -440,6 +408,7 @@ int32_t em_blink_led_start(struct em_hw *hw);
|
||||
|
||||
/* Everything else */
|
||||
void em_clear_hw_cntrs(struct em_hw *hw);
|
||||
|
||||
void em_reset_adaptive(struct em_hw *hw);
|
||||
void em_update_adaptive(struct em_hw *hw);
|
||||
void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
|
||||
@ -448,60 +417,11 @@ void em_pci_set_mwi(struct em_hw *hw);
|
||||
void em_pci_clear_mwi(struct em_hw *hw);
|
||||
void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
|
||||
void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
|
||||
/* Port I/O is only supported on 82544 and newer */
|
||||
uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);
|
||||
void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
|
||||
int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
|
||||
int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
|
||||
int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
|
||||
void em_set_pci_express_master_disable(struct em_hw *hw);
|
||||
void em_enable_pciex_master(struct em_hw *hw);
|
||||
int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);
|
||||
int32_t em_disable_pciex_master(struct em_hw *hw);
|
||||
int32_t em_get_auto_rd_done(struct em_hw *hw);
|
||||
int32_t em_get_phy_cfg_done(struct em_hw *hw);
|
||||
int32_t em_get_software_semaphore(struct em_hw *hw);
|
||||
void em_release_software_semaphore(struct em_hw *hw);
|
||||
int32_t em_check_phy_reset_block(struct em_hw *hw);
|
||||
int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
|
||||
void em_put_hw_eeprom_semaphore(struct em_hw *hw);
|
||||
int32_t em_commit_shadow_ram(struct em_hw *hw);
|
||||
uint8_t em_arc_subsystem_valid(struct em_hw *hw);
|
||||
int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
|
||||
|
||||
int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index,
|
||||
uint8_t *data);
|
||||
int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index,
|
||||
uint8_t byte);
|
||||
int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index,
|
||||
uint8_t byte);
|
||||
int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index,
|
||||
uint16_t *data);
|
||||
int32_t em_write_ich8_word(struct em_hw *hw, uint32_t index,
|
||||
uint16_t word);
|
||||
int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index,
|
||||
uint32_t size, uint16_t *data);
|
||||
int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index,
|
||||
uint32_t size, uint16_t data);
|
||||
int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset,
|
||||
uint16_t words, uint16_t *data);
|
||||
int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset,
|
||||
uint16_t words, uint16_t *data);
|
||||
int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t segment);
|
||||
int32_t em_ich8_cycle_init(struct em_hw *hw);
|
||||
int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
|
||||
int32_t em_phy_ife_get_info(struct em_hw *hw,
|
||||
struct em_phy_info *phy_info);
|
||||
int32_t em_ife_disable_dynamic_power_down(struct em_hw *hw);
|
||||
int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
|
||||
|
||||
#define E1000_BAR_TYPE(v) ((v) & E1000_BAR_TYPE_MASK)
|
||||
#define E1000_BAR_TYPE_MASK 0x00000001
|
||||
#define E1000_BAR_TYPE_MEM 0x00000000
|
||||
#define E1000_BAR_TYPE_IO 0x00000001
|
||||
#define E1000_BAR_MEM_TYPE(v) ((v) & E1000_BAR_MEM_TYPE_MASK)
|
||||
#define E1000_BAR_MEM_TYPE_MASK 0x00000006
|
||||
#define E1000_BAR_MEM_TYPE_32BIT 0x00000000
|
||||
#define E1000_BAR_MEM_TYPE_64BIT 0x00000004
|
||||
|
||||
#ifndef E1000_READ_REG_IO
|
||||
#define E1000_READ_REG_IO(a, reg) \
|
||||
@ -550,6 +470,7 @@ int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
|
||||
#define E1000_DEV_ID_82571EB_FIBER 0x105F
|
||||
#define E1000_DEV_ID_82571EB_SERDES 0x1060
|
||||
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
|
||||
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
|
||||
#define E1000_DEV_ID_82572EI_COPPER 0x107D
|
||||
#define E1000_DEV_ID_82572EI_FIBER 0x107E
|
||||
#define E1000_DEV_ID_82572EI_SERDES 0x107F
|
||||
@ -567,6 +488,8 @@ int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
|
||||
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
|
||||
#define E1000_DEV_ID_ICH8_IGP_C 0x104B
|
||||
#define E1000_DEV_ID_ICH8_IFE 0x104C
|
||||
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
|
||||
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
|
||||
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
|
||||
|
||||
|
||||
@ -639,6 +562,7 @@ int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
|
||||
E1000_IMS_RXO | \
|
||||
E1000_IMS_LSC)
|
||||
|
||||
|
||||
/* Additional interrupts need to be handled for em_ich8lan:
|
||||
DSW = The FW changed the status of the DISSW bit in FWSM
|
||||
PHYINT = The LAN connected device generates an interrupt
|
||||
@ -648,16 +572,18 @@ int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
|
||||
E1000_IMS_PHYINT | \
|
||||
E1000_IMS_EPRST)
|
||||
|
||||
|
||||
/* Number of high/low register pairs in the RAR. The RAR (Receive Address
|
||||
* Registers) holds the directed and multicast addresses that we monitor. We
|
||||
* reserve one of these spots for our directed address, allowing us room for
|
||||
* E1000_RAR_ENTRIES - 1 multicast addresses.
|
||||
*/
|
||||
#define E1000_RAR_ENTRIES 15
|
||||
#define E1000_RAR_ENTRIES_ICH8LAN 7
|
||||
|
||||
#define MIN_NUMBER_OF_DESCRIPTORS 8
|
||||
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
|
||||
#define E1000_RAR_ENTRIES_ICH8LAN 6
|
||||
|
||||
#define MIN_NUMBER_OF_DESCRIPTORS 8
|
||||
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
|
||||
|
||||
/* Receive Descriptor */
|
||||
struct em_rx_desc {
|
||||
@ -778,6 +704,7 @@ union em_rx_desc_packet_split {
|
||||
E1000_RXDEXT_STATERR_CXE | \
|
||||
E1000_RXDEXT_STATERR_RXE)
|
||||
|
||||
|
||||
/* Transmit Descriptor */
|
||||
struct em_tx_desc {
|
||||
uint64_t buffer_addr; /* Address of the descriptor's data buffer */
|
||||
@ -1456,7 +1383,7 @@ struct em_hw {
|
||||
struct em_shadow_ram *eeprom_shadow_ram;
|
||||
uint32_t flash_bank_size;
|
||||
uint32_t flash_base_addr;
|
||||
em_fc_type fc;
|
||||
uint32_t fc;
|
||||
em_bus_speed bus_speed;
|
||||
em_bus_width bus_width;
|
||||
em_bus_type bus_type;
|
||||
@ -1468,6 +1395,7 @@ struct em_hw {
|
||||
uint32_t eeprom_semaphore_present;
|
||||
uint32_t swfw_sync_present;
|
||||
uint32_t swfwhw_semaphore_present;
|
||||
|
||||
unsigned long io_base;
|
||||
uint32_t phy_id;
|
||||
uint32_t phy_revision;
|
||||
@ -1519,6 +1447,7 @@ struct em_hw {
|
||||
boolean_t tbi_compatibility_on;
|
||||
boolean_t laa_is_present;
|
||||
boolean_t phy_reset_disable;
|
||||
boolean_t initialize_hw_bits_disable;
|
||||
boolean_t fc_send_xon;
|
||||
boolean_t fc_strict_ieee;
|
||||
boolean_t report_tx_early;
|
||||
@ -1577,7 +1506,6 @@ struct em_hw {
|
||||
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
|
||||
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
|
||||
#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
|
||||
|
||||
/* Device Status */
|
||||
#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
|
||||
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
|
||||
@ -1651,8 +1579,8 @@ struct em_hw {
|
||||
#define E1000_HICR_FW_RESET 0xC0
|
||||
|
||||
#define E1000_SHADOW_RAM_WORDS 2048
|
||||
#define E1000_ICH8_NVM_SIG_WORD 0x13
|
||||
#define E1000_ICH8_NVM_SIG_MASK 0xC0
|
||||
#define E1000_ICH_NVM_SIG_WORD 0x13
|
||||
#define E1000_ICH_NVM_SIG_MASK 0xC0
|
||||
|
||||
/* EEPROM Read */
|
||||
#define E1000_EERD_START 0x00000001 /* Start Read */
|
||||
@ -1692,16 +1620,17 @@ struct em_hw {
|
||||
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
|
||||
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
|
||||
#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
|
||||
#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
|
||||
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
|
||||
#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
|
||||
#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
|
||||
#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
|
||||
#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
|
||||
#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
|
||||
@ -1836,6 +1765,7 @@ struct em_hw {
|
||||
#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
|
||||
#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
|
||||
|
||||
|
||||
/* Interrupt Cause Set */
|
||||
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
||||
@ -1865,6 +1795,7 @@ struct em_hw {
|
||||
#define E1000_ICS_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_ICS_EPRST E1000_ICR_EPRST
|
||||
|
||||
|
||||
/* Interrupt Mask Set */
|
||||
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
||||
@ -1894,6 +1825,7 @@ struct em_hw {
|
||||
#define E1000_IMS_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_IMS_EPRST E1000_ICR_EPRST
|
||||
|
||||
|
||||
/* Interrupt Mask Clear */
|
||||
#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
||||
@ -1923,6 +1855,7 @@ struct em_hw {
|
||||
#define E1000_IMC_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_IMC_EPRST E1000_ICR_EPRST
|
||||
|
||||
|
||||
/* Receive Control */
|
||||
#define E1000_RCTL_RST 0x00000001 /* Software reset */
|
||||
#define E1000_RCTL_EN 0x00000002 /* enable */
|
||||
@ -2010,6 +1943,13 @@ struct em_hw {
|
||||
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
|
||||
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
|
||||
|
||||
/* Flow Control Settings */
|
||||
#define E1000_FC_NONE 0
|
||||
#define E1000_FC_RX_PAUSE 1
|
||||
#define E1000_FC_TX_PAUSE 2
|
||||
#define E1000_FC_FULL 3
|
||||
#define E1000_FC_DEFAULT 0xFF
|
||||
|
||||
/* Header split receive */
|
||||
#define E1000_RFCTL_ISCSI_DIS 0x00000001
|
||||
#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
|
||||
@ -2297,6 +2237,11 @@ struct em_host_command_info {
|
||||
#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
|
||||
#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
|
||||
|
||||
/* PCI-Ex Config Space */
|
||||
#define PCI_EX_LINK_STATUS 0x12
|
||||
#define PCI_EX_LINK_WIDTH_MASK 0x3F0
|
||||
#define PCI_EX_LINK_WIDTH_SHIFT 4
|
||||
|
||||
/* EEPROM Commands - Microwire */
|
||||
#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
|
||||
#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
|
||||
@ -2604,6 +2549,7 @@ struct em_host_command_info {
|
||||
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
|
||||
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
|
||||
|
||||
|
||||
/* PHY 1000 MII Register/Bit Definitions */
|
||||
/* PHY Registers defined by IEEE */
|
||||
#define PHY_CTRL 0x00 /* Control Register */
|
||||
@ -3199,6 +3145,7 @@ struct em_host_command_info {
|
||||
/* I = Integrated
|
||||
* E = External
|
||||
*/
|
||||
#define M88_VENDOR 0x0141
|
||||
#define M88E1000_E_PHY_ID 0x01410C50
|
||||
#define M88E1000_I_PHY_ID 0x01410C30
|
||||
#define M88E1011_I_PHY_ID 0x01410C20
|
||||
@ -3239,6 +3186,7 @@ struct em_host_command_info {
|
||||
#define IGP3_VR_CTRL \
|
||||
PHY_REG(776, 18) /* Voltage regulator control register */
|
||||
#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
|
||||
#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
|
||||
|
||||
#define IGP3_CAPABILITY \
|
||||
PHY_REG(776, 19) /* IGP3 Capability Register */
|
||||
@ -3323,39 +3271,40 @@ struct em_host_command_info {
|
||||
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
|
||||
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
|
||||
|
||||
#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
|
||||
#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
|
||||
#define ICH8_FLASH_SEG_SIZE_256 256
|
||||
#define ICH8_FLASH_SEG_SIZE_4K 4096
|
||||
#define ICH8_FLASH_SEG_SIZE_64K 65536
|
||||
#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
|
||||
#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
|
||||
#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
|
||||
#define ICH_FLASH_SEG_SIZE_256 256
|
||||
#define ICH_FLASH_SEG_SIZE_4K 4096
|
||||
#define ICH_FLASH_SEG_SIZE_64K 65536
|
||||
|
||||
#define ICH8_CYCLE_READ 0x0
|
||||
#define ICH8_CYCLE_RESERVED 0x1
|
||||
#define ICH8_CYCLE_WRITE 0x2
|
||||
#define ICH8_CYCLE_ERASE 0x3
|
||||
#define ICH_CYCLE_READ 0x0
|
||||
#define ICH_CYCLE_RESERVED 0x1
|
||||
#define ICH_CYCLE_WRITE 0x2
|
||||
#define ICH_CYCLE_ERASE 0x3
|
||||
|
||||
#define ICH8_FLASH_GFPREG 0x0000
|
||||
#define ICH8_FLASH_HSFSTS 0x0004
|
||||
#define ICH8_FLASH_HSFCTL 0x0006
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||||
#define ICH8_FLASH_FADDR 0x0008
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||||
#define ICH8_FLASH_FDATA0 0x0010
|
||||
#define ICH8_FLASH_FRACC 0x0050
|
||||
#define ICH8_FLASH_FREG0 0x0054
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||||
#define ICH8_FLASH_FREG1 0x0058
|
||||
#define ICH8_FLASH_FREG2 0x005C
|
||||
#define ICH8_FLASH_FREG3 0x0060
|
||||
#define ICH8_FLASH_FPR0 0x0074
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||||
#define ICH8_FLASH_FPR1 0x0078
|
||||
#define ICH8_FLASH_SSFSTS 0x0090
|
||||
#define ICH8_FLASH_SSFCTL 0x0092
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||||
#define ICH8_FLASH_PREOP 0x0094
|
||||
#define ICH8_FLASH_OPTYPE 0x0096
|
||||
#define ICH8_FLASH_OPMENU 0x0098
|
||||
#define ICH_FLASH_GFPREG 0x0000
|
||||
#define ICH_FLASH_HSFSTS 0x0004
|
||||
#define ICH_FLASH_HSFCTL 0x0006
|
||||
#define ICH_FLASH_FADDR 0x0008
|
||||
#define ICH_FLASH_FDATA0 0x0010
|
||||
#define ICH_FLASH_FRACC 0x0050
|
||||
#define ICH_FLASH_FREG0 0x0054
|
||||
#define ICH_FLASH_FREG1 0x0058
|
||||
#define ICH_FLASH_FREG2 0x005C
|
||||
#define ICH_FLASH_FREG3 0x0060
|
||||
#define ICH_FLASH_FPR0 0x0074
|
||||
#define ICH_FLASH_FPR1 0x0078
|
||||
#define ICH_FLASH_SSFSTS 0x0090
|
||||
#define ICH_FLASH_SSFCTL 0x0092
|
||||
#define ICH_FLASH_PREOP 0x0094
|
||||
#define ICH_FLASH_OPTYPE 0x0096
|
||||
#define ICH_FLASH_OPMENU 0x0098
|
||||
|
||||
#define ICH8_FLASH_REG_MAPSIZE 0x00A0
|
||||
#define ICH8_FLASH_SECTOR_SIZE 4096
|
||||
#define ICH8_GFPREG_BASE_MASK 0x1FFF
|
||||
#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
|
||||
#define ICH_FLASH_REG_MAPSIZE 0x00A0
|
||||
#define ICH_FLASH_SECTOR_SIZE 4096
|
||||
#define ICH_GFPREG_BASE_MASK 0x1FFF
|
||||
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
|
||||
|
||||
/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
|
||||
/* Offset 04h HSFSTS */
|
||||
@ -3426,3 +3375,5 @@ union ich8_hws_flash_regacc {
|
||||
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
|
||||
|
||||
#endif /* _EM_HW_H_ */
|
||||
|
||||
|
||||
|
||||
@ -148,19 +148,19 @@ struct em_osdep
|
||||
#define E1000_WRITE_REG_ARRAY_DWORD(hw, reg, index, value) \
|
||||
E1000_WRITE_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg) + ((index) << 2), value)
|
||||
|
||||
#define E1000_READ_ICH8_REG(hw, reg) \
|
||||
#define E1000_READ_ICH_FLASH_REG(hw, reg) \
|
||||
bus_space_read_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
|
||||
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
|
||||
|
||||
#define E1000_READ_ICH8_REG16(hw, reg) \
|
||||
#define E1000_READ_ICH_FLASH_REG16(hw, reg) \
|
||||
bus_space_read_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
|
||||
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
|
||||
|
||||
#define E1000_WRITE_ICH8_REG(hw, reg, value) \
|
||||
#define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \
|
||||
bus_space_write_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
|
||||
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
|
||||
|
||||
#define E1000_WRITE_ICH8_REG16(hw, reg, value) \
|
||||
#define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \
|
||||
bus_space_write_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
|
||||
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user