Make cache coherency attributes definitions available in machine/vm.h on MIPS.
Move definitions from cpuregs.h into the cca.h, and include cca.h into vm.h. This is required to make MIPS MD memattr definitions usable in userspace. Sponsored by: The FreeBSD Foundation, Mellanox Technologies MFC after: 1 week Differential revision: https://reviews.freebsd.org/D15583
This commit is contained in:
Konstantin Belousov
parent
bd6313b66e
commit
c9bbc3ef29
@ -45,6 +45,8 @@ __FBSDID("$FreeBSD$");
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#include <string.h>
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#include <unistd.h>
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#include "../../sys/mips/include/cca.h"
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#define _KVM_MINIDUMP
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#include "../../sys/mips/include/cpuregs.h"
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#include "../../sys/mips/include/minidump.h"
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153
sys/mips/include/cca.h
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153
sys/mips/include/cca.h
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@ -0,0 +1,153 @@
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/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
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/*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)machConst.h 8.1 (Berkeley) 6/10/93
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*
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* machConst.h --
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*
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* Machine dependent constants.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
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* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
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* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
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* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_CCA_H_
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#define _MIPS_CCA_H_
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/*
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* Cache Coherency Attributes:
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* UC: Uncached.
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* UA: Uncached accelerated.
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* C: Cacheable, coherency unspecified.
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* CNC: Cacheable non-coherent.
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* CC: Cacheable coherent.
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* CCS: Cacheable coherent, shared read.
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* CCE: Cacheable coherent, exclusive read.
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* CCEW: Cacheable coherent, exclusive write.
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* CCUOW: Cacheable coherent, update on write.
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*
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* Note that some bits vary in meaning across implementations (and that the
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* listing here is no doubt incomplete) and that the optimal cached mode varies
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* between implementations. 0x02 is required to be UC and 0x03 is required to
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* be a least C.
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*
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* We define the following logical bits:
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* UNCACHED:
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* The optimal uncached mode for the target CPU type. This must
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* be suitable for use in accessing memory-mapped devices.
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* CACHED: The optional cached mode for the target CPU type.
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*/
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#define MIPS_CCA_UC 0x02 /* Uncached. */
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#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
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#if defined(CPU_R4000) || defined(CPU_R10000)
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#define MIPS_CCA_CNC 0x03
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#define MIPS_CCA_CCE 0x04
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#define MIPS_CCA_CCEW 0x05
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#ifdef CPU_R4000
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#define MIPS_CCA_CCUOW 0x06
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#endif
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#ifdef CPU_R10000
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#define MIPS_CCA_UA 0x07
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#endif
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#define MIPS_CCA_CACHED MIPS_CCA_CCEW
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#endif /* defined(CPU_R4000) || defined(CPU_R10000) */
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#if defined(CPU_SB1)
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#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
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#endif
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#if defined(CPU_MIPS74K)
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#define MIPS_CCA_UNCACHED 0x02
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#define MIPS_CCA_CACHED 0x03
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#endif
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/*
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* 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
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* Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
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* CCA 0x03 and Uncached Accelerated CCA 0x07
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*/
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#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
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defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
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#define MIPS_CCA_CNC 0x03
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#define MIPS_CCA_CCE 0x04
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#define MIPS_CCA_CCS 0x05
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#define MIPS_CCA_UA 0x07
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/* We use shared read CCA for CACHED CCA */
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#define MIPS_CCA_CACHED MIPS_CCA_CCS
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#endif
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#if defined(CPU_XBURST)
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#define MIPS_CCA_UA 0x01
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#define MIPS_CCA_WC MIPS_CCA_UA
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#endif
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#ifndef MIPS_CCA_UNCACHED
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#define MIPS_CCA_UNCACHED MIPS_CCA_UC
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#endif
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/*
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* If we don't know which cached mode to use and there is a cache coherent
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* mode, use it. If there is not a cache coherent mode, use the required
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* cacheable mode.
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*/
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#ifndef MIPS_CCA_CACHED
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#ifdef MIPS_CCA_CC
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#define MIPS_CCA_CACHED MIPS_CCA_CC
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#else
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#define MIPS_CCA_CACHED MIPS_CCA_C
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#endif
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#endif
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#endif
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@ -60,6 +60,10 @@
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#ifndef _MIPS_CPUREGS_H_
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#define _MIPS_CPUREGS_H_
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#ifndef _KVM_MINIDUMP
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#include <machine/cca.h>
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#endif
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/*
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* Address space.
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* 32-bit mips CPUS partition their 32-bit address space into four segments:
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@ -105,96 +109,6 @@
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#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
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MIPS_IS_KSEG1_ADDR(x))
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/*
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* Cache Coherency Attributes:
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* UC: Uncached.
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* UA: Uncached accelerated.
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* C: Cacheable, coherency unspecified.
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* CNC: Cacheable non-coherent.
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* CC: Cacheable coherent.
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* CCS: Cacheable coherent, shared read.
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* CCE: Cacheable coherent, exclusive read.
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* CCEW: Cacheable coherent, exclusive write.
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* CCUOW: Cacheable coherent, update on write.
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*
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* Note that some bits vary in meaning across implementations (and that the
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* listing here is no doubt incomplete) and that the optimal cached mode varies
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* between implementations. 0x02 is required to be UC and 0x03 is required to
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* be a least C.
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*
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* We define the following logical bits:
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* UNCACHED:
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* The optimal uncached mode for the target CPU type. This must
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* be suitable for use in accessing memory-mapped devices.
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* CACHED: The optional cached mode for the target CPU type.
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*/
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#define MIPS_CCA_UC 0x02 /* Uncached. */
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#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
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#if defined(CPU_R4000) || defined(CPU_R10000)
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#define MIPS_CCA_CNC 0x03
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#define MIPS_CCA_CCE 0x04
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#define MIPS_CCA_CCEW 0x05
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#ifdef CPU_R4000
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#define MIPS_CCA_CCUOW 0x06
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#endif
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#ifdef CPU_R10000
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#define MIPS_CCA_UA 0x07
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#endif
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#define MIPS_CCA_CACHED MIPS_CCA_CCEW
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#endif /* defined(CPU_R4000) || defined(CPU_R10000) */
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#if defined(CPU_SB1)
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#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
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#endif
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#if defined(CPU_MIPS74K)
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#define MIPS_CCA_UNCACHED 0x02
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#define MIPS_CCA_CACHED 0x03
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#endif
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/*
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* 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
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* Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
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* CCA 0x03 and Uncached Accelerated CCA 0x07
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*/
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#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
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defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
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#define MIPS_CCA_CNC 0x03
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#define MIPS_CCA_CCE 0x04
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#define MIPS_CCA_CCS 0x05
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#define MIPS_CCA_UA 0x07
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/* We use shared read CCA for CACHED CCA */
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#define MIPS_CCA_CACHED MIPS_CCA_CCS
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#endif
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#if defined(CPU_XBURST)
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#define MIPS_CCA_UA 0x01
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#define MIPS_CCA_WC MIPS_CCA_UA
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#endif
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#ifndef MIPS_CCA_UNCACHED
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#define MIPS_CCA_UNCACHED MIPS_CCA_UC
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#endif
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/*
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* If we don't know which cached mode to use and there is a cache coherent
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* mode, use it. If there is not a cache coherent mode, use the required
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* cacheable mode.
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*/
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#ifndef MIPS_CCA_CACHED
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#ifdef MIPS_CCA_CC
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#define MIPS_CCA_CACHED MIPS_CCA_CC
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#else
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#define MIPS_CCA_CACHED MIPS_CCA_C
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#endif
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#endif
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#define MIPS_PHYS_TO_XKPHYS(cca,x) \
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((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
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#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
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@ -32,6 +32,7 @@
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#define _MACHINE_VM_H_
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#include <machine/pte.h>
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#include <machine/cca.h>
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/* Memory attributes. */
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#define VM_MEMATTR_UNCACHEABLE ((vm_memattr_t)MIPS_CCA_UNCACHED)
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