o Replace __riscv__ with __riscv
o Replace __riscv64 with (__riscv && __riscv_xlen == 64) This is required to support new GCC 7.1 compiler. This is compatible with current GCC 6.1 compiler. RISC-V is extensible ISA and the idea here is to have built-in define per each extension, so together with __riscv we will have some subset of these as well (depending on -march string passed to compiler): __riscv_compressed __riscv_atomic __riscv_mul __riscv_div __riscv_muldiv __riscv_fdiv __riscv_fsqrt __riscv_float_abi_soft __riscv_float_abi_single __riscv_float_abi_double __riscv_cmodel_medlow __riscv_cmodel_medany __riscv_cmodel_pic __riscv_xlen Reviewed by: ngie Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11901
This commit is contained in:
parent
b96793ae43
commit
ca20f8ec29
@ -250,7 +250,7 @@ printf("%s:%s(%d): DOODAD\n",__FUNCTION__,__FILE__,__LINE__);
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dofr[j].dofr_offset + 4;
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rel->r_info = ELF32_R_INFO(count + dep->de_global,
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R_PPC_REL32);
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/* XXX */
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printf("%s:%s(%d): DOODAD\n",__FUNCTION__,__FILE__,__LINE__);
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#else
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@ -430,7 +430,7 @@ prepare_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, dof_elf64_t *dep)
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dofr[j].dofr_offset;
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rel->r_info = ELF64_R_INFO(count + dep->de_global,
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R_PPC64_REL64);
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/* XXX */
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#elif defined(__i386) || defined(__amd64)
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rel->r_offset = s->dofs_offset +
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@ -904,7 +904,7 @@ dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela,
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return (0);
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}
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/* XXX */
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static int
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dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela,
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@ -311,7 +311,7 @@ pfprint_fp(dtrace_hdl_t *dtp, FILE *fp, const char *format,
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return (dt_printf(dtp, fp, format,
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*((double *)addr) / n));
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#if !defined(__arm__) && !defined(__powerpc__) && \
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!defined(__mips__) && !defined(__riscv__)
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!defined(__mips__) && !defined(__riscv)
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case sizeof (long double):
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return (dt_printf(dtp, fp, format,
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*((long double *)addr) / ldn));
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@ -92,7 +92,7 @@
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* does not have dedicated bit counting instructions.
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*/
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#if defined(__FreeBSD__) && (defined(__sparc64__) || \
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defined(__mips_n64) || defined(__mips_o64) || defined(__riscv__))
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defined(__mips_n64) || defined(__mips_o64) || defined(__riscv))
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si_int __clzsi2(si_int);
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si_int __ctzsi2(si_int);
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#define __builtin_clz __clzsi2
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@ -83,7 +83,7 @@ namespace __sanitizer {
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#elif defined(__powerpc64__)
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const unsigned struct_kernel_stat_sz = 144;
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const unsigned struct_kernel_stat64_sz = 104;
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/* RISCVTODO: check that these values are correct */
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const unsigned struct_kernel_stat_sz = 128;
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const unsigned struct_kernel_stat64_sz = 128;
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@ -126,7 +126,7 @@ namespace __sanitizer {
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#if SANITIZER_LINUX || SANITIZER_FREEBSD
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#if defined(__powerpc64__) || defined(__riscv__) || defined(__s390__)
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#if defined(__powerpc64__) || defined(__riscv) || defined(__s390__)
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const unsigned struct___old_kernel_stat_sz = 0;
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#elif !defined(__sparc__)
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const unsigned struct___old_kernel_stat_sz = 32;
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@ -554,7 +554,7 @@ namespace __sanitizer {
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typedef long __sanitizer___kernel_off_t;
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#endif
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#if defined(__powerpc__) || defined(__mips__) || defined(__riscv__)
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#if defined(__powerpc__) || defined(__mips__) || defined(__riscv)
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typedef unsigned int __sanitizer___kernel_old_uid_t;
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typedef unsigned int __sanitizer___kernel_old_gid_t;
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#else
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@ -97,7 +97,7 @@
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#define LIBELF_BYTEORDER ELFDATA2MSB
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#define LIBELF_CLASS ELFCLASS32
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#elif defined(__riscv64)
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#elif defined(__riscv) && (__riscv_xlen == 64)
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#define LIBELF_ARCH EM_RISCV
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#define LIBELF_BYTEORDER ELFDATA2LSB
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@ -88,7 +88,7 @@ typedef int malloc_cpuid_t;
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# ifdef __powerpc__
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# define LG_QUANTUM 4
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# endif
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# ifdef __riscv__
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# ifdef __riscv
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# define LG_QUANTUM 4
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# endif
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# ifdef __s390__
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@ -67,7 +67,7 @@
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# define LG_VADDR 32
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# define LG_SIZEOF_PTR 2
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#endif
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#ifdef __riscv__
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#ifdef __riscv
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# define LG_VADDR 64
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# define LG_SIZEOF_PTR 3
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#endif
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@ -48,7 +48,7 @@
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# define _LIBUNWIND_CONTEXT_SIZE 16
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# define _LIBUNWIND_CURSOR_SIZE 28
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# define _LIBUNWIND_MAX_REGISTER 32
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# elif defined(__riscv__)
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# elif defined(__riscv)
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_CONTEXT_SIZE 64
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# define _LIBUNWIND_CURSOR_SIZE 76
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@ -478,7 +478,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
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l.jr r9
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l.nop
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#elif defined(__riscv__)
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#elif defined(__riscv)
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//
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// void libunwind::Registers_riscv::jumpto()
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@ -464,7 +464,7 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
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l.sw 120(r3), r30
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l.sw 124(r3), r31
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/* RISCVTODO */
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@ -71,7 +71,7 @@
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(!defined(__APPLE__) && defined(__arm__)) || \
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(defined(__arm64__) || defined(__aarch64__)) || \
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(defined(__APPLE__) && defined(__mips__)) || \
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defined(__riscv__)
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defined(__riscv)
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#define _LIBUNWIND_BUILD_ZERO_COST_APIS 1
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#else
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#define _LIBUNWIND_BUILD_ZERO_COST_APIS 0
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@ -57,7 +57,7 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
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# define REGISTER_KIND Registers_arm
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#elif defined(__or1k__)
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# define REGISTER_KIND Registers_or1k
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#elif defined(__riscv__)
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#elif defined(__riscv)
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# define REGISTER_KIND Registers_riscv
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#elif defined(__mips__)
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# warning The MIPS architecture is not supported.
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@ -135,7 +135,7 @@ ATF_TC_BODY(seekdir_basic, tc)
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}
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/* There is no sbrk on AArch64 and RISC-V */
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#if !defined(__aarch64__) && !defined(__riscv__)
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#if !defined(__aarch64__) && !defined(__riscv)
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ATF_TC(telldir_leak);
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ATF_TC_HEAD(telldir_leak, tc)
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{
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@ -185,7 +185,7 @@ ATF_TP_ADD_TCS(tp)
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{
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ATF_TP_ADD_TC(tp, seekdir_basic);
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#if !defined(__aarch64__) && !defined(__riscv__)
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#if !defined(__aarch64__) && !defined(__riscv)
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ATF_TP_ADD_TC(tp, telldir_leak);
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#endif
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@ -103,7 +103,7 @@ ATF_TC_BODY(mlock_err, tc)
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unsigned long vmin = 0;
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size_t len = sizeof(vmin);
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#endif
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#if !defined(__aarch64__) && !defined(__riscv__)
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#if !defined(__aarch64__) && !defined(__riscv)
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void *invalid_ptr;
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#endif
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int null_errno = ENOMEM; /* error expected for NULL */
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@ -155,7 +155,7 @@ ATF_TC_BODY(mlock_err, tc)
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ATF_REQUIRE_ERRNO(ENOMEM, munlock(buf, page) == -1);
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/* There is no sbrk on AArch64 and RISC-V */
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#if !defined(__aarch64__) && !defined(__riscv__)
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#if !defined(__aarch64__) && !defined(__riscv)
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/*
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* These are permitted to fail (EINVAL) but do not on NetBSD
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*/
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@ -206,7 +206,7 @@ static U64 XXH_read64(const void* memPtr)
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#if defined(_MSC_VER) /* Visual Studio */
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# define XXH_swap32 _byteswap_ulong
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# define XXH_swap64 _byteswap_uint64
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#elif (GCC_VERSION >= 403 && !defined(__riscv__))
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#elif (GCC_VERSION >= 403 && !defined(__riscv))
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# define XXH_swap32 __builtin_bswap32
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# define XXH_swap64 __builtin_bswap64
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#else
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@ -66,7 +66,7 @@ void __libc_free_tls(void *tls, size_t tcbsize, size_t tcbalign);
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#if defined(__amd64__)
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#define TLS_TCB_ALIGN 16
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#elif defined(__aarch64__) || defined(__arm__) || defined(__i386__) || \
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defined(__mips__) || defined(__powerpc__) || defined(__riscv__) || \
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defined(__mips__) || defined(__powerpc__) || defined(__riscv) || \
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defined(__sparc64__)
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#define TLS_TCB_ALIGN sizeof(void *)
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#else
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@ -74,7 +74,7 @@ void __libc_free_tls(void *tls, size_t tcbsize, size_t tcbalign);
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#endif
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#if defined(__aarch64__) || defined(__arm__) || defined(__mips__) || \
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defined(__powerpc__) || defined(__riscv__)
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defined(__powerpc__) || defined(__riscv)
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#define TLS_VARIANT_I
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#endif
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#if defined(__i386__) || defined(__amd64__) || defined(__sparc64__)
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@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
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#elif defined(__powerpc__)
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#define BREAKPOINT_INSTR 0x7fe00008 /* trap */
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#define BREAKPOINT_INSTR_SZ 4
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#elif defined(__riscv__)
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#elif defined(__riscv)
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#define BREAKPOINT_INSTR 0x00100073 /* sbreak */
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#define BREAKPOINT_INSTR_SZ 4
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#else
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@ -67,7 +67,7 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
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*regvalue = regs.r_regs[PC];
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#elif defined(__powerpc__)
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*regvalue = regs.pc;
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#elif defined(__riscv__)
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#elif defined(__riscv)
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*regvalue = regs.sepc;
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#endif
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break;
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@ -84,7 +84,7 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
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*regvalue = regs.r_regs[SP];
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#elif defined(__powerpc__)
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*regvalue = regs.fixreg[1];
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#elif defined(__riscv__)
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#elif defined(__riscv)
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*regvalue = regs.sp;
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#endif
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break;
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@ -122,7 +122,7 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
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regs.r_regs[PC] = regvalue;
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#elif defined(__powerpc__)
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regs.pc = regvalue;
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#elif defined(__riscv__)
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#elif defined(__riscv)
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regs.sepc = regvalue;
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#endif
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break;
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@ -139,7 +139,7 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
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regs.r_regs[PC] = regvalue;
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#elif defined(__powerpc__)
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regs.fixreg[1] = regvalue;
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#elif defined(__riscv__)
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#elif defined(__riscv)
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regs.sp = regvalue;
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#endif
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break;
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@ -4662,7 +4662,7 @@ tls_get_addr_common(Elf_Addr **dtvp, int index, size_t offset)
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}
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#if defined(__aarch64__) || defined(__arm__) || defined(__mips__) || \
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defined(__powerpc__) || defined(__riscv__)
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defined(__powerpc__) || defined(__riscv)
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/*
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* Allocate Static TLS using the Variant I method.
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@ -337,8 +337,8 @@ Architecture-specific macros:
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.It powerpc Ta Dv __powerpc__
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.It powerpcspe Ta Dv __powerpc__, Dv __SPE__
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.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
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.It riscv64 Ta Dv __riscv__, Dv __riscv64
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.It riscv64sf Ta Dv __riscv__, Dv __riscv64
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.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
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.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
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.It sparc64 Ta Dv __sparc64__
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.El
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.Sh SEE ALSO
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@ -51,7 +51,7 @@ extern uint8_t atomic_or_8_nv(volatile uint8_t *target, uint8_t value);
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extern void membar_producer(void);
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#if defined(__sparc64__) || defined(__powerpc__) || defined(__arm__) || \
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defined(__mips__) || defined(__aarch64__) || defined(__riscv__)
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defined(__mips__) || defined(__aarch64__) || defined(__riscv)
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extern void atomic_or_8(volatile uint8_t *target, uint8_t value);
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#else
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static __inline void
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@ -12120,7 +12120,7 @@ dtrace_buffer_alloc(dtrace_buffer_t *bufs, size_t size, int flags,
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*factor = 1;
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#if defined(__aarch64__) || defined(__amd64__) || defined(__arm__) || \
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defined(__mips__) || defined(__powerpc__) || defined(__riscv__)
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defined(__mips__) || defined(__powerpc__) || defined(__riscv)
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/*
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* FreeBSD isn't good at limiting the amount of memory we
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* ask to malloc, so let's place a limit here before trying
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@ -2492,7 +2492,7 @@ extern void dtrace_helpers_destroy(proc_t *);
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#define DTRACE_INVOP_SD 1
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#define DTRACE_INVOP_LD 2
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#elif defined(__riscv__)
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#elif defined(__riscv)
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#define SD_RA_SP_MASK 0x01fff07f
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#define SD_RA_SP 0x00113023
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@ -388,7 +388,7 @@ extern "C" {
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#define _DONT_USE_1275_GENERIC_NAMES
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#define _HAVE_CPUID_INSN
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#elif defined(__riscv__)
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#elif defined(__riscv)
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/*
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* Define the appropriate "processor characteristics"
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@ -143,7 +143,7 @@ struct profile_probe_percpu;
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#define PROF_ARTIFICIAL_FRAMES 10
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#endif
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#ifdef __riscv__
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#ifdef __riscv
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/* TODO: verify */
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#define PROF_ARTIFICIAL_FRAMES 10
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#endif
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@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$");
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#include <linux/mm.h>
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#include <linux/preempt.h>
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#if defined(__amd64__) || defined(__aarch64__) || defined(__riscv__)
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#if defined(__amd64__) || defined(__aarch64__) || defined(__riscv)
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#define LINUXKPI_HAVE_DMAP
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#else
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#undef LINUXKPI_HAVE_DMAP
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@ -138,7 +138,7 @@ typedef u_int32_t u32;
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#define MEMORY_BARRIER() dmb()
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#elif defined __aarch64__
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#define MEMORY_BARRIER() dmb(sy)
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#elif defined __riscv__
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#elif defined __riscv
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#define MEMORY_BARRIER() fence()
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#else
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#error "Not supported platform"
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@ -53,7 +53,7 @@ static struct devmap_entry akva_devmap_entries[AKVA_DEVMAP_MAX_ENTRIES];
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static u_int akva_devmap_idx;
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static vm_offset_t akva_devmap_vaddr = DEVMAP_MAX_VADDR;
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#if defined(__aarch64__) || defined(__riscv__)
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#if defined(__aarch64__) || defined(__riscv)
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extern int early_boot;
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#endif
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@ -197,7 +197,7 @@ devmap_bootstrap(vm_offset_t l1pt, const struct devmap_entry *table)
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pmap_map_chunk(l1pt, pd->pd_va, pd->pd_pa, pd->pd_size,
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VM_PROT_READ | VM_PROT_WRITE, PTE_DEVICE);
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#endif
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#elif defined(__aarch64__) || defined(__riscv__)
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#elif defined(__aarch64__) || defined(__riscv)
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pmap_kenter_device(pd->pd_va, pd->pd_size, pd->pd_pa);
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#endif
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}
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@ -270,7 +270,7 @@ pmap_mapdev(vm_offset_t pa, vm_size_t size)
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pa = trunc_page(pa);
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size = round_page(size + offset);
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#if defined(__aarch64__) || defined(__riscv__)
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#if defined(__aarch64__) || defined(__riscv)
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if (early_boot) {
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akva_devmap_vaddr = trunc_page(akva_devmap_vaddr - size);
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va = akva_devmap_vaddr;
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@ -70,7 +70,7 @@ MODULE_DEPEND(dtraceall, dtmalloc, 1, 1, 1);
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MODULE_DEPEND(dtraceall, dtnfscl, 1, 1, 1);
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#endif
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#if defined(__aarch64__) || defined(__amd64__) || defined(__arm__) || \
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defined(__i386__) || defined(__powerpc__) || defined(__riscv__)
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defined(__i386__) || defined(__powerpc__) || defined(__riscv)
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MODULE_DEPEND(dtraceall, fbt, 1, 1, 1);
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#endif
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#if defined(__amd64__) || defined(__i386__)
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@ -782,7 +782,7 @@
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#endif
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#endif /* __STDC_WANT_LIB_EXT1__ */
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#if defined(__mips) || defined(__powerpc64__) || defined(__riscv__)
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#if defined(__mips) || defined(__powerpc64__) || defined(__riscv)
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#define __NO_TLS 1
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#endif
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||||
|
@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include "extern.h"
|
||||
|
||||
/* We don't support a.out executables on arm64 and riscv */
|
||||
#if !defined(__aarch64__) && !defined(__riscv__)
|
||||
#if !defined(__aarch64__) && !defined(__riscv)
|
||||
#include <a.out.h>
|
||||
#define AOUT_SUPPORTED
|
||||
#endif
|
||||
|
@ -80,7 +80,7 @@
|
||||
#elif __powerpc__
|
||||
#define PTRDIFF_IS_LONG 0
|
||||
#define SIZEOF_IS_ULONG 0
|
||||
#elif __riscv__
|
||||
#elif __riscv
|
||||
#define PTRDIFF_IS_LONG 1
|
||||
#define SIZEOF_IS_ULONG 1
|
||||
#elif __sparc__
|
||||
|
Loading…
Reference in New Issue
Block a user