o Replace __riscv__ with __riscv

o Replace __riscv64 with (__riscv && __riscv_xlen == 64)

This is required to support new GCC 7.1 compiler.
This is compatible with current GCC 6.1 compiler.

RISC-V is extensible ISA and the idea here is to have built-in define
per each extension, so together with __riscv we will have some subset
of these as well (depending on -march string passed to compiler):

__riscv_compressed
__riscv_atomic
__riscv_mul
__riscv_div
__riscv_muldiv
__riscv_fdiv
__riscv_fsqrt
__riscv_float_abi_soft
__riscv_float_abi_single
__riscv_float_abi_double
__riscv_cmodel_medlow
__riscv_cmodel_medany
__riscv_cmodel_pic
__riscv_xlen

Reviewed by:	ngie
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D11901
This commit is contained in:
Ruslan Bukin 2017-08-07 14:09:57 +00:00
parent b96793ae43
commit ca20f8ec29
32 changed files with 45 additions and 45 deletions

View File

@ -250,7 +250,7 @@ printf("%s:%s(%d): DOODAD\n",__FUNCTION__,__FILE__,__LINE__);
dofr[j].dofr_offset + 4;
rel->r_info = ELF32_R_INFO(count + dep->de_global,
R_PPC_REL32);
#elif defined(__riscv__)
#elif defined(__riscv)
/* XXX */
printf("%s:%s(%d): DOODAD\n",__FUNCTION__,__FILE__,__LINE__);
#else
@ -430,7 +430,7 @@ prepare_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, dof_elf64_t *dep)
dofr[j].dofr_offset;
rel->r_info = ELF64_R_INFO(count + dep->de_global,
R_PPC64_REL64);
#elif defined(__riscv__)
#elif defined(__riscv)
/* XXX */
#elif defined(__i386) || defined(__amd64)
rel->r_offset = s->dofs_offset +
@ -904,7 +904,7 @@ dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela,
return (0);
}
#elif defined(__riscv__)
#elif defined(__riscv)
/* XXX */
static int
dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela,

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@ -311,7 +311,7 @@ pfprint_fp(dtrace_hdl_t *dtp, FILE *fp, const char *format,
return (dt_printf(dtp, fp, format,
*((double *)addr) / n));
#if !defined(__arm__) && !defined(__powerpc__) && \
!defined(__mips__) && !defined(__riscv__)
!defined(__mips__) && !defined(__riscv)
case sizeof (long double):
return (dt_printf(dtp, fp, format,
*((long double *)addr) / ldn));

View File

@ -92,7 +92,7 @@
* does not have dedicated bit counting instructions.
*/
#if defined(__FreeBSD__) && (defined(__sparc64__) || \
defined(__mips_n64) || defined(__mips_o64) || defined(__riscv__))
defined(__mips_n64) || defined(__mips_o64) || defined(__riscv))
si_int __clzsi2(si_int);
si_int __ctzsi2(si_int);
#define __builtin_clz __clzsi2

View File

@ -83,7 +83,7 @@ namespace __sanitizer {
#elif defined(__powerpc64__)
const unsigned struct_kernel_stat_sz = 144;
const unsigned struct_kernel_stat64_sz = 104;
#elif defined(__riscv__)
#elif defined(__riscv)
/* RISCVTODO: check that these values are correct */
const unsigned struct_kernel_stat_sz = 128;
const unsigned struct_kernel_stat64_sz = 128;
@ -126,7 +126,7 @@ namespace __sanitizer {
#if SANITIZER_LINUX || SANITIZER_FREEBSD
#if defined(__powerpc64__) || defined(__riscv__) || defined(__s390__)
#if defined(__powerpc64__) || defined(__riscv) || defined(__s390__)
const unsigned struct___old_kernel_stat_sz = 0;
#elif !defined(__sparc__)
const unsigned struct___old_kernel_stat_sz = 32;
@ -554,7 +554,7 @@ namespace __sanitizer {
typedef long __sanitizer___kernel_off_t;
#endif
#if defined(__powerpc__) || defined(__mips__) || defined(__riscv__)
#if defined(__powerpc__) || defined(__mips__) || defined(__riscv)
typedef unsigned int __sanitizer___kernel_old_uid_t;
typedef unsigned int __sanitizer___kernel_old_gid_t;
#else

View File

@ -97,7 +97,7 @@
#define LIBELF_BYTEORDER ELFDATA2MSB
#define LIBELF_CLASS ELFCLASS32
#elif defined(__riscv64)
#elif defined(__riscv) && (__riscv_xlen == 64)
#define LIBELF_ARCH EM_RISCV
#define LIBELF_BYTEORDER ELFDATA2LSB

View File

@ -88,7 +88,7 @@ typedef int malloc_cpuid_t;
# ifdef __powerpc__
# define LG_QUANTUM 4
# endif
# ifdef __riscv__
# ifdef __riscv
# define LG_QUANTUM 4
# endif
# ifdef __s390__

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@ -67,7 +67,7 @@
# define LG_VADDR 32
# define LG_SIZEOF_PTR 2
#endif
#ifdef __riscv__
#ifdef __riscv
# define LG_VADDR 64
# define LG_SIZEOF_PTR 3
#endif

View File

@ -48,7 +48,7 @@
# define _LIBUNWIND_CONTEXT_SIZE 16
# define _LIBUNWIND_CURSOR_SIZE 28
# define _LIBUNWIND_MAX_REGISTER 32
# elif defined(__riscv__)
# elif defined(__riscv)
# define _LIBUNWIND_TARGET_RISCV 1
# define _LIBUNWIND_CONTEXT_SIZE 64
# define _LIBUNWIND_CURSOR_SIZE 76

View File

@ -478,7 +478,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
l.jr r9
l.nop
#elif defined(__riscv__)
#elif defined(__riscv)
//
// void libunwind::Registers_riscv::jumpto()

View File

@ -464,7 +464,7 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
l.sw 120(r3), r30
l.sw 124(r3), r31
#elif defined(__riscv__)
#elif defined(__riscv)
/* RISCVTODO */

View File

@ -71,7 +71,7 @@
(!defined(__APPLE__) && defined(__arm__)) || \
(defined(__arm64__) || defined(__aarch64__)) || \
(defined(__APPLE__) && defined(__mips__)) || \
defined(__riscv__)
defined(__riscv)
#define _LIBUNWIND_BUILD_ZERO_COST_APIS 1
#else
#define _LIBUNWIND_BUILD_ZERO_COST_APIS 0

View File

@ -57,7 +57,7 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
# define REGISTER_KIND Registers_arm
#elif defined(__or1k__)
# define REGISTER_KIND Registers_or1k
#elif defined(__riscv__)
#elif defined(__riscv)
# define REGISTER_KIND Registers_riscv
#elif defined(__mips__)
# warning The MIPS architecture is not supported.

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@ -135,7 +135,7 @@ ATF_TC_BODY(seekdir_basic, tc)
}
/* There is no sbrk on AArch64 and RISC-V */
#if !defined(__aarch64__) && !defined(__riscv__)
#if !defined(__aarch64__) && !defined(__riscv)
ATF_TC(telldir_leak);
ATF_TC_HEAD(telldir_leak, tc)
{
@ -185,7 +185,7 @@ ATF_TP_ADD_TCS(tp)
{
ATF_TP_ADD_TC(tp, seekdir_basic);
#if !defined(__aarch64__) && !defined(__riscv__)
#if !defined(__aarch64__) && !defined(__riscv)
ATF_TP_ADD_TC(tp, telldir_leak);
#endif

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@ -103,7 +103,7 @@ ATF_TC_BODY(mlock_err, tc)
unsigned long vmin = 0;
size_t len = sizeof(vmin);
#endif
#if !defined(__aarch64__) && !defined(__riscv__)
#if !defined(__aarch64__) && !defined(__riscv)
void *invalid_ptr;
#endif
int null_errno = ENOMEM; /* error expected for NULL */
@ -155,7 +155,7 @@ ATF_TC_BODY(mlock_err, tc)
ATF_REQUIRE_ERRNO(ENOMEM, munlock(buf, page) == -1);
/* There is no sbrk on AArch64 and RISC-V */
#if !defined(__aarch64__) && !defined(__riscv__)
#if !defined(__aarch64__) && !defined(__riscv)
/*
* These are permitted to fail (EINVAL) but do not on NetBSD
*/

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@ -206,7 +206,7 @@ static U64 XXH_read64(const void* memPtr)
#if defined(_MSC_VER) /* Visual Studio */
# define XXH_swap32 _byteswap_ulong
# define XXH_swap64 _byteswap_uint64
#elif (GCC_VERSION >= 403 && !defined(__riscv__))
#elif (GCC_VERSION >= 403 && !defined(__riscv))
# define XXH_swap32 __builtin_bswap32
# define XXH_swap64 __builtin_bswap64
#else

View File

@ -66,7 +66,7 @@ void __libc_free_tls(void *tls, size_t tcbsize, size_t tcbalign);
#if defined(__amd64__)
#define TLS_TCB_ALIGN 16
#elif defined(__aarch64__) || defined(__arm__) || defined(__i386__) || \
defined(__mips__) || defined(__powerpc__) || defined(__riscv__) || \
defined(__mips__) || defined(__powerpc__) || defined(__riscv) || \
defined(__sparc64__)
#define TLS_TCB_ALIGN sizeof(void *)
#else
@ -74,7 +74,7 @@ void __libc_free_tls(void *tls, size_t tcbsize, size_t tcbalign);
#endif
#if defined(__aarch64__) || defined(__arm__) || defined(__mips__) || \
defined(__powerpc__) || defined(__riscv__)
defined(__powerpc__) || defined(__riscv)
#define TLS_VARIANT_I
#endif
#if defined(__i386__) || defined(__amd64__) || defined(__sparc64__)

View File

@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
#elif defined(__powerpc__)
#define BREAKPOINT_INSTR 0x7fe00008 /* trap */
#define BREAKPOINT_INSTR_SZ 4
#elif defined(__riscv__)
#elif defined(__riscv)
#define BREAKPOINT_INSTR 0x00100073 /* sbreak */
#define BREAKPOINT_INSTR_SZ 4
#else

View File

@ -67,7 +67,7 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
*regvalue = regs.r_regs[PC];
#elif defined(__powerpc__)
*regvalue = regs.pc;
#elif defined(__riscv__)
#elif defined(__riscv)
*regvalue = regs.sepc;
#endif
break;
@ -84,7 +84,7 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
*regvalue = regs.r_regs[SP];
#elif defined(__powerpc__)
*regvalue = regs.fixreg[1];
#elif defined(__riscv__)
#elif defined(__riscv)
*regvalue = regs.sp;
#endif
break;
@ -122,7 +122,7 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
regs.r_regs[PC] = regvalue;
#elif defined(__powerpc__)
regs.pc = regvalue;
#elif defined(__riscv__)
#elif defined(__riscv)
regs.sepc = regvalue;
#endif
break;
@ -139,7 +139,7 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
regs.r_regs[PC] = regvalue;
#elif defined(__powerpc__)
regs.fixreg[1] = regvalue;
#elif defined(__riscv__)
#elif defined(__riscv)
regs.sp = regvalue;
#endif
break;

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@ -4662,7 +4662,7 @@ tls_get_addr_common(Elf_Addr **dtvp, int index, size_t offset)
}
#if defined(__aarch64__) || defined(__arm__) || defined(__mips__) || \
defined(__powerpc__) || defined(__riscv__)
defined(__powerpc__) || defined(__riscv)
/*
* Allocate Static TLS using the Variant I method.

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@ -337,8 +337,8 @@ Architecture-specific macros:
.It powerpc Ta Dv __powerpc__
.It powerpcspe Ta Dv __powerpc__, Dv __SPE__
.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
.It riscv64 Ta Dv __riscv__, Dv __riscv64
.It riscv64sf Ta Dv __riscv__, Dv __riscv64
.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
.It sparc64 Ta Dv __sparc64__
.El
.Sh SEE ALSO

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@ -51,7 +51,7 @@ extern uint8_t atomic_or_8_nv(volatile uint8_t *target, uint8_t value);
extern void membar_producer(void);
#if defined(__sparc64__) || defined(__powerpc__) || defined(__arm__) || \
defined(__mips__) || defined(__aarch64__) || defined(__riscv__)
defined(__mips__) || defined(__aarch64__) || defined(__riscv)
extern void atomic_or_8(volatile uint8_t *target, uint8_t value);
#else
static __inline void

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@ -12120,7 +12120,7 @@ dtrace_buffer_alloc(dtrace_buffer_t *bufs, size_t size, int flags,
*factor = 1;
#if defined(__aarch64__) || defined(__amd64__) || defined(__arm__) || \
defined(__mips__) || defined(__powerpc__) || defined(__riscv__)
defined(__mips__) || defined(__powerpc__) || defined(__riscv)
/*
* FreeBSD isn't good at limiting the amount of memory we
* ask to malloc, so let's place a limit here before trying

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@ -2492,7 +2492,7 @@ extern void dtrace_helpers_destroy(proc_t *);
#define DTRACE_INVOP_SD 1
#define DTRACE_INVOP_LD 2
#elif defined(__riscv__)
#elif defined(__riscv)
#define SD_RA_SP_MASK 0x01fff07f
#define SD_RA_SP 0x00113023

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@ -388,7 +388,7 @@ extern "C" {
#define _DONT_USE_1275_GENERIC_NAMES
#define _HAVE_CPUID_INSN
#elif defined(__riscv__)
#elif defined(__riscv)
/*
* Define the appropriate "processor characteristics"

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@ -143,7 +143,7 @@ struct profile_probe_percpu;
#define PROF_ARTIFICIAL_FRAMES 10
#endif
#ifdef __riscv__
#ifdef __riscv
/* TODO: verify */
#define PROF_ARTIFICIAL_FRAMES 10
#endif

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@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$");
#include <linux/mm.h>
#include <linux/preempt.h>
#if defined(__amd64__) || defined(__aarch64__) || defined(__riscv__)
#if defined(__amd64__) || defined(__aarch64__) || defined(__riscv)
#define LINUXKPI_HAVE_DMAP
#else
#undef LINUXKPI_HAVE_DMAP

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@ -138,7 +138,7 @@ typedef u_int32_t u32;
#define MEMORY_BARRIER() dmb()
#elif defined __aarch64__
#define MEMORY_BARRIER() dmb(sy)
#elif defined __riscv__
#elif defined __riscv
#define MEMORY_BARRIER() fence()
#else
#error "Not supported platform"

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@ -53,7 +53,7 @@ static struct devmap_entry akva_devmap_entries[AKVA_DEVMAP_MAX_ENTRIES];
static u_int akva_devmap_idx;
static vm_offset_t akva_devmap_vaddr = DEVMAP_MAX_VADDR;
#if defined(__aarch64__) || defined(__riscv__)
#if defined(__aarch64__) || defined(__riscv)
extern int early_boot;
#endif
@ -197,7 +197,7 @@ devmap_bootstrap(vm_offset_t l1pt, const struct devmap_entry *table)
pmap_map_chunk(l1pt, pd->pd_va, pd->pd_pa, pd->pd_size,
VM_PROT_READ | VM_PROT_WRITE, PTE_DEVICE);
#endif
#elif defined(__aarch64__) || defined(__riscv__)
#elif defined(__aarch64__) || defined(__riscv)
pmap_kenter_device(pd->pd_va, pd->pd_size, pd->pd_pa);
#endif
}
@ -270,7 +270,7 @@ pmap_mapdev(vm_offset_t pa, vm_size_t size)
pa = trunc_page(pa);
size = round_page(size + offset);
#if defined(__aarch64__) || defined(__riscv__)
#if defined(__aarch64__) || defined(__riscv)
if (early_boot) {
akva_devmap_vaddr = trunc_page(akva_devmap_vaddr - size);
va = akva_devmap_vaddr;

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@ -70,7 +70,7 @@ MODULE_DEPEND(dtraceall, dtmalloc, 1, 1, 1);
MODULE_DEPEND(dtraceall, dtnfscl, 1, 1, 1);
#endif
#if defined(__aarch64__) || defined(__amd64__) || defined(__arm__) || \
defined(__i386__) || defined(__powerpc__) || defined(__riscv__)
defined(__i386__) || defined(__powerpc__) || defined(__riscv)
MODULE_DEPEND(dtraceall, fbt, 1, 1, 1);
#endif
#if defined(__amd64__) || defined(__i386__)

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@ -782,7 +782,7 @@
#endif
#endif /* __STDC_WANT_LIB_EXT1__ */
#if defined(__mips) || defined(__powerpc64__) || defined(__riscv__)
#if defined(__mips) || defined(__powerpc64__) || defined(__riscv)
#define __NO_TLS 1
#endif

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@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
#include "extern.h"
/* We don't support a.out executables on arm64 and riscv */
#if !defined(__aarch64__) && !defined(__riscv__)
#if !defined(__aarch64__) && !defined(__riscv)
#include <a.out.h>
#define AOUT_SUPPORTED
#endif

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@ -80,7 +80,7 @@
#elif __powerpc__
#define PTRDIFF_IS_LONG 0
#define SIZEOF_IS_ULONG 0
#elif __riscv__
#elif __riscv
#define PTRDIFF_IS_LONG 1
#define SIZEOF_IS_ULONG 1
#elif __sparc__