Omnibus PCI commit:
o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
This commit is contained in:
imp
parent
fd75a2f931
commit
ca56ea20fc
@ -79,7 +79,7 @@ static device_method_t acpi_pci_methods[] = {
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DEVMETHOD(device_probe, acpi_pci_probe),
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DEVMETHOD(device_attach, acpi_pci_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_suspend, pci_suspend),
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DEVMETHOD(device_resume, pci_resume),
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/* Bus interface */
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@ -87,7 +87,7 @@ static device_method_t acpi_pci_methods[] = {
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DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
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DEVMETHOD(bus_read_ivar, acpi_pci_read_ivar),
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DEVMETHOD(bus_write_ivar, pci_write_ivar),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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DEVMETHOD(bus_driver_added, pci_driver_added),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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@ -70,6 +70,10 @@ static void acpi_pcib_write_config(device_t dev, int bus, int slot, int func, i
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u_int32_t data, int bytes);
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static int acpi_pcib_acpi_route_interrupt(device_t pcib,
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device_t dev, int pin);
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static struct resource *acpi_pcib_acpi_alloc_resource(device_t dev,
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device_t child, int type, int *rid,
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u_long start, u_long end, u_long count,
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u_int flags);
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static device_method_t acpi_pcib_acpi_methods[] = {
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/* Device interface */
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@ -83,7 +87,7 @@ static device_method_t acpi_pcib_acpi_methods[] = {
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, acpi_pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, acpi_pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
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DEVMETHOD(bus_alloc_resource, acpi_pcib_acpi_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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@ -289,3 +293,20 @@ acpi_pcib_acpi_route_interrupt(device_t pcib, device_t dev, int pin)
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sc = device_get_softc(pcib);
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return (acpi_pcib_route_interrupt(pcib, dev, pin, &sc->ap_prt));
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}
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struct resource *
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acpi_pcib_acpi_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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/*
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* If no memory preference is given, use upper 256MB slot most
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* bioses use for their memory window. Typically other bridges
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* before us get in the way to assert their preferences on memory.
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* Hardcoding like this sucks, so a more MD/MI way needs to be
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* found to do it.
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*/
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if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
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start = 0xf0000000;
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return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
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count, flags));
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}
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@ -68,7 +68,8 @@ static void pci_fixancient(pcicfgregs *cfg);
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static int pci_porten(device_t pcib, int b, int s, int f);
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static int pci_memen(device_t pcib, int b, int s, int f);
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static int pci_add_map(device_t pcib, int b, int s, int f, int reg,
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static int pci_add_map(device_t pcib, device_t bus, device_t dev,
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int b, int s, int f, int reg,
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struct resource_list *rl);
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static void pci_add_resources(device_t pcib, device_t bus,
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device_t dev);
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@ -82,13 +83,15 @@ static int pci_modevent(module_t mod, int what, void *arg);
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static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
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pcicfgregs *cfg);
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static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
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static void pci_cfg_restore(device_t, struct pci_devinfo *);
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static void pci_cfg_save(device_t, struct pci_devinfo *, int);
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static device_method_t pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pci_probe),
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DEVMETHOD(device_attach, pci_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_suspend, pci_suspend),
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DEVMETHOD(device_resume, pci_resume),
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/* Bus interface */
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@ -96,7 +99,7 @@ static device_method_t pci_methods[] = {
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DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
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DEVMETHOD(bus_read_ivar, pci_read_ivar),
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DEVMETHOD(bus_write_ivar, pci_write_ivar),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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DEVMETHOD(bus_driver_added, pci_driver_added),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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@ -613,6 +616,7 @@ pci_enable_io_method(device_t dev, device_t child, int space)
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return (EINVAL);
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}
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pci_set_command_bit(dev, child, bit);
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/* Some devices seem to need a brief stall here, what do to? */
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command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
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if (command & bit)
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return (0);
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@ -719,11 +723,12 @@ pci_memen(device_t pcib, int b, int s, int f)
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* register is a 32bit map register or 2 if it is a 64bit register.
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*/
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static int
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pci_add_map(device_t pcib, int b, int s, int f, int reg,
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struct resource_list *rl)
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pci_add_map(device_t pcib, device_t bus, device_t dev,
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int b, int s, int f, int reg, struct resource_list *rl)
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{
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uint32_t map;
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uint64_t base;
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uint64_t start, end, count;
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uint8_t ln2size;
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uint8_t ln2range;
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uint32_t testval;
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@ -731,25 +736,34 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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int type;
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map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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if (map == 0 || map == 0xffffffff)
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return (1); /* skip invalid entry */
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
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testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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base = pci_mapbase(map);
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if (pci_maptype(map) & PCI_MAPMEM)
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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base = pci_mapbase(map);
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/*
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* For I/O registers, if bottom bit is set, and the next bit up
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* isn't clear, we know we have a BAR that doesn't conform to the
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* spec, so ignore it. Also, sanity check the size of the data
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* areas to the type of memory involved.
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*/
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if ((testval & 0x1) == 0x1 &&
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(testval & 0x2) != 0)
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return (1);
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if ((type == SYS_RES_MEMORY && ln2size < 5) ||
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(type == SYS_RES_IOPORT && ln2size < 3))
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return (1);
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if (ln2range == 64)
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/* Read the other half of a 64bit map register */
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base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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}
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if (bootverbose) {
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printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
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@ -765,9 +779,10 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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/*
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* This code theoretically does the right thing, but has
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* undesirable side effects in some cases where
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* peripherals respond oddly to having these bits
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* enabled. Leave them alone by default.
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* undesirable side effects in some cases where peripherals
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* respond oddly to having these bits enabled. Let the user
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* be able to turn them off (since pci_enable_io_modes is 1 by
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* default).
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*/
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if (pci_enable_io_modes) {
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/* Turn on resources that have been left off by a lazy BIOS */
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@ -787,9 +802,23 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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return (1);
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}
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resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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/*
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* If base is 0, then we have problems. It is best to ignore
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* such entires for the moment. These will be allocated later if
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* the driver specifically requests them.
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*/
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if (base == 0)
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return 1;
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start = base;
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end = base + (1 << ln2size) - 1;
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count = 1 << ln2size;
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resource_list_add(rl, type, reg, start, end, count);
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/*
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* Not quite sure what to do on failure of allocating the resource
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* since I can postulate several right answers.
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*/
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resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0);
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return ((ln2range == 64) ? 2 : 1);
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}
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@ -805,14 +834,13 @@ pci_add_resources(device_t pcib, device_t bus, device_t dev)
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b = cfg->bus;
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s = cfg->slot;
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f = cfg->func;
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for (i = 0; i < cfg->nummaps;) {
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i += pci_add_map(pcib, b, s, f, PCIR_BAR(i), rl);
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}
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for (i = 0; i < cfg->nummaps;)
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i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), rl);
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for (q = &pci_quirks[0]; q->devid; q++) {
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if (q->devid == ((cfg->device << 16) | cfg->vendor)
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&& q->type == PCI_QUIRK_MAP_REG)
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pci_add_map(pcib, b, s, f, q->arg1, rl);
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pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl);
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}
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if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
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@ -873,6 +901,8 @@ pci_add_child(device_t bus, struct pci_devinfo *dinfo)
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pcib = device_get_parent(bus);
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dinfo->cfg.dev = device_add_child(bus, NULL, -1);
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device_set_ivars(dinfo->cfg.dev, dinfo);
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pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
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pci_cfg_restore(dinfo->cfg.dev, dinfo);
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pci_add_resources(pcib, bus, dinfo->cfg.dev);
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pci_print_verbose(dinfo);
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}
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@ -907,6 +937,52 @@ pci_attach(device_t dev)
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return (bus_generic_attach(dev));
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}
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int
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pci_suspend(device_t dev)
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{
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int numdevs;
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device_t *devlist;
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device_t child;
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struct pci_devinfo *dinfo;
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int i;
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/*
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* Save the pci configuration space for each child. We don't need
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* to do this, unless the BIOS suspend code powers down the bus and
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* the devices on the bus.
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*/
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device_get_children(dev, &devlist, &numdevs);
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for (i = 0; i < numdevs; i++) {
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child = devlist[i];
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dinfo = (struct pci_devinfo *) device_get_ivars(child);
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pci_cfg_save(child, dinfo, 0);
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}
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free(devlist, M_TEMP);
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return (bus_generic_suspend(dev));
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}
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int
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pci_resume(device_t dev)
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{
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int numdevs;
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device_t *devlist;
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device_t child;
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struct pci_devinfo *dinfo;
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int i;
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/*
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* Restore the pci configuration space for each child.
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*/
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device_get_children(dev, &devlist, &numdevs);
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for (i = 0; i < numdevs; i++) {
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child = devlist[i];
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dinfo = (struct pci_devinfo *) device_get_ivars(child);
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pci_cfg_restore(child, dinfo);
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}
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free(devlist, M_TEMP);
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return (bus_generic_resume(dev));
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}
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static void
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pci_load_vendor_data(void)
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{
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@ -922,6 +998,34 @@ pci_load_vendor_data(void)
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}
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}
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void
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pci_driver_added(device_t dev, driver_t *driver)
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{
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int numdevs;
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device_t *devlist;
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device_t child;
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struct pci_devinfo *dinfo;
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int i;
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device_printf(dev, "driver added\n");
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DEVICE_IDENTIFY(driver, dev);
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device_get_children(dev, &devlist, &numdevs);
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for (i = 0; i < numdevs; i++) {
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child = devlist[i];
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if (device_get_state(child) != DS_NOTPRESENT)
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continue;
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dinfo = device_get_ivars(child);
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pci_print_verbose(dinfo);
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/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */
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printf("pci%d:%d:%d: reprobing on driver added\n",
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dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
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pci_cfg_restore(child, dinfo);
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if (device_probe_and_attach(child) != 0)
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pci_cfg_save(child, dinfo, 1);
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}
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free(devlist, M_TEMP);
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}
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int
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pci_print_child(device_t dev, device_t child)
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{
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@ -1047,6 +1151,7 @@ pci_probe_nomatch(device_t dev, device_t child)
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}
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printf(" at device %d.%d (no driver attached)\n",
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pci_get_slot(child), pci_get_function(child));
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pci_cfg_save(child, (struct pci_devinfo *) device_get_ivars(child), 1);
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return;
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}
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@ -1326,18 +1431,78 @@ DB_SHOW_COMMAND(pciregs, db_pci_dump)
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}
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#endif /* DDB */
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/*
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* XXX I'm not sure the following is good for 64-bit bars.
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*/
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static struct resource *
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pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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struct resource_list *rl = &dinfo->resources;
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struct resource_list_entry *rle;
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struct resource *res;
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uint32_t map, testval;
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int mapsize;
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/*
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* Weed out the bogons, and figure out how large the BAR/map is.
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*/
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map = pci_read_config(child, *rid, 4);
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if (pci_maptype(map) & PCI_MAPMEM) {
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if (type != SYS_RES_MEMORY) {
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device_printf(child, "rid %#x says memory, driver wants %d failed.\n", *rid, type);
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return (NULL);
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}
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} else {
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if (type != SYS_RES_IOPORT) {
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device_printf(child, "rid %#x says ioport, driver wants %d failed.\n", *rid, type);
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return (NULL);
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}
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}
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pci_write_config(child, *rid, 0xffffffff, 4);
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testval = pci_read_config(child, *rid, 4);
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/*
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* Allocate enough resource, and then write back the
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* appropriate bar for that resource (this is the part
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* I'm not sure is good for 64-bit bars).
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*/
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mapsize = pci_mapsize(testval);
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count = 1 << mapsize;
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if (RF_ALIGNMENT(flags) < mapsize)
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flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
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res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
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start, end, count, flags);
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if (res == NULL) {
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device_printf(child, "%#lx bytes of rid %#x res %d failed.\n",
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count, *rid, type);
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pci_write_config(child, *rid, map, 4);
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return (NULL);
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}
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resource_list_add(rl, type, *rid, start, end, count);
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rle = resource_list_find(rl, type, *rid);
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if (rle == NULL)
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panic("pci_alloc_map: unexpedly can't find resource.");
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rle->res = res;
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device_printf(child, "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
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count, *rid, type, rman_get_start(res));
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pci_write_config(child, *rid, rman_get_start(res), 4);
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return (res);
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}
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struct resource *
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pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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struct resource_list *rl = &dinfo->resources;
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struct resource_list_entry *rle;
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pcicfgregs *cfg = &dinfo->cfg;
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/*
|
||||
* Perform lazy resource allocation
|
||||
*
|
||||
* XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
|
||||
*/
|
||||
if (device_get_parent(child) == dev) {
|
||||
switch (type) {
|
||||
@ -1363,16 +1528,39 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
if (*rid < PCIR_BAR(cfg->nummaps)) {
|
||||
/*
|
||||
* Enable the I/O mode. We should
|
||||
* also be allocating resources
|
||||
* too. XXX
|
||||
* also be assigning resources too
|
||||
* when none are present. The
|
||||
* resource_list_alloc kind of sorta does
|
||||
* this...
|
||||
*/
|
||||
if (PCI_ENABLE_IO(dev, child, type))
|
||||
return (NULL);
|
||||
}
|
||||
rle = resource_list_find(rl, type, *rid);
|
||||
if (rle == NULL)
|
||||
return (pci_alloc_map(dev, child, type, rid,
|
||||
start, end, count, flags));
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* If we've already allocated the resource, then
|
||||
* return it now. But first we may need to activate
|
||||
* it, since we don't allocate the resource as active
|
||||
* above. Normally this would be done down in the
|
||||
* nexus, but since we short-circuit that path we have
|
||||
* to do its job here. Not sure if we should free the
|
||||
* resource if it fails to activate.
|
||||
*/
|
||||
rle = resource_list_find(rl, type, *rid);
|
||||
if (rle != NULL && rle->res != NULL) {
|
||||
device_printf(child, "Bus reserved %#lx bytes for rid %#x type %d at %#lx\n", rman_get_size(rle->res), *rid, type, rman_get_start(rle->res));
|
||||
if ((flags & RF_ACTIVE) &&
|
||||
bus_generic_activate_resource(dev, child, type,
|
||||
*rid, rle->res) != 0)
|
||||
return NULL;
|
||||
return (rle->res);
|
||||
}
|
||||
}
|
||||
|
||||
return (resource_list_alloc(rl, dev, child, type, rid,
|
||||
start, end, count, flags));
|
||||
}
|
||||
@ -1416,13 +1604,9 @@ pci_delete_resource(device_t dev, device_t child, int type, int rid)
|
||||
struct resource_list *
|
||||
pci_get_resource_list (device_t dev, device_t child)
|
||||
{
|
||||
struct pci_devinfo * dinfo = device_get_ivars(child);
|
||||
struct resource_list * rl = &dinfo->resources;
|
||||
struct pci_devinfo *dinfo = device_get_ivars(child);
|
||||
|
||||
if (!rl)
|
||||
return (NULL);
|
||||
|
||||
return (rl);
|
||||
return (&dinfo->resources);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
@ -1447,7 +1631,7 @@ pci_write_config_method(device_t dev, device_t child, int reg,
|
||||
}
|
||||
|
||||
int
|
||||
pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
|
||||
pci_child_location_str_method(device_t dev, device_t child, char *buf,
|
||||
size_t buflen)
|
||||
{
|
||||
struct pci_devinfo *dinfo;
|
||||
@ -1459,7 +1643,7 @@ pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
|
||||
}
|
||||
|
||||
int
|
||||
pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
|
||||
pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
|
||||
size_t buflen)
|
||||
{
|
||||
struct pci_devinfo *dinfo;
|
||||
@ -1506,34 +1690,86 @@ pci_modevent(module_t mod, int what, void *arg)
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
pci_resume(device_t dev)
|
||||
static void
|
||||
pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
|
||||
{
|
||||
int numdevs;
|
||||
int i;
|
||||
device_t *children;
|
||||
device_t child;
|
||||
struct pci_devinfo *dinfo;
|
||||
pcicfgregs *cfg;
|
||||
int i;
|
||||
|
||||
device_get_children(dev, &children, &numdevs);
|
||||
|
||||
for (i = 0; i < numdevs; i++) {
|
||||
child = children[i];
|
||||
|
||||
dinfo = device_get_ivars(child);
|
||||
cfg = &dinfo->cfg;
|
||||
if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
|
||||
cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
|
||||
if (PCI_INTERRUPT_VALID(cfg->intline)) {
|
||||
pci_write_config(child, PCIR_INTLINE,
|
||||
cfg->intline, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
free(children, M_TEMP);
|
||||
|
||||
return (bus_generic_resume(dev));
|
||||
/*
|
||||
* Only do header type 0 devices. Type 1 devices are bridges, which
|
||||
* we know need special treatment. Type 2 devices are cardbus bridges
|
||||
* which also require special treatment. Other types are unknown, and
|
||||
* we err on the side of safety by ignoring them.
|
||||
*/
|
||||
if (dinfo->cfg.hdrtype != 0)
|
||||
return;
|
||||
printf("pci%d:%d:%d: setting power state D0\n", dinfo->cfg.bus,
|
||||
dinfo->cfg.slot, dinfo->cfg.func);
|
||||
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
||||
for (i = 0; i < dinfo->cfg.nummaps; i++)
|
||||
pci_write_config(dev, PCIR_MAPS + i * 4, dinfo->cfg.bar[i], 4);
|
||||
pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
|
||||
pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
|
||||
pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
|
||||
pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
|
||||
pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
|
||||
pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
|
||||
pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
|
||||
pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
|
||||
{
|
||||
int i;
|
||||
uint32_t cls;
|
||||
|
||||
/*
|
||||
* Only do header type 0 devices. Type 1 devices are bridges, which
|
||||
* we know need special treatment. Type 2 devices are cardbus bridges
|
||||
* which also require special treatment. Other types are unknown, and
|
||||
* we err on the side of safety by ignoring them. Powering down
|
||||
* bridges should not be undertaken lightly.
|
||||
*/
|
||||
if (dinfo->cfg.hdrtype != 0)
|
||||
return;
|
||||
for (i = 0; i < dinfo->cfg.nummaps; i++)
|
||||
dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
|
||||
dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
|
||||
|
||||
/*
|
||||
* Some drivers apparently write to these registers w/o
|
||||
* updating our cahced copy. No harm happens if we update the
|
||||
* copy, so do so here so we can restore them. The COMMAND
|
||||
* register is modified by the bus w/o updating the cache. This
|
||||
* should represent the normally writable portion of the 'defined'
|
||||
* part of type 0 headers. In theory we also need to save/restore
|
||||
* the PCI capability structures we know about, but apart from power
|
||||
* we don't know any that are writable.
|
||||
*/
|
||||
dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
|
||||
dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
|
||||
dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
|
||||
dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
|
||||
dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
|
||||
dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
|
||||
dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
|
||||
|
||||
/*
|
||||
* don't set the state for display devices and for memory devices
|
||||
* since bad things happen. we should (a) have drivers that can easily
|
||||
* detach and (b) use generic drivers for these devices so that some
|
||||
* device actually attaches. We need to make sure that when we
|
||||
* implement (a) we don't power the device down on a reattach.
|
||||
*
|
||||
* John and Nate also tell me that we should be running the power up
|
||||
* and power down hooks when we change power state for those nodes
|
||||
* that have ACPI hooks in the tree.
|
||||
*/
|
||||
cls = pci_get_class(dev);
|
||||
if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) {
|
||||
pci_set_powerstate(dev, PCI_POWERSTATE_D3);
|
||||
printf("pci%d:%d:%d: setting power state D3\n", dinfo->cfg.bus,
|
||||
dinfo->cfg.slot, dinfo->cfg.func);
|
||||
}
|
||||
}
|
||||
|
||||
@ -321,7 +321,7 @@ pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
}
|
||||
} else {
|
||||
ok = 1;
|
||||
#if 0
|
||||
#if 1
|
||||
if (start < sc->iobase && end > sc->iolimit) {
|
||||
start = sc->iobase;
|
||||
end = sc->iolimit;
|
||||
@ -377,7 +377,7 @@ pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
}
|
||||
} else if (!ok) {
|
||||
ok = 1; /* subtractive bridge: always ok */
|
||||
#if 0
|
||||
#if 1
|
||||
if (pcib_is_nonprefetch_open(sc)) {
|
||||
if (start < sc->membase && end > sc->memlimit) {
|
||||
start = sc->membase;
|
||||
|
||||
@ -41,6 +41,7 @@ extern devclass_t pci_devclass;
|
||||
|
||||
void pci_add_children(device_t dev, int busno, size_t dinfo_size);
|
||||
void pci_add_child(device_t bus, struct pci_devinfo *dinfo);
|
||||
void pci_driver_added(device_t dev, driver_t *driver);
|
||||
int pci_print_child(device_t dev, device_t child);
|
||||
void pci_probe_nomatch(device_t dev, device_t child);
|
||||
int pci_read_ivar(device_t dev, device_t child, int which,
|
||||
@ -74,4 +75,5 @@ int pci_child_pnpinfo_str_method(device_t cbdev, device_t child,
|
||||
char *buf, size_t buflen);
|
||||
int pci_assign_interrupt_method(device_t dev, device_t child);
|
||||
int pci_resume(device_t dev);
|
||||
int pci_suspend(device_t dev);
|
||||
#endif /* _PCI_PRIVATE_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user