Make the apb driver independent of the standard PCI bridge driver.
This commit is contained in:
Thomas Moestl
parent
7d1656b9fa
commit
caaed7acb7
@ -58,6 +58,9 @@
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* Bridge-specific data.
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*/
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struct apb_softc {
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device_t dev;
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u_int8_t secbus; /* secondary bus number */
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u_int8_t subbus; /* subordinate bus number */
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u_int8_t iomap;
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u_int8_t memmap;
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};
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@ -66,6 +69,15 @@ static int apb_probe(device_t dev);
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static int apb_attach(device_t dev);
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static struct resource *apb_alloc_resource(device_t dev, device_t child,
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int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
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static int apb_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result);
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static int apb_write_ivar(device_t dev, device_t child, int which,
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uintptr_t value);
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static int apb_maxslots(device_t dev);
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static u_int32_t apb_read_config(device_t dev, int b, int s, int f, int reg,
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int width);
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static void apb_write_config(device_t dev, int b, int s, int f, int reg,
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u_int32_t val, int width);
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static int apb_route_interrupt(device_t pcib, device_t dev, int pin);
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static device_method_t apb_methods[] = {
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@ -78,8 +90,8 @@ static device_method_t apb_methods[] = {
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, pcib_write_ivar),
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DEVMETHOD(bus_read_ivar, apb_read_ivar),
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DEVMETHOD(bus_write_ivar, apb_write_ivar),
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DEVMETHOD(bus_alloc_resource, apb_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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@ -88,9 +100,9 @@ static device_method_t apb_methods[] = {
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, pcib_read_config),
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DEVMETHOD(pcib_write_config, pcib_write_config),
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DEVMETHOD(pcib_maxslots, apb_maxslots),
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DEVMETHOD(pcib_read_config, apb_read_config),
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DEVMETHOD(pcib_write_config, apb_write_config),
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DEVMETHOD(pcib_route_interrupt, apb_route_interrupt),
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{ 0, 0 }
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@ -106,8 +118,6 @@ static devclass_t apb_devclass;
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DRIVER_MODULE(apb, pci, apb_driver, apb_devclass, 0, 0);
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#define APB_SOFTC(sc) ((struct apb_softc *)((sc)->extptr))
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/* APB specific registers */
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#define APBR_IOMAP 0xde
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#define APBR_MEMMAP 0xdf
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@ -163,41 +173,28 @@ apb_map_checkrange(u_int8_t map, u_long scale, u_long start, u_long end)
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static int
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apb_attach(device_t dev)
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{
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struct pcib_softc *sc;
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struct apb_softc *asc;
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struct apb_softc *sc;
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device_t child;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->extptr = malloc(sizeof(struct apb_softc), M_DEVBUF, M_NOWAIT);
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asc = APB_SOFTC(sc);
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/*
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* Get current bridge configuration.
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*/
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sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
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sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
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sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
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sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
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sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
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sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
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/* The APB does not implement base/limit registers. */
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sc->iobase = sc->iolimit = 0;
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sc->membase = sc->memlimit = 0;
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sc->pmembase = sc->pmemlimit = 0;
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asc->iomap = pci_read_config(dev, APBR_IOMAP, 1);
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asc->memmap = pci_read_config(dev, APBR_MEMMAP, 1);
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sc->iomap = pci_read_config(dev, APBR_IOMAP, 1);
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sc->memmap = pci_read_config(dev, APBR_MEMMAP, 1);
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if (bootverbose) {
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device_printf(dev, " secondary bus %d\n", sc->secbus);
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device_printf(dev, " subordinate bus %d\n", sc->subbus);
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device_printf(dev, " I/O decode ");
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apb_map_print(asc->iomap, APB_IO_SCALE);
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apb_map_print(sc->iomap, APB_IO_SCALE);
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printf("\n");
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device_printf(dev, " memory decode ");
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apb_map_print(asc->memmap, APB_MEM_SCALE);
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apb_map_print(sc->memmap, APB_MEM_SCALE);
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printf("\n");
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}
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@ -226,11 +223,9 @@ static struct resource *
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apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct pcib_softc *sc;
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struct apb_softc *asc;
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struct apb_softc *sc;
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sc = device_get_softc(dev);
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asc = APB_SOFTC(sc);
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/*
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* If this is a "default" allocation against this rid, we can't work
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* out where it's coming from (we should actually never see these) so we
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@ -248,7 +243,7 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
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*/
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switch (type) {
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case SYS_RES_IOPORT:
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if (!apb_map_checkrange(asc->iomap, APB_IO_SCALE, start,
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if (!apb_map_checkrange(sc->iomap, APB_IO_SCALE, start,
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end)) {
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device_printf(dev, "device %s%d requested "
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"unsupported I/O range 0x%lx-0x%lx\n",
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@ -264,7 +259,7 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
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break;
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case SYS_RES_MEMORY:
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if (!apb_map_checkrange(asc->memmap, APB_MEM_SCALE,
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if (!apb_map_checkrange(sc->memmap, APB_MEM_SCALE,
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start, end)) {
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device_printf(dev, "device %s%d requested "
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"unsupported memory range 0x%lx-0x%lx\n",
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@ -291,6 +286,63 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
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count, flags));
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}
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static int
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apb_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct apb_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = sc->secbus;
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return (0);
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}
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return (ENOENT);
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}
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static int
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apb_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct apb_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->secbus = value;
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break;
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}
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return (ENOENT);
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}
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/*
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* PCIB interface.
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*/
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static int
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apb_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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/*
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* Since we are a child of a PCI bus, its parent must support the pcib
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* interface.
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*/
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static u_int32_t
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apb_read_config(device_t dev, int b, int s, int f, int reg, int width)
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{
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return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b,
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s, f, reg, width));
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}
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static void
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apb_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val,
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int width)
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{
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PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg,
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val, width);
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}
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/*
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* Route an interrupt across a PCI bridge - the APB does not route interrupts,
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* and routing of interrupts that are not preinitialized is not supported yet.
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