riscv: improve exception code naming
The existing names were inherited from arm64, but we should prefer RISC-V terminology. Change the prefix to SCAUSE, and further change the names to better match the RISC-V spec and be more consistent with one another. Also, remove two codes that are not defined for S-mode (machine and hypervisor ecall). While here, apply style(9) to some condition checks. Reviewed by: kp Discussed with: jrtc27 Differential Revision: https://reviews.freebsd.org/D26918
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@ -41,7 +41,7 @@
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#include <machine/frame.h>
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#include <machine/trap.h>
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#define T_BREAKPOINT (EXCP_BREAKPOINT)
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#define T_BREAKPOINT (SCAUSE_BREAKPOINT)
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#define T_WATCHPOINT (0)
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typedef vm_offset_t db_addr_t;
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@ -37,23 +37,21 @@
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#ifndef _MACHINE_RISCVREG_H_
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#define _MACHINE_RISCVREG_H_
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#define EXCP_MASK (~EXCP_INTR)
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#define EXCP_MISALIGNED_FETCH 0
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#define EXCP_FAULT_FETCH 1
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#define EXCP_ILLEGAL_INSTRUCTION 2
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#define EXCP_BREAKPOINT 3
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#define EXCP_MISALIGNED_LOAD 4
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#define EXCP_FAULT_LOAD 5
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#define EXCP_MISALIGNED_STORE 6
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#define EXCP_FAULT_STORE 7
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#define EXCP_USER_ECALL 8
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#define EXCP_SUPERVISOR_ECALL 9
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#define EXCP_HYPERVISOR_ECALL 10
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#define EXCP_MACHINE_ECALL 11
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#define EXCP_INST_PAGE_FAULT 12
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#define EXCP_LOAD_PAGE_FAULT 13
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#define EXCP_STORE_PAGE_FAULT 15
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#define EXCP_INTR (1ul << 63)
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#define SCAUSE_INTR (1ul << 63)
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#define SCAUSE_CODE (~SCAUSE_INTR)
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#define SCAUSE_INST_MISALIGNED 0
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#define SCAUSE_INST_ACCESS_FAULT 1
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#define SCAUSE_ILLEGAL_INSTRUCTION 2
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#define SCAUSE_BREAKPOINT 3
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#define SCAUSE_LOAD_MISALIGNED 4
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#define SCAUSE_LOAD_ACCESS_FAULT 5
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#define SCAUSE_STORE_MISALIGNED 6
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#define SCAUSE_STORE_ACCESS_FAULT 7
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#define SCAUSE_ECALL_USER 8
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#define SCAUSE_ECALL_SUPERVISOR 9
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#define SCAUSE_INST_PAGE_FAULT 12
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#define SCAUSE_LOAD_PAGE_FAULT 13
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#define SCAUSE_STORE_PAGE_FAULT 15
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#define SSTATUS_UIE (1 << 0)
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#define SSTATUS_SIE (1 << 1)
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@ -101,12 +101,12 @@ db_stack_trace_cmd(struct unwind_state *frame)
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tf = (struct trapframe *)(uintptr_t)frame->sp;
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if (tf->tf_scause & EXCP_INTR)
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if ((tf->tf_scause & SCAUSE_INTR) != 0)
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db_printf("--- interrupt %ld\n",
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tf->tf_scause & EXCP_MASK);
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tf->tf_scause & SCAUSE_CODE);
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else
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db_printf("--- exception %ld, tval = %#lx\n",
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tf->tf_scause & EXCP_MASK,
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tf->tf_scause & SCAUSE_CODE,
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tf->tf_stval);
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frame->sp = tf->tf_sp;
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frame->fp = tf->tf_s[0];
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@ -158,10 +158,10 @@ riscv_cpu_intr(struct trapframe *frame)
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struct intr_irqsrc *isrc;
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int active_irq;
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KASSERT(frame->tf_scause & EXCP_INTR,
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KASSERT((frame->tf_scause & SCAUSE_INTR) != 0,
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("riscv_cpu_intr: wrong frame passed"));
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active_irq = frame->tf_scause & EXCP_MASK;
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active_irq = frame->tf_scause & SCAUSE_CODE;
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switch (active_irq) {
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case IRQ_SOFTWARE_USER:
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@ -217,9 +217,9 @@ page_fault_handler(struct trapframe *frame, int usermode)
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va = trunc_page(stval);
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if (frame->tf_scause == EXCP_STORE_PAGE_FAULT) {
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if (frame->tf_scause == SCAUSE_STORE_PAGE_FAULT) {
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ftype = VM_PROT_WRITE;
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} else if (frame->tf_scause == EXCP_INST_PAGE_FAULT) {
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} else if (frame->tf_scause == SCAUSE_INST_PAGE_FAULT) {
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ftype = VM_PROT_EXECUTE;
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} else {
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ftype = VM_PROT_READ;
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@ -232,7 +232,7 @@ page_fault_handler(struct trapframe *frame, int usermode)
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if (error != KERN_SUCCESS) {
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if (usermode) {
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call_trapsignal(td, sig, ucode, (void *)stval,
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frame->tf_scause & EXCP_MASK);
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frame->tf_scause & SCAUSE_CODE);
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} else {
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if (pcb->pcb_onfault != 0) {
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frame->tf_a[0] = error;
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@ -262,8 +262,8 @@ do_trap_supervisor(struct trapframe *frame)
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KASSERT((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) ==
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SSTATUS_SPP, ("Came from S mode with interrupts enabled"));
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exception = frame->tf_scause & EXCP_MASK;
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if (frame->tf_scause & EXCP_INTR) {
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exception = frame->tf_scause & SCAUSE_CODE;
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if ((frame->tf_scause & SCAUSE_INTR) != 0) {
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/* Interrupt */
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riscv_cpu_intr(frame);
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return;
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@ -278,18 +278,18 @@ do_trap_supervisor(struct trapframe *frame)
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curthread, frame->tf_sepc, frame);
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switch (exception) {
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case EXCP_FAULT_LOAD:
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case EXCP_FAULT_STORE:
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case EXCP_FAULT_FETCH:
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case SCAUSE_LOAD_ACCESS_FAULT:
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case SCAUSE_STORE_ACCESS_FAULT:
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case SCAUSE_INST_ACCESS_FAULT:
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dump_regs(frame);
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panic("Memory access exception at 0x%016lx\n", frame->tf_sepc);
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break;
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case EXCP_STORE_PAGE_FAULT:
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case EXCP_LOAD_PAGE_FAULT:
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case EXCP_INST_PAGE_FAULT:
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case SCAUSE_STORE_PAGE_FAULT:
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case SCAUSE_LOAD_PAGE_FAULT:
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case SCAUSE_INST_PAGE_FAULT:
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page_fault_handler(frame, 0);
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break;
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case EXCP_BREAKPOINT:
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case SCAUSE_BREAKPOINT:
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#ifdef KDTRACE_HOOKS
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if (dtrace_invop_jump_addr != NULL &&
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dtrace_invop_jump_addr(frame) == 0)
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@ -302,7 +302,7 @@ do_trap_supervisor(struct trapframe *frame)
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panic("No debugger in kernel.\n");
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#endif
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break;
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case EXCP_ILLEGAL_INSTRUCTION:
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case SCAUSE_ILLEGAL_INSTRUCTION:
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dump_regs(frame);
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panic("Illegal instruction at 0x%016lx\n", frame->tf_sepc);
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break;
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@ -330,8 +330,8 @@ do_trap_user(struct trapframe *frame)
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KASSERT((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == 0,
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("Came from U mode with interrupts enabled"));
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exception = frame->tf_scause & EXCP_MASK;
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if (frame->tf_scause & EXCP_INTR) {
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exception = frame->tf_scause & SCAUSE_CODE;
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if ((frame->tf_scause & SCAUSE_INTR) != 0) {
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/* Interrupt */
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riscv_cpu_intr(frame);
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return;
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@ -342,23 +342,23 @@ do_trap_user(struct trapframe *frame)
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curthread, frame->tf_sepc, frame);
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switch (exception) {
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case EXCP_FAULT_LOAD:
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case EXCP_FAULT_STORE:
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case EXCP_FAULT_FETCH:
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case SCAUSE_LOAD_ACCESS_FAULT:
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case SCAUSE_STORE_ACCESS_FAULT:
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case SCAUSE_INST_ACCESS_FAULT:
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call_trapsignal(td, SIGBUS, BUS_ADRERR, (void *)frame->tf_sepc,
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exception);
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userret(td, frame);
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break;
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case EXCP_STORE_PAGE_FAULT:
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case EXCP_LOAD_PAGE_FAULT:
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case EXCP_INST_PAGE_FAULT:
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case SCAUSE_STORE_PAGE_FAULT:
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case SCAUSE_LOAD_PAGE_FAULT:
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case SCAUSE_INST_PAGE_FAULT:
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page_fault_handler(frame, 1);
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break;
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case EXCP_USER_ECALL:
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case SCAUSE_ECALL_USER:
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frame->tf_sepc += 4; /* Next instruction */
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ecall_handler();
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break;
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case EXCP_ILLEGAL_INSTRUCTION:
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case SCAUSE_ILLEGAL_INSTRUCTION:
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#ifdef FPE
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if ((pcb->pcb_fpflags & PCB_FP_STARTED) == 0) {
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/*
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@ -376,7 +376,7 @@ do_trap_user(struct trapframe *frame)
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exception);
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userret(td, frame);
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break;
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case EXCP_BREAKPOINT:
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case SCAUSE_BREAKPOINT:
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call_trapsignal(td, SIGTRAP, TRAP_BRKPT, (void *)frame->tf_sepc,
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exception);
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userret(td, frame);
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