arm64: rockchip: Add gpio controller driver
Add a driver that match on 'rockchip,gpio-bank', this compatible string is found on almost all RockChip SoC so this driver is compatible with almost all of the RockChip SoCs. The only features missing for this driver are : - Interrupts support - Debouncing
This commit is contained in:
Emmanuel Vadot
parent
803a230592
commit
cbf65cf228
@ -444,6 +444,7 @@ MAN= aac.4 \
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re.4 \
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rgephy.4 \
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rights.4 \
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${_rk_gpio.4} \
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${_rk_grf.4} \
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${_rk_pinctrl.4} \
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rl.4 \
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@ -767,6 +768,7 @@ MLINKS+=xl.4 if_xl.4
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.if ${MACHINE_CPUARCH} == "aarch64"
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_armv8crypto.4= armv8crypto.4
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_rk_gpio.4= rk_gpio.4
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_rk_grf.4= rk_grf.4
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_rk_pinctrl.4= rk_pinctrl.4
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.endif
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63
share/man/man4/rk_gpio.4
Normal file
63
share/man/man4/rk_gpio.4
Normal file
@ -0,0 +1,63 @@
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.\"-
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.\" Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd Apr 26, 2018
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.Dt RK_GPIO 4
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.Os
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.Sh NAME
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.Nm rk_gpio
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.Nd driver for the gpio controller on RockChip SoCs
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.Sh SYNOPSIS
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.Cd "options SOC_ROCKCHIP_RK3328"
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.Sh DESCRIPTION
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The
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.Nm
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device driver provides support for the gpio controller device present
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on RockChip SoC.
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.Sh HARDWARE
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The current version of the
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.Nm
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driver supports the gpio banks with one of the following
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compatible strings :
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.Pp
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.Bl -bullet -compact
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.It
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rockchip,gpio-bank
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.El
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.Sh SEE ALSO
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.Xr gpiobus 4 ,
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.Xr gpioctl 8 ,
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 12.0 .
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.Sh AUTHORS
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The
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.Nm
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device driver and manpage was written by
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.An Emmanuel Vadot Aq Mt manu@freebsd.org .
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426
sys/arm64/rockchip/rk_gpio.c
Normal file
426
sys/arm64/rockchip/rk_gpio.c
Normal file
@ -0,0 +1,426 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include "opt_soc.h"
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#include "gpio_if.h"
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#define RK_GPIO_SWPORTA_DR 0x00 /* Data register */
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#define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */
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#define RK_GPIO_INTEN 0x30 /* Interrupt enable register */
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#define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */
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#define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */
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#define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */
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#define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */
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#define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */
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#define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */
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#define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */
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#define RK_GPIO_EXT_PORTA 0x50 /* External port register */
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#define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
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struct rk_gpio_softc {
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device_t sc_dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource *sc_res[2];
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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clk_t clk;
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};
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,gpio-bank", 1},
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{NULL, 0}
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};
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static struct resource_spec rk_gpio_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int rk_gpio_detach(device_t dev);
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#define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define RK_GPIO_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
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#define RK_GPIO_READ(_sc, _off) \
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bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
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static int
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rk_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "RockChip GPIO Bank controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_gpio_attach(device_t dev)
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{
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struct rk_gpio_softc *sc;
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phandle_t node;
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int err;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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node = ofw_bus_get_node(sc->sc_dev);
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if (!OF_hasprop(node, "gpio-controller"))
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return (ENXIO);
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mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
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if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
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device_printf(dev, "could not allocate resources\n");
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bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
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mtx_destroy(&sc->sc_mtx);
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
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if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
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device_printf(dev, "Cannot get clock\n");
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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err = clk_enable(sc->clk);
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if (err != 0) {
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device_printf(dev, "Could not enable clock %s\n",
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clk_get_name(sc->clk));
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL) {
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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return (0);
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}
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static int
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rk_gpio_detach(device_t dev)
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{
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struct rk_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (sc->sc_busdev)
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gpiobus_detach_bus(dev);
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bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
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mtx_destroy(&sc->sc_mtx);
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clk_disable(sc->clk);
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return(0);
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}
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static device_t
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rk_gpio_get_bus(device_t dev)
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{
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struct rk_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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rk_gpio_pin_max(device_t dev, int *maxpin)
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{
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/* Each bank have always 32 pins */
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*maxpin = 32;
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return (0);
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}
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static int
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rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct rk_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= 32)
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return (EINVAL);
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RK_GPIO_LOCK(sc);
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snprintf(name, GPIOMAXNAME, "gpio%d", pin);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
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RK_GPIO_UNLOCK(sc);
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if (reg & (1 << pin))
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*flags = GPIO_PIN_OUTPUT;
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else
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*flags = GPIO_PIN_INPUT;
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return (0);
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}
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static int
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rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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/* Caps are managed by the pinctrl device */
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*caps = 0;
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return (0);
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}
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static int
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rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
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if (flags & GPIO_PIN_INPUT)
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reg &= ~(1 << pin);
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else if (flags & GPIO_PIN_OUTPUT)
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reg |= (1 << pin);
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RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
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RK_GPIO_UNLOCK(sc);
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*val = reg & (1 << pin) ? 1 : 0;
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return (0);
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}
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static int
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rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
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if (value)
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reg |= (1 << pin);
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else
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reg &= ~(1 << pin);
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RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
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if (reg & (1 << pin))
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reg &= ~(1 << pin);
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else
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reg |= (1 << pin);
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RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
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uint32_t change_pins, uint32_t *orig_pins)
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{
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struct rk_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
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if (orig_pins)
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*orig_pins = reg;
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if ((clear_pins | change_pins) != 0) {
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reg = (reg & ~clear_pins) ^ change_pins;
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RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
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}
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
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uint32_t *pin_flags)
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{
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uint32_t reg, set, mask, flask;
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int i;
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if (first_pin != 0 || num_pins > 32)
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return (EINVAL);
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set = 0;
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mask = 0;
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for (i = 0; i < num_pins; i++) {
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mask = (mask << 1) | 1;
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flags = pin_flags[i];
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if (flags & GPIO_PIN_INPUT) {
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set &= ~(1 << i);
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} else if (flags & GPIO_PIN_OUTPUT) {
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set |= (1 << i);
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}
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}
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RK_GPIO_LOCK(sc);
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reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
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reg &= ~mask;
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reg |= set;
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RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
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pcell_t *gpios, uint32_t *pin, uint32_t *flags)
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{
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/* The gpios are mapped as <gpio-phandle pin flags> */
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*pin = gpios[1];
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*flags = gpios[2];
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return (0);
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}
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static device_method_t rk_gpio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rk_gpio_probe),
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DEVMETHOD(device_attach, rk_gpio_attach),
|
||||
DEVMETHOD(device_detach, rk_gpio_detach),
|
||||
|
||||
/* GPIO protocol */
|
||||
DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
|
||||
DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
|
||||
DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
|
||||
DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
|
||||
DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
|
||||
DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
|
||||
DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
|
||||
DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
|
||||
DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
|
||||
DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
|
||||
DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
|
||||
DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t rk_gpio_driver = {
|
||||
"gpio",
|
||||
rk_gpio_methods,
|
||||
sizeof(struct rk_gpio_softc),
|
||||
};
|
||||
|
||||
static devclass_t rk_gpio_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver,
|
||||
rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
||||
@ -244,6 +244,7 @@ cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "
|
||||
|
||||
arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328
|
||||
arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328
|
||||
arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328
|
||||
arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328
|
||||
arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328
|
||||
arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328
|
||||
|
||||
Loading…
Reference in New Issue
Block a user