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Implement cpu_flush_dcache(). This allows us to optimize __syncicache()

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for the common case in chich D-caches are coherent by virtue of busdma.
This commit is contained in:
marcel 2012-07-02 21:11:01 +00:00
parent 53224f018a
commit ce5683d3c5
1 changed files with 18 additions and 1 deletions
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19
sys/powerpc/booke/machdep.c
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@ -473,7 +473,24 @@ cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
void
cpu_flush_dcache(void *ptr, size_t len)
{
/* TBD */
register_t addr, off;
/*
* Align the address to a cacheline and adjust the length
* accordingly. Then round the length to a multiple of the
* cacheline for easy looping.
*/
addr = (uintptr_t)ptr;
off = addr & (cacheline_size - 1);
addr -= off;
len = (len + off + cacheline_size - 1) & ~(cacheline_size - 1);
while (len > 0) {
__asm __volatile ("dcbf 0,%0" :: "r"(addr));
__asm __volatile ("sync");
addr += cacheline_size;
len -= cacheline_size;
}
}
void