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powerpc/booke: Depessimize MAS register updates even more

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Remove isyncs between MAS register updates in the TLB miss handler, since
it's only needed before the TLB update instructions.
This commit is contained in:
jhibbits 2019-03-02 20:59:18 +00:00
parent a7b0a05518
commit ce8811681f
2 changed files with 5 additions and 11 deletions
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5
sys/powerpc/booke/locore.S
View File

@ -252,6 +252,7 @@ __start:
isync
bl zero_mas7
bl zero_mas8
isync
tlbwe
isync
msync
@ -505,6 +506,7 @@ bp_kernload:
isync
bl zero_mas7
bl zero_mas8
isync
tlbwe
isync
msync
@ -695,6 +697,7 @@ tlb1_temp_mapping_as1:
bl zero_mas7
bl zero_mas8
mtlr %r3
isync
tlbwe
isync
msync
@ -742,7 +745,6 @@ zero_mas7:
li %r20, 0
mtspr SPR_MAS7, %r20
isync
1:
blr
@ -759,7 +761,6 @@ zero_mas8:
1:
li %r20, 0
mtspr SPR_MAS8, %r20
isync
blr
#endif

11
sys/powerpc/booke/trap_subr.S
View File

@ -761,17 +761,14 @@ search_failed:
/* Load MAS registers. */
mtspr SPR_MAS0, %r29
isync
mtspr SPR_MAS1, %r28
isync
mtspr SPR_MAS2, %r27
isync
mtspr SPR_MAS3, %r23
isync
bl zero_mas7
bl zero_mas8
isync
tlbwe
msync
isync
@ -906,20 +903,16 @@ tlb_fill_entry:
/* Load MAS registers. */
mtspr SPR_MAS0, %r29
isync
mtspr SPR_MAS1, %r28
isync
mtspr SPR_MAS2, %r27
isync
mtspr SPR_MAS3, %r22
isync
mtspr SPR_MAS7, %r23
isync
mflr %r21
bl zero_mas8
mtlr %r21
isync
tlbwe
isync
msync