MFp4: Make it work :-)
o Don't delay when checking the done bits. There's no gain other than a small performance hit. o calculate the clock divisors better (things are still way slow, so maybe there's more here?) o don't always fail reset. Always succeed instead. o fix inverted logic around at91_twi_wait() return value o remove debug code o remove unneeded, unworking junk
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@ -227,133 +227,15 @@ static int
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at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit)
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{
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int err = 0;
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int counter = 10000;
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int counter = 100000;
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while (!(RD4(sc, TWI_SR) & bit) && counter-- >= 0)
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DELAY(10);
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continue;
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if (counter <= 0)
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err = EIO;
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return (err);
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}
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/*
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* Stop the transfer by entering a STOP state on the iic bus. For read
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* operations, we've already entered the STOP state, since we need to do
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* that to read the last character. For write operations, we need to
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* wait for the TXCOMP bit to turn on before returning.
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*/
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static int
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at91_twi_stop(device_t dev)
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{
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struct at91_twi_softc *sc;
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int err = 0;
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sc = device_get_softc(dev);
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if (sc->sc_started) {
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WR4(sc, TWI_CR, TWI_CR_STOP);
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err = at91_twi_wait(sc, TWI_SR_TXCOMP);
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}
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return (err);
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}
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/*
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* enter a START condition without requiring the device to be in a STOP
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* state.
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*/
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static int
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at91_twi_repeated_start(device_t dev, u_char slave, int timeout)
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{
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struct at91_twi_softc *sc;
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sc = device_get_softc(dev);
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WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
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return (0);
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}
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/*
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* enter a START condition from an idle state.
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*/
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static int
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at91_twi_start(device_t dev, u_char slave, int timeout)
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{
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struct at91_twi_softc *sc;
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sc = device_get_softc(dev);
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WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
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sc->sc_started = 1;
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return (0);
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}
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static int
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at91_twi_write(device_t dev, char *buf, int len, int *sent, int timeout /* us */)
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{
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struct at91_twi_softc *sc;
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uint8_t *walker;
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int err = 0;
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walker = buf;
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sc = device_get_softc(dev);
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AT91_TWI_LOCK(sc);
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WR4(sc, TWI_MMR, ~TWI_MMR_MREAD & RD4(sc, TWI_MMR));
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WR4(sc, TWI_CR, TWI_CR_START);
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sc->sc_started = 1;
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// WR4(sc, TWI_IER, TWI_SR_TXRDY);
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while (len--) {
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WR4(sc, TWI_THR, *walker++);
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while (!(sc->flags & TXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr",
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0);
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if (err)
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goto errout;
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}
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}
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errout:;
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WR4(sc, TWI_IDR, TWI_SR_TXRDY);
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AT91_TWI_UNLOCK(sc);
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return (err);
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}
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static int
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at91_twi_read(device_t dev, char *buf, int len, int *read, int last,
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int delay /* us */)
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{
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struct at91_twi_softc *sc;
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char *walker;
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int err = 0;
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walker = buf;
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sc = device_get_softc(dev);
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AT91_TWI_LOCK(sc);
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WR4(sc, TWI_MMR, TWI_MMR_MREAD | RD4(sc, TWI_MMR));
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WR4(sc, TWI_CR, TWI_CR_START);
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sc->sc_started = 1;
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// WR4(sc, TWI_IER, TWI_SR_RXRDY);
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while (len-- > 0) {
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err = 0;
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while (!(sc->flags & RXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
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0);
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if (err)
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goto errout;
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}
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sc->flags &= ~RXRDY;
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*walker++ = RD4(sc, TWI_RHR) & 0xff;
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if (len == 1 && last)
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break;
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}
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if (!last)
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goto errout;
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WR4(sc, TWI_CR, TWI_CR_STOP);
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err = at91_twi_wait(sc, TWI_SR_TXCOMP);
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*walker = RD4(sc, TWI_RHR) & 0xff;
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if (read)
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*read = walker - buf;
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errout:;
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WR4(sc, TWI_IDR, TWI_SR_RXRDY);
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AT91_TWI_UNLOCK(sc);
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return (err);
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}
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static int
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at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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@ -371,22 +253,21 @@ at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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rate = 1;
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/*
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* 8 * is because "rate == 1" -> 4 clocks down, 4 clocks up. The
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* speeds are for 1.5kb/s, 45kb/s and 90kb/s.
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*/
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switch (speed) {
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case IIC_SLOW:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 1500;
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ckdiv = AT91C_MASTER_CLOCK / (1500 * 4) - 2;
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break;
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case IIC_FAST:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 45000;
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ckdiv = AT91C_MASTER_CLOCK / (45000 * 4) - 2;
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break;
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 90000;
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ckdiv = AT91C_MASTER_CLOCK / (90000 * 4) - 2;
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break;
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}
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@ -396,7 +277,7 @@ at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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return EIO;
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return 0;
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}
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static int
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@ -446,10 +327,8 @@ at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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while (len--) {
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if (len == 0)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if (!at91_twi_wait(sc, TWI_SR_RXRDY)) {
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printf("1\n");
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if (at91_twi_wait(sc, TWI_SR_RXRDY))
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return (EIO);
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}
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*buf++ = RD4(sc, TWI_RHR) & 0xff;
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}
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} else {
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@ -457,16 +336,12 @@ at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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WR4(sc, TWI_THR, *buf++);
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if (len == 0)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if (!at91_twi_wait(sc, TWI_SR_TXRDY)) {
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printf("3\n");
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if (at91_twi_wait(sc, TWI_SR_TXRDY))
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return (EIO);
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}
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}
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}
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if (!at91_twi_wait(sc, TWI_SR_TXCOMP)) {
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printf("2\n");
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if (at91_twi_wait(sc, TWI_SR_TXCOMP))
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return (EIO);
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}
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}
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return (0);
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}
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@ -479,11 +354,6 @@ static device_method_t at91_twi_methods[] = {
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/* iicbus interface */
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DEVMETHOD(iicbus_callback, at91_twi_callback),
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DEVMETHOD(iicbus_repeated_start, at91_twi_repeated_start),
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DEVMETHOD(iicbus_start, at91_twi_start),
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DEVMETHOD(iicbus_stop, at91_twi_stop),
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DEVMETHOD(iicbus_write, at91_twi_write),
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DEVMETHOD(iicbus_read, at91_twi_read),
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DEVMETHOD(iicbus_reset, at91_twi_rst_card),
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DEVMETHOD(iicbus_transfer, at91_twi_transfer),
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{ 0, 0 }
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