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- Even after masking the media with IFM_GMASK the result may have bits

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besides the duplex ones set so just comparing it with IFM_FDX may lead
  to false negatives.
- Simplify ciphy_service() to only set the manual configuration bits
  once after we have figured them all out. This also means we no longer
  unnecessarily update the hardware along the road.

MFC after:	1 week
This commit is contained in:
marius 2011-01-14 19:29:53 +00:00
parent 0ea473c75d
commit cfca51bb67
3 changed files with 13 additions and 16 deletions
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2
sys/dev/mii/brgphy.c
View File

@ -453,7 +453,7 @@ brgphy_setmedia(struct mii_softc *sc, int media)
break;
}
if ((media & IFM_GMASK) == IFM_FDX) {
if ((media & IFM_FDX) != 0) {
bmcr |= BRGPHY_BMCR_FDX;
gig = BRGPHY_1000CTL_AFD;
} else {

25
sys/dev/mii/ciphy.c
View File

@ -176,26 +176,23 @@ ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
case IFM_10_T:
speed = CIPHY_S10;
setit:
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
if ((ife->ifm_media & IFM_FDX) != 0) {
speed |= CIPHY_BMCR_FDX;
gig = CIPHY_1000CTL_AFD;
} else {
} else
gig = CIPHY_1000CTL_AHD;
}
PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
gig |= CIPHY_1000CTL_MSE;
if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
gig |= CIPHY_1000CTL_MSC;
speed |=
CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
} else
gig = 0;
PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
break;
gig |= CIPHY_1000CTL_MSE;
if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
gig |= CIPHY_1000CTL_MSC;
PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
PHY_WRITE(sc, CIPHY_MII_BMCR,
speed | CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG);
break;
case IFM_NONE:
PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);

2
sys/dev/mii/xmphy.c
View File

@ -171,7 +171,7 @@ xmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
break;
case IFM_1000_SX:
mii_phy_reset(sc);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
if ((ife->ifm_media & IFM_FDX) != 0) {
PHY_WRITE(sc, XMPHY_MII_ANAR, XMPHY_ANAR_FDX);
PHY_WRITE(sc, XMPHY_MII_BMCR, XMPHY_BMCR_FDX);
} else {