If an interrupt on an I/O APIC is moved to a different CPU after it has
started to execute, it seems that the corresponding ISR bit in the "old" local APIC can be cleared. This causes the local APIC interrupt routine to fail to find an interrupt to service. Rather than panic'ing in this case, simply return from the interrupt without sending an EOI to the local APIC. If there are any other pending interrupts in other ISR registers, the local APIC will assert a new interrupt. Tested by: steve
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@ -58,17 +58,15 @@ IDTVEC(vec_name) ; \
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FAKE_MCOUNT(TF_RIP(%rsp)) ; \
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movq lapic, %rdx ; /* pointer to local APIC */ \
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movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \
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bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
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jz 2f ; \
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bsrl %eax, %eax ; /* index of highest set bit in ISR */ \
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jz 1f ; \
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addl $(32 * index),%eax ; \
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1: ; \
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movq %rsp, %rsi ; \
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movl %eax, %edi ; /* pass the IRQ */ \
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call lapic_handle_intr ; \
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1: ; \
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MEXITCOUNT ; \
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jmp doreti ; \
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2: movl $-1, %eax ; /* send a vector of -1 */ \
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jmp 1b
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jmp doreti
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/*
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* Handle "spurious INTerrupts".
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@ -60,18 +60,16 @@ IDTVEC(vec_name) ; \
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FAKE_MCOUNT(TF_EIP(%esp)) ; \
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movl lapic, %edx ; /* pointer to local APIC */ \
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movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \
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bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
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jz 2f ; \
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bsrl %eax, %eax ; /* index of highest set bit in ISR */ \
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jz 1f ; \
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addl $(32 * index),%eax ; \
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1: ; \
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pushl %esp ; \
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pushl %eax ; /* pass the IRQ */ \
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call lapic_handle_intr ; \
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addl $8, %esp ; /* discard parameter */ \
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1: ; \
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MEXITCOUNT ; \
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jmp doreti ; \
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2: movl $-1, %eax ; /* send a vector of -1 */ \
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jmp 1b
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jmp doreti
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/*
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* Handle "spurious INTerrupts".
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@ -780,8 +780,6 @@ lapic_handle_intr(int vector, struct trapframe *frame)
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{
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struct intsrc *isrc;
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if (vector == -1)
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panic("Couldn't get vector from ISR!");
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isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
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vector));
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intr_execute_handlers(isrc, frame);
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