rockchip: add audio-related clocks to the CRU driver
- Add I2S and CODEC clocks to CRU driver - Add support for gate selection to frac clock - Add setfreq support to mux clock Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D27831
This commit is contained in:
Oleksandr Tymoshenko
parent
52981a1694
commit
d03fd8ede2
@ -56,6 +56,11 @@ __FBSDID("$FreeBSD$");
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/* GATES */
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#define SCLK_I2S0 41
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#define SCLK_I2S1 42
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#define SCLK_I2S2 43
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#define SCLK_I2S1_OUT 44
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#define SCLK_I2S2_OUT 45
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#define SCLK_MAC2PHY_RXTX 83
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#define SCLK_MAC2PHY_SRC 84
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#define SCLK_MAC2PHY_REF 85
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@ -90,6 +95,10 @@ __FBSDID("$FreeBSD$");
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#define PCLK_USB3PHY_OTG 224
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#define PCLK_USB3PHY_PIPE 225
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#define PCLK_USB3_GRF 226
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#define PCLK_ACODECPHY 235
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#define HCLK_I2S0_8CH 311
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#define HCLK_I2S1_8CH 312
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#define HCLK_I2S2_2CH 313
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#define HCLK_SDMMC 317
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#define HCLK_SDIO 318
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#define HCLK_EMMC 319
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@ -102,6 +111,11 @@ static struct rk_cru_gate rk3328_gates[] = {
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CRU_GATE(0, "gpll_core", "gpll", 0x200, 2)
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CRU_GATE(0, "npll_core", "npll", 0x200, 12)
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/* CRU_CLKGATE_CON1 */
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CRU_GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 0x204, 3)
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CRU_GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 0x204, 6)
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CRU_GATE(SCLK_I2S1, "clk_i2s2", "clk_i2s2_mux", 0x204, 10)
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/* CRU_CLKGATE_CON4 */
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CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0)
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CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1)
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@ -123,6 +137,9 @@ static struct rk_cru_gate rk3328_gates[] = {
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CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0)
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/* CRU_CLKGATE_CON15*/
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CRU_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0x23C, 3)
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CRU_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0x23C, 4)
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CRU_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0x23C, 5)
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CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10)
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/* CRU_CLKGATE_CON16 */
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@ -138,6 +155,7 @@ static struct rk_cru_gate rk3328_gates[] = {
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/* CRU_CLKGATE_CON17 */
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CRU_GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", 0x244, 2)
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CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0x244, 5)
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/* CRU_CLKGATE_CON19 */
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CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0)
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@ -1115,6 +1133,215 @@ static struct rk_clk_composite_def ref_usb3otg_src = {
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/* I2S0 */
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static const char *i2s0_div_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def i2s0_div = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s0_div",
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.parent_names = i2s0_div_parents,
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.parent_cnt = nitems(i2s0_div_parents),
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},
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/* CRU_CLKSEL_CON6 */
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.muxdiv_offset = 0x118,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 0,
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.div_width = 7,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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static const char *i2s0_frac_parents[] = { "clk_i2s0_div" };
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static struct rk_clk_fract_def i2s0_frac = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s0_frac",
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.parent_names = i2s0_frac_parents,
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.parent_cnt = nitems(i2s0_frac_parents),
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},
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/* CRU_CLKSEL_CON7 */
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.offset = 0x11c,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 2,
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.flags = RK_CLK_FRACT_HAVE_GATE,
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};
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static const char *i2s0_mux_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" };
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static struct rk_clk_mux_def i2s0_mux = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s0_mux",
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.parent_names = i2s0_mux_parents,
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.parent_cnt = nitems(i2s0_mux_parents),
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},
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.offset = 0x118,
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.shift = 8,
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.width = 2,
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.mux_flags = RK_CLK_MUX_REPARENT,
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};
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/* I2S1 */
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static const char *i2s1_div_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def i2s1_div = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s1_div",
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.parent_names = i2s1_div_parents,
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.parent_cnt = nitems(i2s1_div_parents),
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},
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/* CRU_CLKSEL_CON8 */
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.muxdiv_offset = 0x120,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 0,
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.div_width = 7,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 4,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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static const char *i2s1_frac_parents[] = { "clk_i2s1_div" };
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static struct rk_clk_fract_def i2s1_frac = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s1_frac",
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.parent_names = i2s1_frac_parents,
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.parent_cnt = nitems(i2s1_frac_parents),
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},
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/* CRU_CLKSEL_CON9 */
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.offset = 0x124,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 5,
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.flags = RK_CLK_FRACT_HAVE_GATE,
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};
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static const char *i2s1_mux_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" };
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static struct rk_clk_mux_def i2s1_mux = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s1_mux",
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.parent_names = i2s1_mux_parents,
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.parent_cnt = nitems(i2s1_mux_parents),
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},
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.offset = 0x120,
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.shift = 8,
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.width = 2,
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.mux_flags = RK_CLK_MUX_REPARENT,
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};
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static struct clk_fixed_def clkin_i2s1 = {
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.clkdef = {
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.id = 0,
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.name = "clkin_i2s1",
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.parent_names = NULL,
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.parent_cnt = 0
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},
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.freq = 0,
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};
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/* I2S2 */
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static const char *i2s2_div_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def i2s2_div = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s2_div",
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.parent_names = i2s2_div_parents,
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.parent_cnt = nitems(i2s2_div_parents),
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},
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/* CRU_CLKSEL_CON10 */
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.muxdiv_offset = 0x128,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 0,
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.div_width = 7,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 8,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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static const char *i2s2_frac_parents[] = { "clk_i2s2_div" };
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static struct rk_clk_fract_def i2s2_frac = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s2_frac",
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.parent_names = i2s2_frac_parents,
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.parent_cnt = nitems(i2s2_frac_parents),
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},
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/* CRU_CLKSEL_CON11 */
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.offset = 0x12c,
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/* CRU_CLKGATE_CON1 */
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.gate_offset = 0x204,
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.gate_shift = 9,
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.flags = RK_CLK_FRACT_HAVE_GATE,
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};
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static const char *i2s2_mux_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" };
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static struct rk_clk_mux_def i2s2_mux = {
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.clkdef = {
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.id = 0,
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.name = "clk_i2s2_mux",
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.parent_names = i2s2_mux_parents,
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.parent_cnt = nitems(i2s2_mux_parents),
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},
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.offset = 0x128,
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.shift = 8,
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.width = 2,
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.mux_flags = RK_CLK_MUX_REPARENT,
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};
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static struct clk_fixed_def clkin_i2s2 = {
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.clkdef = {
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.id = 0,
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.name = "clkin_i2s2",
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.parent_names = NULL,
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.parent_cnt = 0
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},
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.freq = 0,
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};
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static struct clk_fixed_def xin12m = {
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.clkdef = {
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.id = 0,
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.name = "xin12m",
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.parent_names = NULL,
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.parent_cnt = 0
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},
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.freq = 12000000,
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};
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static const char *mac2io_src_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def mac2io_src = {
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@ -1417,6 +1644,54 @@ static struct rk_clk rk3328_clks[] = {
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &usb3otg_suspend
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &i2s0_div
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},
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{
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.type = RK_CLK_FRACT,
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.clk.fract = &i2s0_frac
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},
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{
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.type = RK_CLK_MUX,
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.clk.mux = &i2s0_mux
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &i2s1_div
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},
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{
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.type = RK_CLK_FRACT,
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.clk.fract = &i2s1_frac
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},
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{
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.type = RK_CLK_MUX,
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.clk.mux = &i2s1_mux
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},
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{
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.type = RK_CLK_FIXED,
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.clk.fixed = &clkin_i2s1
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &i2s2_div
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},
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{
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.type = RK_CLK_FRACT,
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.clk.fract = &i2s2_frac
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},
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{
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.type = RK_CLK_MUX,
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.clk.mux = &i2s2_mux
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},
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{
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.type = RK_CLK_FIXED,
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.clk.fixed = &clkin_i2s2
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},
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{
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.type = RK_CLK_FIXED,
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.clk.fixed = &xin12m
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2io_src
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@ -964,19 +964,19 @@ static struct rk_clk rk3399_clks[] = {
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27, 0, 10, 15, 1),
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/* CRU_CLKSEL_CON28 */
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MUX(0, "clk_i2s0_mux", i2s0_p, 0,
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MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
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28, 8, 2),
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COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
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28, 0, 7, 7, 1),
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/* CRU_CLKSEL_CON29 */
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MUX(0, "clk_i2s1_mux", i2s1_p, 0,
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MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
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29, 8, 2),
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COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
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29, 0, 7, 7, 1),
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/* CRU_CLKSEL_CON30 */
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MUX(0, "clk_i2s2_mux", i2s2_p, 0,
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MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
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30, 8, 2),
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COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
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30, 0, 7, 7, 1),
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@ -49,21 +49,27 @@ __FBSDID("$FreeBSD$");
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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#define RK_CLK_FRACT_MASK_SHIFT 16
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static int rk_clk_fract_init(struct clknode *clk, device_t dev);
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static int rk_clk_fract_recalc(struct clknode *clk, uint64_t *req);
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static int rk_clk_fract_set_freq(struct clknode *clknode, uint64_t fin,
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uint64_t *fout, int flag, int *stop);
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static int rk_clk_fract_set_gate(struct clknode *clk, bool enable);
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struct rk_clk_fract_sc {
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uint32_t flags;
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uint32_t offset;
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uint32_t numerator;
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uint32_t denominator;
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uint32_t gate_offset;
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uint32_t gate_shift;
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};
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static clknode_method_t rk_clk_fract_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, rk_clk_fract_init),
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CLKNODEMETHOD(clknode_set_gate, rk_clk_fract_set_gate),
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CLKNODEMETHOD(clknode_recalc_freq, rk_clk_fract_recalc),
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CLKNODEMETHOD(clknode_set_freq, rk_clk_fract_set_freq),
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CLKNODEMETHOD_END
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@ -149,6 +155,33 @@ rk_clk_fract_init(struct clknode *clk, device_t dev)
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return(0);
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}
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static int
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rk_clk_fract_set_gate(struct clknode *clk, bool enable)
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{
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struct rk_clk_fract_sc *sc;
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uint32_t val = 0;
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sc = clknode_get_softc(clk);
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if ((sc->flags & RK_CLK_FRACT_HAVE_GATE) == 0)
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return (0);
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RD4(clk, sc->gate_offset, &val);
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val = 0;
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if (!enable)
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val |= 1 << sc->gate_shift;
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val |= (1 << sc->gate_shift) << RK_CLK_FRACT_MASK_SHIFT;
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DEVICE_LOCK(clk);
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WR4(clk, sc->gate_offset, val);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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static int
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rk_clk_fract_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
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int flags, int *stop);
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static int
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rk_clk_fract_recalc(struct clknode *clk, uint64_t *freq)
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{
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@ -240,6 +273,8 @@ rk_clk_fract_register(struct clkdom *clkdom, struct rk_clk_fract_def *clkdef)
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sc = clknode_get_softc(clk);
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sc->flags = clkdef->flags;
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sc->offset = clkdef->offset;
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sc->gate_offset = clkdef->gate_offset;
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sc->gate_shift = clkdef->gate_shift;
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clknode_register(clkdom, clk);
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return (0);
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@ -35,9 +35,13 @@
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struct rk_clk_fract_def {
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struct clknode_init_def clkdef;
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uint32_t offset;
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uint32_t gate_offset;
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uint32_t gate_shift;
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uint32_t flags;
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};
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#define RK_CLK_FRACT_HAVE_GATE 0x0001
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||||
|
||||
int rk_clk_fract_register(struct clkdom *clkdom,
|
||||
struct rk_clk_fract_def *clkdef);
|
||||
|
||||
|
||||
@ -55,8 +55,17 @@ __FBSDID("$FreeBSD$");
|
||||
#define DEVICE_UNLOCK(_clk) \
|
||||
CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
|
||||
|
||||
#if 0
|
||||
#define dprintf(format, arg...) \
|
||||
printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
|
||||
#else
|
||||
#define dprintf(format, arg...)
|
||||
#endif
|
||||
|
||||
static int rk_clk_mux_init(struct clknode *clk, device_t dev);
|
||||
static int rk_clk_mux_set_mux(struct clknode *clk, int idx);
|
||||
static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent,
|
||||
uint64_t *fout, int flags, int *stop);
|
||||
|
||||
struct rk_clk_mux_sc {
|
||||
uint32_t offset;
|
||||
@ -69,6 +78,7 @@ static clknode_method_t rk_clk_mux_methods[] = {
|
||||
/* Device interface */
|
||||
CLKNODEMETHOD(clknode_init, rk_clk_mux_init),
|
||||
CLKNODEMETHOD(clknode_set_mux, rk_clk_mux_set_mux),
|
||||
CLKNODEMETHOD(clknode_set_freq, rk_clk_mux_set_freq),
|
||||
CLKNODEMETHOD_END
|
||||
};
|
||||
DEFINE_CLASS_1(rk_clk_mux, rk_clk_mux_class, rk_clk_mux_methods,
|
||||
@ -116,6 +126,57 @@ rk_clk_mux_set_mux(struct clknode *clk, int idx)
|
||||
return(0);
|
||||
}
|
||||
|
||||
static int
|
||||
rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
|
||||
int flags, int *stop)
|
||||
{
|
||||
struct rk_clk_mux_sc *sc;
|
||||
struct clknode *p_clk, *p_best_clk;
|
||||
const char **p_names;
|
||||
int p_idx, best_parent;
|
||||
int rv;
|
||||
|
||||
sc = clknode_get_softc(clk);
|
||||
|
||||
if ((sc->mux_flags & RK_CLK_MUX_REPARENT) == 0)
|
||||
return (0);
|
||||
|
||||
dprintf("Finding best parent for target freq of %ju\n", *fout);
|
||||
p_names = clknode_get_parent_names(clk);
|
||||
for (p_idx = 0; p_idx != clknode_get_parents_num(clk); p_idx++) {
|
||||
p_clk = clknode_find_by_name(p_names[p_idx]);
|
||||
dprintf("Testing with parent %s (%d)\n",
|
||||
clknode_get_name(p_clk), p_idx);
|
||||
|
||||
rv = clknode_set_freq(p_clk, *fout, flags | CLK_SET_DRYRUN, 0);
|
||||
dprintf("Testing with parent %s (%d) rv=%d\n",
|
||||
clknode_get_name(p_clk), p_idx, rv);
|
||||
if (rv == 0) {
|
||||
best_parent = p_idx;
|
||||
p_best_clk = p_clk;
|
||||
*stop = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (!*stop)
|
||||
return (0);
|
||||
|
||||
if ((flags & CLK_SET_DRYRUN) != 0)
|
||||
return (0);
|
||||
|
||||
p_idx = clknode_get_parent_idx(clk);
|
||||
if (p_idx != best_parent) {
|
||||
dprintf("Switching parent index from %d to %d\n", p_idx,
|
||||
best_parent);
|
||||
clknode_set_parent_by_idx(clk, best_parent);
|
||||
}
|
||||
|
||||
clknode_set_freq(p_best_clk, *fout, flags, 0);
|
||||
clknode_get_freq(p_best_clk, fout);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ struct rk_clk_mux_def {
|
||||
};
|
||||
|
||||
#define RK_CLK_MUX_MASK 0xFFFF0000
|
||||
#define RK_CLK_MUX_REPARENT (1 << 0)
|
||||
|
||||
int rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef);
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user