MFC r274641, r274644, r274822, r276049:
Allow i2c bus speed to be configured via hints, FDT data, and sysctl. Implement bus speed setting for OMAP4, AM335x, and imx5/6. Fix the i2c bus speed divisors for TI OMAP4 and AM335x to give the advertised 100, 400, and 1000 KHz speeds. PR: 195009
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@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd June 24, 2014
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.Dd November 17, 2014
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.Dt IICBUS 4
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.Os
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.Sh NAME
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@ -103,11 +103,58 @@ Some I2C interfaces are available:
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.It Sy lpbb Ta "parallel port specific bit-banging interface"
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.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface"
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.El
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.Sh BUS FREQUENCY CONFIGURATION
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The operating frequency of an I2C bus may be fixed or configurable.
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The bus may be used as part of some larger standard interface, and that
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interface specification may require a fixed frequency.
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The driver for that hardware would not honor an attempt to configure a
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different speed.
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A general purpose I2C bus, such as those found in many embedded systems,
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will often support multiple bus frequencies.
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.Pp
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When a system supports multiple I2C busses, a different frequency can
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be configured for each bus by number, represented by the
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.Va %d
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in the variable names below.
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Busses can be configured using any combination of device hints,
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Flattened Device Tree (FDT) data, tunables set via
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.Xr loader 8 ,
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or at runtime using
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.Xr sysctl 8 .
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When configuration is supplied using more than one method, FDT and
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hint data will be overridden by a tunable, which can be overriden by
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.Xr sysctl 8 .
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.Ss Device Hints
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Set
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.Va hint.iicbus.%d.frequency
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to the frequency in Hz, on systems that use device hints to configure
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I2C devices.
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The hint is also honored by systems that use FDT data if
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no frequency is configured using FDT.
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.Ss Flattened Device Tree Data
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Configure the I2C bus speed using the FDT standard
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.Va clock-frequency
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property of the node describing the I2C controller hardware.
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.Ss Sysctl and Tunable
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Set
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.Va dev.iicbus.%d.frequency
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in
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.Xr loader.conf 5 .
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The same variable can be changed at any time with
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.Xr sysctl 8 .
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Reset the bus using
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.Xr i2c 8
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or the
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.Xr iic 4
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.Va I2CRSTCARD
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ioctl to make the change take effect.
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.Sh SEE ALSO
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.Xr fdt 4 ,
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.Xr iic 4 ,
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.Xr iicbb 4 ,
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.Xr lpbb 4 ,
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.Xr pcf 4
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.Xr pcf 4 ,
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.Xr i2c 8
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.Sh HISTORY
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The
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.Nm
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@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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@ -45,6 +46,8 @@ __FBSDID("$FreeBSD$");
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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@ -79,6 +82,32 @@ __FBSDID("$FreeBSD$");
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#define I2C_BAUD_RATE_DEF 0x3F
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#define I2C_DFSSR_DIV 0x10
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/*
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* A table of available divisors and the associated coded values to put in the
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* FDR register to achieve that divisor.. There is no algorithmic relationship I
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* can see between divisors and the codes that go into the register. The table
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* begins and ends with entries that handle insane configuration values.
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*/
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struct clkdiv {
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u_int divisor;
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u_int regcode;
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};
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static struct clkdiv clkdiv_table[] = {
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{ 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 },
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{ 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 },
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{ 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 },
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{ 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a },
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{ 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d },
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{ 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c },
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{ 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f },
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{ 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 },
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{ 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 },
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{ 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 },
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{ 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d },
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{ 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c },
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{ 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
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};
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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@ -390,28 +419,29 @@ static int
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i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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{
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struct i2c_softc *sc;
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uint8_t baud_rate;
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u_int busfreq, div, i, ipgfreq;
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sc = device_get_softc(dev);
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switch (speed) {
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case IIC_FAST:
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baud_rate = I2C_BAUD_RATE_FAST;
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break;
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case IIC_SLOW:
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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baud_rate = I2C_BAUD_RATE_DEF;
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break;
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/*
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* Look up the divisor that gives the nearest speed that doesn't exceed
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* the configured value for the bus.
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*/
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ipgfreq = imx_ccm_ipg_hz();
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busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
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div = (ipgfreq + busfreq - 1) / busfreq;
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for (i = 0; i < nitems(clkdiv_table); i++) {
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if (clkdiv_table[i].divisor >= div)
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break;
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}
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div = clkdiv_table[i].regcode;
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mtx_lock(&sc->mutex);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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DELAY(1000);
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i2c_write_reg(sc, I2C_FDR_REG, 20);
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i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)div);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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DELAY(1000);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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@ -102,8 +102,7 @@ struct ti_i2c_softc
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struct ti_i2c_clock_config
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{
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int speed;
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int bitrate;
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u_int frequency; /* Bus frequency in Hz */
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uint8_t psc; /* Fast/Standard mode prescale divider */
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uint8_t scll; /* Fast/Standard mode SCL low time */
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uint8_t sclh; /* Fast/Standard mode SCL high time */
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@ -116,27 +115,30 @@ struct ti_i2c_clock_config
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#endif
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#if defined(SOC_OMAP4)
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/*
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* OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
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* The prescaler values for 100KHz and 400KHz modes come from the table in the
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* OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
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*/
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static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
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{ IIC_UNKNOWN, 100000, 23, 13, 15, 0, 0},
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{ IIC_SLOW, 100000, 23, 13, 15, 0, 0},
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{ IIC_FAST, 400000, 9, 5, 7, 0, 0},
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{ IIC_FASTEST, 1000000, 5, 3, 4, 0, 0},
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/* { IIC_FASTEST, 3200000, 1, 113, 115, 7, 10}, - HS mode */
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{ -1, 0 }
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{ 100000, 23, 13, 15, 0, 0},
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{ 400000, 9, 5, 7, 0, 0},
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{ 1000000, 3, 5, 7, 0, 0},
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/* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
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{ 0 /* Table terminator */ }
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};
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#endif
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#if defined(SOC_TI_AM335X)
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/*
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* AM335X doesn't support HS mode. For 100kHz I2C clock set the internal
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* clock to 12Mhz, for 400kHz I2C clock set the internal clock to 24Mhz.
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* AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
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* In all cases we prescale the clock to 24MHz as recommended in the manual.
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*/
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static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
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{ IIC_UNKNOWN, 100000, 7, 59, 61, 0, 0},
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{ IIC_SLOW, 100000, 7, 59, 61, 0, 0},
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{ IIC_FAST, 400000, 3, 23, 25, 0, 0},
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{ IIC_FASTEST, 400000, 3, 23, 25, 0, 0},
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{ -1, 0 }
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{ 100000, 1, 111, 117, 0, 0},
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{ 400000, 1, 23, 25, 0, 0},
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{ 1000000, 1, 5, 7, 0, 0},
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{ 0 /* Table terminator */ }
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};
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#endif
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@ -512,6 +514,7 @@ ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
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{
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int timeout;
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struct ti_i2c_clock_config *clkcfg;
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u_int busfreq;
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uint16_t fifo_trsh, reg, scll, sclh;
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switch (ti_chip()) {
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@ -528,13 +531,24 @@ ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
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default:
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panic("Unknown Ti SoC, unable to reset the i2c");
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}
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while (clkcfg->speed != -1) {
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if (clkcfg->speed == speed)
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/*
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* If we haven't attached the bus yet, just init at the default slow
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* speed. This lets us get the hardware initialized enough to attach
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* the bus which is where the real speed configuration is handled. After
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* the bus is attached, get the configured speed from it. Search the
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* configuration table for the best speed we can do that doesn't exceed
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* the requested speed.
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*/
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if (sc->sc_iicbus == NULL)
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busfreq = 100000;
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else
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busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
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for (;;) {
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if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
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break;
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clkcfg++;
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}
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if (clkcfg->speed == -1)
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return (EINVAL);
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/*
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* 23.1.4.3 - HS I2C Software Reset
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@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/bus.h>
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#include <dev/iicbus/iiconf.h>
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@ -96,6 +97,7 @@ iicbus_attach(device_t dev)
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sc->dev = dev;
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mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF);
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iicbus_init_frequency(dev, 0);
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iicbus_reset(dev, IIC_FASTEST, 0, NULL);
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if (resource_int_value(device_get_name(dev),
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device_get_unit(dev), "strict", &strict) == 0)
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@ -243,6 +245,51 @@ iicbus_null_repeated_start(device_t dev, u_char addr)
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return (IIC_ENOTSUPP);
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}
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void
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iicbus_init_frequency(device_t dev, u_int bus_freq)
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{
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struct iicbus_softc *sc = IICBUS_SOFTC(dev);
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/*
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* If a bus frequency value was passed in, use it. Otherwise initialize
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* it first to the standard i2c 100KHz frequency, then override that
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* from a hint if one exists.
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*/
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if (bus_freq > 0)
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sc->bus_freq = bus_freq;
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else {
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sc->bus_freq = 100000;
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resource_int_value(device_get_name(dev), device_get_unit(dev),
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"frequency", (int *)&sc->bus_freq);
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}
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/*
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* Set up the sysctl that allows the bus frequency to be changed.
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* It is flagged as a tunable so that the user can set the value in
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* loader(8), and that will override any other setting from any source.
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* The sysctl tunable/value is the one most directly controlled by the
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* user and thus the one that always takes precedence.
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*/
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SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
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OID_AUTO, "frequency", CTLFLAG_RW | CTLFLAG_TUN, &sc->bus_freq,
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sc->bus_freq, "Bus frequency in Hz");
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}
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static u_int
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iicbus_get_frequency(device_t dev, u_char speed)
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{
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struct iicbus_softc *sc = IICBUS_SOFTC(dev);
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/*
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* If the frequency has not been configured for the bus, or the request
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* is specifically for SLOW speed, use the standard 100KHz rate, else
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* use the configured bus speed.
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*/
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if (sc->bus_freq == 0 || speed == IIC_SLOW)
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return (100000);
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return (sc->bus_freq);
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}
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static device_method_t iicbus_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, iicbus_probe),
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@ -260,6 +307,7 @@ static device_method_t iicbus_methods[] = {
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/* iicbus interface */
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DEVMETHOD(iicbus_transfer, iicbus_transfer),
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DEVMETHOD(iicbus_get_frequency, iicbus_get_frequency),
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DEVMETHOD_END
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};
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@ -44,6 +44,7 @@ struct iicbus_softc
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u_char strict; /* deny operations that violate the
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* I2C protocol */
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struct mtx lock;
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u_int bus_freq; /* Configured bus Hz. */
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};
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struct iicbus_ivar
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@ -67,7 +68,8 @@ IICBUS_ACCESSOR(nostop, NOSTOP, bool)
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#define IICBUS_UNLOCK(sc) mtx_unlock(&(sc)->lock)
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#define IICBUS_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
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extern int iicbus_generic_intr(device_t dev, int event, char *buf);
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int iicbus_generic_intr(device_t dev, int event, char *buf);
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void iicbus_init_frequency(device_t dev, u_int bus_freq);
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extern driver_t iicbus_driver;
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extern devclass_t iicbus_devclass;
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@ -31,6 +31,15 @@
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INTERFACE iicbus;
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CODE {
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static u_int
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iicbus_default_frequency(device_t bus, u_char speed)
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{
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return (100000);
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}
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};
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#
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# Interpret interrupt
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#
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@ -115,3 +124,14 @@ METHOD int transfer {
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struct iic_msg *msgs;
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uint32_t nmsgs;
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};
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#
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# Return the frequency in Hz for the bus running at the given
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# symbolic speed. Only the IIC_SLOW speed has meaning, it is always
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# 100KHz. The UNKNOWN, FAST, and FASTEST rates all map to the
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# configured bus frequency, or 100KHz when not otherwise configured.
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#
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METHOD u_int get_frequency {
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device_t dev;
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u_char speed;
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} DEFAULT iicbus_default_frequency;
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@ -101,12 +101,24 @@ ofw_iicbus_attach(device_t dev)
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{
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struct iicbus_softc *sc = IICBUS_SOFTC(dev);
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struct ofw_iicbus_devinfo *dinfo;
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phandle_t child;
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pcell_t paddr;
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phandle_t child, node;
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pcell_t freq, paddr;
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device_t childdev;
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sc->dev = dev;
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mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF);
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/*
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* If there is a clock-frequency property for the device node, use it as
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* the starting value for the bus frequency. Then call the common
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* routine that handles the tunable/sysctl which allows the FDT value to
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* be overridden by the user.
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*/
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node = ofw_bus_get_node(dev);
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freq = 0;
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OF_getencprop(node, "clock-frequency", &freq, sizeof(freq));
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iicbus_init_frequency(dev, freq);
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iicbus_reset(dev, IIC_FASTEST, 0, NULL);
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bus_generic_probe(dev);
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@ -115,8 +127,7 @@ ofw_iicbus_attach(device_t dev)
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/*
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* Attach those children represented in the device tree.
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*/
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for (child = OF_child(ofw_bus_get_node(dev)); child != 0;
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child = OF_peer(child)) {
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for (child = OF_child(node); child != 0; child = OF_peer(child)) {
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/*
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* Try to get the I2C address first from the i2c-address
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* property, then try the reg property. It moves around
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