Fix the interrupt code, broken 7 months ago. The interrupt framework
already supported nested PICs, but was limited to having a nested
AT-PIC only. With G5 support the need for nested OpenPIC controllers
needed to be added. This was done the wrong way and broke the MPC8555
eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a
controller and an interrupt pin on it. This needs to be mapped to a
flat and global resource: the IRQ. The IRQ is the same as the PCI
intline and as such needs to be representable in 8 bits. Secondly,
ISA support pretty much dictates that IRQ 0-15 should be reserved
for ISA interrupts, because of the internal workins of south bridges.
Both were broken.
This change reverts revision 209298 for a big part and re-implements
it simpler. In particular:
o The id() method of the PIC I/F is removed again. It's not needed.
o The openpic_attach() function has been changed to take the OFW
or FDT phandle of the controller as a second argument. All bus
attachments that previously used openpic_attach() as the attach
method of the device I/F now implement as bus-specific method
and pass the phandle_t to the renamed openpic_attach().
o Change powerpc_register_pic() to take a few more arguments. In
particular:
- Pass the number of IPIs specificly. The number of IRQs carved
out for a PIC is the sum of the number of int. pins and IPIs.
- Pass a flag indicating whether the PIC is an AT-PIC or not.
This tells the interrupt framework whether to assign IRQ 0-15
or some other range.
o Until we implement proper multi-pass bus enumeration, we have to
handle the case where we need to map from PIC+pin to IRQ *before*
the PIC gets registered. This is done in a similar way as before,
but rather than carving out 256 IRQs per PIC, we carve out 128
IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case,
but should really be fixed properly using multiple passes.
o Have the interrupt framework set root_pic in most cases and not
put that burden in PIC drivers (for the most part).
o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq().
Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken
by the FDT code. Besides not attaching properly, bus numbers were
assigned improperly and enumeration was broken in general. This
prevented the AT PIC from being discovered and interrupt routing to
work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS
going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible
that there are unpleasant side-effects. At least MPC85xx support is
back to where it was 7 months ago -- it's amazing how badly support
can be broken in just 7 months...
Sponsored by: Juniper Networks
This commit is contained in:
marcel
parent
f9d6eb1e75
commit
d129fb0e44
@ -29,13 +29,9 @@
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#define _MACHINE_INTR_MACHDEP_H_
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#define INTR_VECTORS 256
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#define MAX_PICS 5
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#define IGN_SHIFT 8
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#define INTR_INTLINE(irq) (irq & ((1 << IGN_SHIFT) - 1))
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#define INTR_IGN(irq) (irq >> IGN_SHIFT)
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#define INTR_VEC(pic_id, irq) ((powerpc_ign_lookup(pic_id) << IGN_SHIFT) | (irq))
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#define MAX_PICS 5
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#define INTR_VEC(node, pin) powerpc_get_irq(node, pin)
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/*
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* Default base address for MSI messages on PowerPC
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@ -50,8 +46,8 @@ driver_filter_t powerpc_ipi_handler;
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void intrcnt_add(const char *name, u_long **countp);
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void powerpc_register_pic(device_t, u_int);
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int powerpc_ign_lookup(uint32_t pic_id);
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void powerpc_register_pic(device_t, uint32_t, u_int, u_int, u_int);
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u_int powerpc_get_irq(uint32_t, u_int);
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void powerpc_dispatch_intr(u_int, struct trapframe *);
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int powerpc_enable_intr(void);
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@ -52,7 +52,7 @@ extern devclass_t openpic_devclass;
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/*
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* Bus-independent attach i/f
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*/
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int openpic_attach(device_t);
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int openpic_common_attach(device_t, uint32_t);
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/*
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* PIC interface.
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@ -56,12 +56,11 @@ __FBSDID("$FreeBSD$");
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* Mambo interface
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*/
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static int openpic_mambo_probe(device_t);
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static uint32_t openpic_mambo_id(device_t dev);
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static int openpic_mambo_attach(device_t);
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static int openpicbus_mambo_probe(device_t dev);
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static int openpicbus_mambo_attach(device_t dev);
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static struct resource *openpicbus_alloc_resource(device_t bus, device_t dev,
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int type, int *rid, u_long start, u_long end, u_long count,
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u_int flags);
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static struct resource *openpicbus_alloc_resource(device_t bus, device_t dev,
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int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
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static device_method_t openpicbus_mambo_methods[] = {
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/* Device interface */
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@ -87,7 +86,7 @@ static driver_t openpicbus_mambo_driver = {
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static device_method_t openpic_mambo_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, openpic_mambo_probe),
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DEVMETHOD(device_attach, openpic_attach),
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DEVMETHOD(device_attach, openpic_mambo_attach),
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/* PIC interface */
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DEVMETHOD(pic_config, openpic_config),
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@ -97,7 +96,6 @@ static device_method_t openpic_mambo_methods[] = {
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DEVMETHOD(pic_ipi, openpic_ipi),
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DEVMETHOD(pic_mask, openpic_mask),
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DEVMETHOD(pic_unmask, openpic_unmask),
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DEVMETHOD(pic_id, openpic_mambo_id),
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{ 0, 0 },
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};
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@ -167,14 +165,15 @@ openpicbus_alloc_resource(device_t bus, device_t dev, int type, int *rid,
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static int
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openpic_mambo_probe(device_t dev)
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{
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device_set_desc(dev, OPENPIC_DEVSTR);
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return (0);
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}
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static uint32_t
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openpic_mambo_id(device_t dev)
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static int
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openpic_mambo_attach(device_t dev)
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{
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return (ofw_bus_get_node(device_get_parent(dev)));
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return (openpic_common_attach(dev,
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ofw_bus_get_node(device_get_parent(dev))));
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}
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@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/ocpbus.h>
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#include <machine/pio.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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@ -79,7 +78,6 @@ static void atpic_eoi(device_t, u_int);
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static void atpic_ipi(device_t, u_int);
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static void atpic_mask(device_t, u_int);
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static void atpic_unmask(device_t, u_int);
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static uint32_t atpic_id (device_t dev);
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static device_method_t atpic_isa_methods[] = {
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/* Device interface */
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@ -95,7 +93,6 @@ static device_method_t atpic_isa_methods[] = {
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DEVMETHOD(pic_ipi, atpic_ipi),
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DEVMETHOD(pic_mask, atpic_mask),
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DEVMETHOD(pic_unmask, atpic_unmask),
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DEVMETHOD(pic_id, atpic_id),
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{ 0, 0 },
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};
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@ -154,7 +151,7 @@ atpic_isa_identify(driver_t *drv, device_t parent)
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bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
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/* ISA interrupts are routed through external interrupt 0. */
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bus_set_resource(child, SYS_RES_IRQ, 0, PIC_IRQ_EXT(0), 1);
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bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
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}
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static int
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@ -221,7 +218,7 @@ atpic_isa_attach(device_t dev)
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atpic_init(sc, ATPIC_SLAVE);
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atpic_init(sc, ATPIC_MASTER);
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powerpc_register_pic(dev, 0x10);
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powerpc_register_pic(dev, 0, 16, 0, TRUE);
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return (0);
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fail:
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@ -328,11 +325,3 @@ atpic_unmask(device_t dev, u_int irq)
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atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
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}
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}
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static uint32_t
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atpic_id (device_t dev)
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{
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return (ATPIC_ID);
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}
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@ -33,15 +33,12 @@ __FBSDID("$FreeBSD$");
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#include <sys/rman.h>
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#include <machine/intr_machdep.h>
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#include <machine/ocpbus.h>
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#include <machine/resource.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <isa/isa_common.h>
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#include "ocpbus.h"
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void
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isa_init(device_t dev)
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{
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@ -62,10 +59,7 @@ isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
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resource_list_find(rl, type, *rid) == NULL) {
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switch (type) {
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case SYS_RES_IOPORT: rids = ISA_PNP_NPORT; break;
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case SYS_RES_IRQ:
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rids = ISA_PNP_NIRQ;
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start = ISA_IRQ(start);
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break;
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case SYS_RES_IRQ: rids = ISA_PNP_NIRQ; break;
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case SYS_RES_MEMORY: rids = ISA_PNP_NMEM; break;
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default: rids = 0; break;
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}
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@ -45,12 +45,12 @@ __FBSDID("$FreeBSD$");
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#include "pic_if.h"
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static int openpic_fdt_probe(device_t);
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static uint32_t openpic_fdt_id(device_t);
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static int openpic_fdt_attach(device_t);
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static device_method_t openpic_fdt_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, openpic_fdt_probe),
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DEVMETHOD(device_attach, openpic_attach),
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DEVMETHOD(device_attach, openpic_fdt_attach),
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/* PIC interface */
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DEVMETHOD(pic_bind, openpic_bind),
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@ -61,7 +61,6 @@ static device_method_t openpic_fdt_methods[] = {
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DEVMETHOD(pic_ipi, openpic_ipi),
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DEVMETHOD(pic_mask, openpic_mask),
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DEVMETHOD(pic_unmask, openpic_unmask),
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DEVMETHOD(pic_id, openpic_fdt_id),
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{ 0, 0 },
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};
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@ -85,9 +84,9 @@ openpic_fdt_probe(device_t dev)
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return (BUS_PROBE_DEFAULT);
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}
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static uint32_t
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openpic_fdt_id(device_t dev)
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static int
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openpic_fdt_attach(device_t dev)
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{
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return (ofw_bus_get_node(dev));
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return (openpic_common_attach(dev, ofw_bus_get_node(dev)));
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}
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@ -136,7 +136,7 @@ static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
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static void fsl_pcib_err_init(device_t);
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static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
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u_long, u_long);
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static int fsl_pcib_init(struct fsl_pcib_softc *, int, int, int);
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static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
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static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *);
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static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long,
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u_long);
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@ -160,8 +160,6 @@ static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int next_busnr = 0;
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/* Configuration r/w mutex. */
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struct mtx pcicfg_mtx;
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static int mtx_initialized = 0;
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@ -215,23 +213,17 @@ DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0);
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static int
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fsl_pcib_probe(device_t dev)
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{
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phandle_t parnode;
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phandle_t node;
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/*
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* The PCI subnode does not have the 'compatible' property, so we need
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* to check in the parent PCI node. However the parent is not
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* represented by a separate ofw_bus child, and therefore
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* ofw_bus_is_compatible() cannot be used, but direct fdt equivalent.
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*/
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parnode = OF_parent(ofw_bus_get_node(dev));
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if (parnode == 0)
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node = ofw_bus_get_node(dev);
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if (!fdt_is_type(node, "pci"))
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return (ENXIO);
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if (!(fdt_is_compatible(parnode, "fsl,mpc8548-pcie") ||
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fdt_is_compatible(parnode, "fsl,mpc8548-pcie")))
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if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") ||
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fdt_is_compatible(node, "fsl,mpc8548-pcie")))
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return (ENXIO);
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device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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@ -241,7 +233,7 @@ fsl_pcib_attach(device_t dev)
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struct fsl_pcib_softc *sc;
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phandle_t node;
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uint32_t cfgreg;
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int maxslot, subbus;
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int maxslot;
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uint8_t ltssm, capptr;
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sc = device_get_softc(dev);
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@ -304,23 +296,13 @@ fsl_pcib_attach(device_t dev)
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sc->sc_devfn_tundra = -1;
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sc->sc_devfn_via_ide = -1;
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maxslot = (sc->sc_pcie) ? 1 : 31;
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/*
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* Scan bus using firmware configured, 0 based bus numbering,
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* let fsl_pcib_init() shift bus number by next_busnr offset.
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* Scan bus using firmware configured, 0 based bus numbering.
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*/
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sc->sc_busnr = 1;
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subbus = fsl_pcib_init(sc, 0, next_busnr, maxslot);
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if (bootverbose)
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printf("PCI: domain %d, busnr = %d, next_busnr = %d\n",
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device_get_unit(dev), next_busnr + 1,
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next_busnr + subbus + 1);
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/* Set final busnr */
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sc->sc_busnr = next_busnr + 1;
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next_busnr += subbus + 1;
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sc->sc_busnr = 0;
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maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
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fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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if (sc->sc_pcie) {
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ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
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@ -455,7 +437,7 @@ fsl_pcib_maxslots(device_t dev)
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{
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struct fsl_pcib_softc *sc = device_get_softc(dev);
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return ((sc->sc_pcie) ? 1 : 31);
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return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
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}
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static uint32_t
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@ -572,14 +554,11 @@ fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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devfn = DEVFN(bus, slot, func);
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if (devfn == sc->sc_devfn_via_ide)
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#if 0
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intline = INTR_VEC(ATPIC_ID, 14);
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intline = INTR_VEC(0, 14);
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else if (devfn == sc->sc_devfn_via_ide + 1)
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intline = INTR_VEC(ATPIC_ID, 10);
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intline = INTR_VEC(0, 10);
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else if (devfn == sc->sc_devfn_via_ide + 2)
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intline = INTR_VEC(ATPIC_ID, 10);
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#endif
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;
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intline = INTR_VEC(0, 10);
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else {
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if (intpin != 0)
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err = fdt_pci_route_intr(bus, slot, func, intpin,
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@ -596,10 +575,9 @@ fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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}
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static int
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fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int busnr_offset,
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int maxslot)
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fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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{
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int secbus, subbus;
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int secbus;
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int old_pribus, old_secbus, old_subbus;
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int new_pribus, new_secbus, new_subbus;
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int slot, func, maxfunc;
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@ -608,11 +586,10 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int busnr_offset,
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uint8_t command, hdrtype, class, subclass;
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uint8_t intline, intpin;
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subbus = bus;
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secbus = bus;
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for (slot = 0; slot <= maxslot; slot++) {
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maxfunc = 0;
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for (func = 0; func <= maxfunc; func++) {
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hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_HDRTYPE, 1);
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@ -667,19 +644,14 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int busnr_offset,
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func, PCIR_CLASS, 1);
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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#if 0
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/* Allow only proper PCI-PCI briges */
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if (class != PCIC_BRIDGE)
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continue;
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if (subclass != PCIS_BRIDGE_PCI)
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continue;
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#endif
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/* Allow all DEVTYPE 1 devices */
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if (hdrtype != PCIM_HDRTYPE_BRIDGE)
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continue;
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subbus++;
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secbus = subbus;
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secbus++;
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/* Program I/O decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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@ -718,31 +690,20 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int busnr_offset,
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if (bootverbose)
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printf("PCI: reading firmware bus numbers for "
|
||||
"secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
|
||||
secbus + busnr_offset, old_pribus,
|
||||
old_secbus, old_subbus);
|
||||
secbus, old_pribus, old_secbus, old_subbus);
|
||||
|
||||
/* Skip unconfigured devices */
|
||||
if ((old_pribus == 0) &&
|
||||
(old_secbus == 0) && (old_subbus == 0))
|
||||
continue;
|
||||
new_pribus = bus;
|
||||
new_secbus = secbus;
|
||||
|
||||
subbus += fsl_pcib_init(sc, secbus, busnr_offset,
|
||||
(subclass == PCIS_BRIDGE_PCI) ? 31 : 1);
|
||||
secbus = fsl_pcib_init(sc, secbus,
|
||||
(subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
|
||||
|
||||
new_pribus = bus + busnr_offset;
|
||||
new_secbus = secbus + busnr_offset;
|
||||
new_subbus = subbus + busnr_offset;
|
||||
|
||||
/* Fixup pribus for MPC8572 PCIE controller */
|
||||
if ((vendor == 0x1957) && ((device = 0x0040) ||
|
||||
(device == 0x0041)))
|
||||
new_pribus = 0;
|
||||
new_subbus = secbus;
|
||||
|
||||
if (bootverbose)
|
||||
printf("PCI: translate firmware bus numbers for "
|
||||
"secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
|
||||
secbus + busnr_offset,
|
||||
old_pribus, old_secbus, old_subbus,
|
||||
printf("PCI: translate firmware bus numbers "
|
||||
"for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
|
||||
secbus, old_pribus, old_secbus, old_subbus,
|
||||
new_pribus, new_secbus, new_subbus);
|
||||
|
||||
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
||||
@ -754,11 +715,7 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int busnr_offset,
|
||||
}
|
||||
}
|
||||
|
||||
if (bootverbose)
|
||||
printf("PCI: bus %d, #subbus = %d\n",
|
||||
bus + busnr_offset, subbus - bus);
|
||||
|
||||
return (subbus - bus);
|
||||
return (secbus);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -938,12 +895,10 @@ fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
va = sc->sc_iomem_va;
|
||||
break;
|
||||
case SYS_RES_IRQ:
|
||||
#if 0
|
||||
if (INTR_IGN(start) == powerpc_ign_lookup(ATPIC_ID)) {
|
||||
if (start < 16) {
|
||||
device_printf(dev, "%s requested ISA interrupt %lu\n",
|
||||
device_get_nameunit(child), start);
|
||||
}
|
||||
#endif
|
||||
flags |= RF_SHAREABLE;
|
||||
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
||||
type, rid, start, end, count, flags));
|
||||
|
||||
@ -757,7 +757,6 @@ static void openpic_cpcht_config(device_t, u_int irq,
|
||||
static void openpic_cpcht_enable(device_t, u_int irq, u_int vector);
|
||||
static void openpic_cpcht_unmask(device_t, u_int irq);
|
||||
static void openpic_cpcht_eoi(device_t, u_int irq);
|
||||
static uint32_t openpic_cpcht_id(device_t);
|
||||
|
||||
static device_method_t openpic_cpcht_methods[] = {
|
||||
/* Device interface */
|
||||
@ -773,7 +772,6 @@ static device_method_t openpic_cpcht_methods[] = {
|
||||
DEVMETHOD(pic_ipi, openpic_ipi),
|
||||
DEVMETHOD(pic_mask, openpic_mask),
|
||||
DEVMETHOD(pic_unmask, openpic_cpcht_unmask),
|
||||
DEVMETHOD(pic_id, openpic_cpcht_id),
|
||||
|
||||
{ 0, 0 },
|
||||
};
|
||||
@ -808,9 +806,11 @@ static int
|
||||
openpic_cpcht_attach(device_t dev)
|
||||
{
|
||||
struct openpic_cpcht_softc *sc;
|
||||
phandle_t node;
|
||||
int err, irq;
|
||||
|
||||
err = openpic_attach(dev);
|
||||
node = ofw_bus_get_node(dev);
|
||||
err = openpic_common_attach(dev, node);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
@ -839,9 +839,8 @@ openpic_cpcht_attach(device_t dev)
|
||||
* be necessary, but Linux does it, and I cannot find any U3 machines
|
||||
* with MSI devices to test.
|
||||
*/
|
||||
|
||||
if (dev == root_pic)
|
||||
cpcht_msipic = PIC_ID(dev);
|
||||
cpcht_msipic = node;
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -981,10 +980,3 @@ openpic_cpcht_eoi(device_t dev, u_int irq)
|
||||
|
||||
openpic_eoi(dev, irq);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
openpic_cpcht_id(device_t dev)
|
||||
{
|
||||
return (ofw_bus_get_node(dev));
|
||||
}
|
||||
|
||||
|
||||
@ -69,7 +69,6 @@ static void hrowpic_eoi(device_t, u_int);
|
||||
static void hrowpic_ipi(device_t, u_int);
|
||||
static void hrowpic_mask(device_t, u_int);
|
||||
static void hrowpic_unmask(device_t, u_int);
|
||||
static uint32_t hrowpic_id(device_t dev);
|
||||
|
||||
static device_method_t hrowpic_methods[] = {
|
||||
/* Device interface */
|
||||
@ -80,7 +79,6 @@ static device_method_t hrowpic_methods[] = {
|
||||
DEVMETHOD(pic_dispatch, hrowpic_dispatch),
|
||||
DEVMETHOD(pic_enable, hrowpic_enable),
|
||||
DEVMETHOD(pic_eoi, hrowpic_eoi),
|
||||
DEVMETHOD(pic_id, hrowpic_id),
|
||||
DEVMETHOD(pic_ipi, hrowpic_ipi),
|
||||
DEVMETHOD(pic_mask, hrowpic_mask),
|
||||
DEVMETHOD(pic_unmask, hrowpic_unmask),
|
||||
@ -169,9 +167,7 @@ hrowpic_attach(device_t dev)
|
||||
hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_SECONDARY, 0);
|
||||
hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff);
|
||||
|
||||
powerpc_register_pic(dev, 64);
|
||||
root_pic = dev; /* Heathrow systems have only one PIC */
|
||||
|
||||
powerpc_register_pic(dev, ofw_bus_get_node(dev), 64, 0, FALSE);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -282,10 +278,3 @@ hrowpic_unmask(device_t dev, u_int irq)
|
||||
sc = device_get_softc(dev);
|
||||
hrowpic_toggle_irq(sc, irq, 1);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
hrowpic_id(device_t dev)
|
||||
{
|
||||
return (ofw_bus_get_node(dev));
|
||||
}
|
||||
|
||||
|
||||
@ -58,12 +58,12 @@ __FBSDID("$FreeBSD$");
|
||||
* MacIO interface
|
||||
*/
|
||||
static int openpic_macio_probe(device_t);
|
||||
static uint32_t openpic_macio_id(device_t);
|
||||
static int openpic_macio_attach(device_t);
|
||||
|
||||
static device_method_t openpic_macio_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, openpic_macio_probe),
|
||||
DEVMETHOD(device_attach, openpic_attach),
|
||||
DEVMETHOD(device_attach, openpic_macio_attach),
|
||||
|
||||
/* PIC interface */
|
||||
DEVMETHOD(pic_bind, openpic_bind),
|
||||
@ -74,7 +74,6 @@ static device_method_t openpic_macio_methods[] = {
|
||||
DEVMETHOD(pic_ipi, openpic_ipi),
|
||||
DEVMETHOD(pic_mask, openpic_mask),
|
||||
DEVMETHOD(pic_unmask, openpic_unmask),
|
||||
DEVMETHOD(pic_id, openpic_macio_id),
|
||||
|
||||
{ 0, 0 },
|
||||
};
|
||||
@ -99,9 +98,9 @@ openpic_macio_probe(device_t dev)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
openpic_macio_id(device_t dev)
|
||||
static int
|
||||
openpic_macio_attach(device_t dev)
|
||||
{
|
||||
return (ofw_bus_get_node(dev));
|
||||
|
||||
return (openpic_common_attach(dev, ofw_bus_get_node(dev)));
|
||||
}
|
||||
|
||||
|
||||
@ -60,6 +60,8 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include "opt_isa.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
@ -102,9 +104,11 @@ struct powerpc_intr {
|
||||
};
|
||||
|
||||
struct pic {
|
||||
device_t pic;
|
||||
uint32_t pic_id;
|
||||
int ipi_irq;
|
||||
device_t dev;
|
||||
uint32_t node;
|
||||
u_int irqs;
|
||||
u_int ipis;
|
||||
int base;
|
||||
};
|
||||
|
||||
static u_int intrcnt_index = 0;
|
||||
@ -113,6 +117,11 @@ static struct powerpc_intr *powerpc_intrs[INTR_VECTORS];
|
||||
static struct pic piclist[MAX_PICS];
|
||||
static u_int nvectors; /* Allocated vectors */
|
||||
static u_int npics; /* PICs registered */
|
||||
#ifdef DEV_ISA
|
||||
static u_int nirqs = 16; /* Allocated IRQS (ISA pre-allocated). */
|
||||
#else
|
||||
static u_int nirqs = 0; /* Allocated IRQs. */
|
||||
#endif
|
||||
static u_int stray_count;
|
||||
|
||||
device_t root_pic;
|
||||
@ -142,7 +151,6 @@ smp_intr_init(void *dummy __unused)
|
||||
PIC_BIND(i->pic, i->intline, i->cpu);
|
||||
}
|
||||
}
|
||||
|
||||
SYSINIT(smp_intr_init, SI_SUB_SMP, SI_ORDER_ANY, smp_intr_init, NULL);
|
||||
#endif
|
||||
|
||||
@ -231,9 +239,21 @@ intr_lookup(u_int irq)
|
||||
static int
|
||||
powerpc_map_irq(struct powerpc_intr *i)
|
||||
{
|
||||
struct pic *p;
|
||||
u_int cnt;
|
||||
int idx;
|
||||
|
||||
i->intline = INTR_INTLINE(i->irq);
|
||||
i->pic = piclist[INTR_IGN(i->irq)].pic;
|
||||
for (idx = 0; idx < npics; idx++) {
|
||||
p = &piclist[idx];
|
||||
cnt = p->irqs + p->ipis;
|
||||
if (i->irq >= p->base && i->irq < p->base + cnt)
|
||||
break;
|
||||
}
|
||||
if (idx == npics)
|
||||
return (EINVAL);
|
||||
|
||||
i->intline = i->irq - p->base;
|
||||
i->pic = p->dev;
|
||||
|
||||
/* Try a best guess if that failed */
|
||||
if (i->pic == NULL)
|
||||
@ -288,46 +308,76 @@ powerpc_assign_intr_cpu(void *arg, u_char cpu)
|
||||
}
|
||||
|
||||
void
|
||||
powerpc_register_pic(device_t dev, u_int ipi)
|
||||
powerpc_register_pic(device_t dev, uint32_t node, u_int irqs, u_int ipis,
|
||||
u_int atpic)
|
||||
{
|
||||
int i;
|
||||
struct pic *p;
|
||||
u_int irq;
|
||||
int idx;
|
||||
|
||||
mtx_lock(&intr_table_lock);
|
||||
|
||||
for (i = 0; i < npics; i++) {
|
||||
if (piclist[i].pic_id == PIC_ID(dev))
|
||||
/* XXX see powerpc_get_irq(). */
|
||||
for (idx = 0; idx < npics; idx++) {
|
||||
p = &piclist[idx];
|
||||
if (p->node != node)
|
||||
continue;
|
||||
if (node != 0 || p->dev == dev)
|
||||
break;
|
||||
}
|
||||
piclist[i].pic = dev;
|
||||
piclist[i].pic_id = PIC_ID(dev);
|
||||
piclist[i].ipi_irq = ipi;
|
||||
if (i == npics)
|
||||
p = &piclist[idx];
|
||||
|
||||
p->dev = dev;
|
||||
p->node = node;
|
||||
p->irqs = irqs;
|
||||
p->ipis = ipis;
|
||||
if (idx == npics) {
|
||||
#ifdef DEV_ISA
|
||||
p->base = (atpic) ? 0 : nirqs;
|
||||
#else
|
||||
p->base = nirqs;
|
||||
#endif
|
||||
irq = p->base + irqs + ipis;
|
||||
nirqs = MAX(nirqs, irq);
|
||||
npics++;
|
||||
}
|
||||
|
||||
mtx_unlock(&intr_table_lock);
|
||||
}
|
||||
|
||||
int
|
||||
powerpc_ign_lookup(uint32_t pic_id)
|
||||
u_int
|
||||
powerpc_get_irq(uint32_t node, u_int pin)
|
||||
{
|
||||
int i;
|
||||
int idx;
|
||||
|
||||
if (node == 0)
|
||||
return (pin);
|
||||
|
||||
mtx_lock(&intr_table_lock);
|
||||
|
||||
for (i = 0; i < npics; i++) {
|
||||
if (piclist[i].pic_id == pic_id) {
|
||||
for (idx = 0; idx < npics; idx++) {
|
||||
if (piclist[idx].node == node) {
|
||||
mtx_unlock(&intr_table_lock);
|
||||
return (i);
|
||||
return (piclist[idx].base + pin);
|
||||
}
|
||||
}
|
||||
piclist[i].pic = NULL;
|
||||
piclist[i].pic_id = pic_id;
|
||||
piclist[i].ipi_irq = 0;
|
||||
|
||||
/*
|
||||
* XXX we should never encounter an unregistered PIC, but that
|
||||
* can only be done when we properly support bus enumeration
|
||||
* using multiple passes. Until then, fake an entry and give it
|
||||
* some adhoc maximum number of IRQs and IPIs.
|
||||
*/
|
||||
piclist[idx].dev = NULL;
|
||||
piclist[idx].node = node;
|
||||
piclist[idx].irqs = 124;
|
||||
piclist[idx].ipis = 4;
|
||||
piclist[idx].base = nirqs;
|
||||
nirqs += 128;
|
||||
npics++;
|
||||
|
||||
mtx_unlock(&intr_table_lock);
|
||||
|
||||
return (i);
|
||||
return (piclist[idx].base + pin);
|
||||
}
|
||||
|
||||
int
|
||||
@ -342,15 +392,18 @@ powerpc_enable_intr(void)
|
||||
if (npics == 0)
|
||||
panic("no PIC detected\n");
|
||||
|
||||
if (root_pic == NULL)
|
||||
root_pic = piclist[0].dev;
|
||||
|
||||
#ifdef SMP
|
||||
/* Install an IPI handler. */
|
||||
|
||||
for (n = 0; n < npics; n++) {
|
||||
if (piclist[n].pic != root_pic)
|
||||
if (piclist[n].dev != root_pic)
|
||||
continue;
|
||||
|
||||
KASSERT(piclist[n].ipis != 0, ("%s", __func__));
|
||||
error = powerpc_setup_intr("IPI",
|
||||
INTR_VEC(piclist[n].pic_id, piclist[n].ipi_irq),
|
||||
INTR_VEC(piclist[n].node, piclist[n].irqs),
|
||||
powerpc_ipi_handler, NULL, NULL,
|
||||
INTR_TYPE_MISC | INTR_EXCL, &ipi_cookie);
|
||||
if (error) {
|
||||
@ -373,6 +426,9 @@ powerpc_enable_intr(void)
|
||||
i->pol != INTR_POLARITY_CONFORM)
|
||||
PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
|
||||
|
||||
if (i != NULL && i->pic == root_pic)
|
||||
PIC_BIND(i->pic, i->intline, i->cpu);
|
||||
|
||||
if (i->event != NULL)
|
||||
PIC_ENABLE(i->pic, i->intline, vector);
|
||||
}
|
||||
|
||||
@ -83,7 +83,7 @@ openpic_set_priority(struct openpic_softc *sc, int pri)
|
||||
}
|
||||
|
||||
int
|
||||
openpic_attach(device_t dev)
|
||||
openpic_common_attach(device_t dev, uint32_t node)
|
||||
{
|
||||
struct openpic_softc *sc;
|
||||
u_int cpu, ipi, irq;
|
||||
@ -217,7 +217,7 @@ openpic_attach(device_t dev)
|
||||
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
|
||||
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
|
||||
|
||||
powerpc_register_pic(dev, sc->sc_nirq);
|
||||
powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
|
||||
|
||||
/* If this is not a cascaded PIC, it must be the root PIC */
|
||||
if (sc->sc_intr == NULL)
|
||||
@ -285,7 +285,6 @@ openpic_dispatch(device_t dev, struct trapframe *tf)
|
||||
cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
while (1) {
|
||||
vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
|
||||
vector &= OPENPIC_VECTOR_MASK;
|
||||
|
||||
@ -66,10 +66,6 @@ METHOD void ipi {
|
||||
u_int cpu;
|
||||
};
|
||||
|
||||
METHOD uint32_t id {
|
||||
device_t dev;
|
||||
};
|
||||
|
||||
METHOD void mask {
|
||||
device_t dev;
|
||||
u_int irq;
|
||||
|
||||
@ -54,7 +54,6 @@ static void ps3pic_eoi(device_t, u_int);
|
||||
static void ps3pic_ipi(device_t, u_int);
|
||||
static void ps3pic_mask(device_t, u_int);
|
||||
static void ps3pic_unmask(device_t, u_int);
|
||||
static uint32_t ps3pic_id(device_t dev);
|
||||
|
||||
struct ps3pic_softc {
|
||||
uint64_t *bitmap_thread0;
|
||||
@ -76,7 +75,6 @@ static device_method_t ps3pic_methods[] = {
|
||||
DEVMETHOD(pic_dispatch, ps3pic_dispatch),
|
||||
DEVMETHOD(pic_enable, ps3pic_enable),
|
||||
DEVMETHOD(pic_eoi, ps3pic_eoi),
|
||||
DEVMETHOD(pic_id, ps3pic_id),
|
||||
DEVMETHOD(pic_ipi, ps3pic_ipi),
|
||||
DEVMETHOD(pic_mask, ps3pic_mask),
|
||||
DEVMETHOD(pic_unmask, ps3pic_unmask),
|
||||
@ -146,9 +144,7 @@ ps3pic_attach(device_t dev)
|
||||
sc->sc_ipi_outlet[1], 0);
|
||||
#endif
|
||||
|
||||
powerpc_register_pic(dev, sc->sc_ipi_outlet[0]);
|
||||
root_pic = dev; /* PS3s have only one PIC */
|
||||
|
||||
powerpc_register_pic(dev, 0, sc->sc_ipi_outlet[0], 1, FALSE);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -245,10 +241,3 @@ ps3pic_unmask(device_t dev, u_int irq)
|
||||
lv1_did_update_interrupt_mask(ppe, 0);
|
||||
lv1_did_update_interrupt_mask(ppe, 1);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
ps3pic_id(device_t dev)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
@ -62,11 +62,12 @@ __FBSDID("$FreeBSD$");
|
||||
* PSIM IOBus interface
|
||||
*/
|
||||
static int openpic_iobus_probe(device_t);
|
||||
static int openpic_iobus_attach(device_t);
|
||||
|
||||
static device_method_t openpic_iobus_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, openpic_iobus_probe),
|
||||
DEVMETHOD(device_attach, openpic_attach),
|
||||
DEVMETHOD(device_attach, openpic_iobus_attach),
|
||||
|
||||
/* PIC interface */
|
||||
DEVMETHOD(pic_config, openpic_config),
|
||||
@ -109,3 +110,10 @@ openpic_iobus_probe(device_t dev)
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
openpic_iobus_attach(device_t dev)
|
||||
{
|
||||
|
||||
return (openpic_common_attach(dev, 0));
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user