Add Attansic/Atheros F1 PHY driver.
This commit is contained in:
Pyun YongHyeon
parent
9097a8e66e
commit
d1307e812e
413
sys/dev/mii/atphy.c
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413
sys/dev/mii/atphy.c
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/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the Attansic/Atheros F1 10/100/1000 PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/atphyreg.h>
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#include "miibus_if.h"
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static int atphy_probe(device_t);
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static int atphy_attach(device_t);
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struct atphy_softc {
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struct mii_softc mii_sc;
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int mii_oui;
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int mii_model;
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int mii_rev;
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};
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static device_method_t atphy_methods[] = {
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/* Device interface. */
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DEVMETHOD(device_probe, atphy_probe),
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DEVMETHOD(device_attach, atphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ NULL, NULL }
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};
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static devclass_t atphy_devclass;
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static driver_t atphy_driver = {
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"atphy",
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atphy_methods,
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sizeof(struct atphy_softc)
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};
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DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
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static int atphy_service(struct mii_softc *, struct mii_data *, int);
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static void atphy_status(struct mii_softc *);
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static void atphy_reset(struct mii_softc *);
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static uint16_t atphy_anar(struct ifmedia_entry *);
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static int atphy_auto(struct mii_softc *);
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static const struct mii_phydesc atphys[] = {
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MII_PHY_DESC(ATHEROS, F1),
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MII_PHY_END
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};
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static int
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atphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
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}
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static int
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atphy_attach(device_t dev)
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{
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struct atphy_softc *asc;
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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asc = device_get_softc(dev);
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sc = &asc->mii_sc;
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = atphy_service;
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sc->mii_pdata = mii;
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sc->mii_anegticks = MII_ANEGTICKS_GIGE;
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mii->mii_instance++;
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asc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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asc->mii_model = MII_MODEL(ma->mii_id2);
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asc->mii_rev = MII_REV(ma->mii_id2);
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if (bootverbose)
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device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
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asc->mii_oui, asc->mii_model, asc->mii_rev);
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atphy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t anar, bmcr, bmsr;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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bmcr = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
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IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
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atphy_auto(sc);
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break;
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}
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bmcr = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_100_TX:
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bmcr = BMCR_S100;
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break;
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case IFM_10_T:
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bmcr = BMCR_S10;
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break;
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case IFM_NONE:
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bmcr = PHY_READ(sc, MII_BMCR);
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/*
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* XXX
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* Due to an unknown reason powering down PHY resulted
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* in unexpected results such as inaccessbility of
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* hardware of freshly rebooted system. Disable
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* powering down PHY until I got more information for
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* Attansic/Atheros PHY hardwares.
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*/
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
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goto done;
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default:
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return (EINVAL);
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}
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anar = atphy_anar(ife);
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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bmcr |= BMCR_FDX;
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/* Enable pause. */
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anar |= (3 << 10);
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}
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if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
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EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, MII_100T2CR, 0);
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PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
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/*
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* Reset the PHY so all changes take effect.
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*/
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET);
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done:
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0;
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break;
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}
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/*
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* check for link.
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* Read the status register twice; BMSR_LINK is latch-low.
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*/
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (bmsr & BMSR_LINK) {
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sc->mii_ticks = 0;
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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if (sc->mii_ticks <= sc->mii_anegticks)
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return (0);
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sc->mii_ticks = 0;
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atphy_auto(sc);
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break;
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}
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/* Update the media status. */
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atphy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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atphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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uint32_t bmsr, bmcr, ssr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if ((bmsr & BMSR_LINK) != 0)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if ((bmcr & BMCR_ISO) != 0) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if ((bmcr & BMCR_LOOP) != 0)
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mii->mii_media_active |= IFM_LOOP;
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ssr = PHY_READ(sc, ATPHY_SSR);
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if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch (ssr & ATPHY_SSR_SPEED_MASK) {
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case ATPHY_SSR_1000MBS:
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mii->mii_media_active |= IFM_1000_T;
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/*
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* atphy(4) got a valid link so reset mii_ticks.
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* Resetting mii_ticks is needed in order to
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* detect link loss after auto-negotiation.
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*/
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sc->mii_ticks = 0;
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break;
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case ATPHY_SSR_100MBS:
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mii->mii_media_active |= IFM_100_TX;
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sc->mii_ticks = 0;
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break;
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case ATPHY_SSR_10MBS:
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mii->mii_media_active |= IFM_10_T;
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sc->mii_ticks = 0;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if ((ssr & ATPHY_SSR_DUPLEX) != 0)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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/* XXX Master/Slave, Flow-control */
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}
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static void
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atphy_reset(struct mii_softc *sc)
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{
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struct atphy_softc *asc;
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uint32_t reg;
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int i;
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asc = (struct atphy_softc *)sc;
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/* Take PHY out of power down mode. */
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PHY_WRITE(sc, 29, 0x29);
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PHY_WRITE(sc, 30, 0);
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reg = PHY_READ(sc, ATPHY_SCR);
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/* Enable automatic crossover. */
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reg |= ATPHY_SCR_AUTO_X_MODE;
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/* Disable power down. */
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reg &= ~ATPHY_SCR_MAC_PDOWN;
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/* Enable CRS on Tx. */
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reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
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/* Auto correction for reversed cable polarity. */
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reg |= ATPHY_SCR_POLARITY_REVERSAL;
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PHY_WRITE(sc, ATPHY_SCR, reg);
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/* Workaround F1 bug to reset phy. */
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atphy_auto(sc);
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for (i = 0; i < 1000; i++) {
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DELAY(1);
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if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
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break;
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}
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}
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static uint16_t
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atphy_anar(struct ifmedia_entry *ife)
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{
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uint16_t anar;
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anar = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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return (anar);
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case IFM_1000_T:
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return (anar);
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case IFM_100_TX:
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anar |= ANAR_TX;
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break;
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case IFM_10_T:
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anar |= ANAR_10;
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break;
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default:
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return (0);
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}
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
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anar |= ANAR_TX_FD;
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else
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anar |= ANAR_10_FD;
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}
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return (anar);
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}
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static int
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atphy_auto(struct mii_softc *sc)
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{
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uint16_t anar;
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anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities);
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PHY_WRITE(sc, MII_ANAR, anar | (3 << 10) | ANAR_CSMA);
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if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
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GTCR_ADV_1000THDX);
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PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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return (EJUSTRETURN);
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}
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63
sys/dev/mii/atphyreg.h
Normal file
63
sys/dev/mii/atphyreg.h
Normal file
@ -0,0 +1,63 @@
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/*-
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* Copyright (c) 2008, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_ATPHYREG_H_
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#define _DEV_MII_ATPHYREG_H_
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/*
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* Registers for the Attansic/Atheros Gigabit PHY.
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*/
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/* Special Control Register */
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#define ATPHY_SCR 0x10
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#define ATPHY_SCR_JABBER_DISABLE 0x0001
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#define ATPHY_SCR_POLARITY_REVERSAL 0x0002
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#define ATPHY_SCR_SQE_TEST 0x0004
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#define ATPHY_SCR_MAC_PDOWN 0x0008
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#define ATPHY_SCR_CLK125_DISABLE 0x0010
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#define ATPHY_SCR_MDI_MANUAL_MODE 0x0000
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#define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020
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#define ATPHY_SCR_AUTO_X_1000T 0x0040
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#define ATPHY_SCR_AUTO_X_MODE 0x0060
|
||||
#define ATPHY_SCR_10BT_EXT_ENABLE 0x0080
|
||||
#define ATPHY_SCR_MII_5BIT_ENABLE 0x0100
|
||||
#define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200
|
||||
#define ATPHY_SCR_FORCE_LINK_GOOD 0x0400
|
||||
#define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800
|
||||
|
||||
/* Special Status Register. */
|
||||
#define ATPHY_SSR 0x11
|
||||
#define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800
|
||||
#define ATPHY_SSR_DUPLEX 0x2000
|
||||
#define ATPHY_SSR_SPEED_MASK 0xC000
|
||||
#define ATPHY_SSR_10MBS 0x0000
|
||||
#define ATPHY_SSR_100MBS 0x4000
|
||||
#define ATPHY_SSR_1000MBS 0x8000
|
||||
|
||||
#endif /* _DEV_MII_ATPHYREG_H_ */
|
||||
@ -51,6 +51,7 @@ $FreeBSD$
|
||||
|
||||
oui ALTIMA 0x0010a9 Altima Communications
|
||||
oui AMD 0x00001a Advanced Micro Devices
|
||||
oui ATHEROS 0x001374 Atheros Communications
|
||||
oui BROADCOM 0x001018 Broadcom Corporation
|
||||
oui BROADCOM2 0x000af7 Broadcom Corporation
|
||||
oui CICADA 0x0003F1 Cicada Semiconductor
|
||||
@ -113,6 +114,9 @@ model AMD 79c973phy 0x0036 Am79c973 internal PHY
|
||||
model AMD 79c978 0x0039 Am79c978 HomePNA PHY
|
||||
model xxAMD 79C873 0x0000 Am79C873/DM9101 10/100 media interface
|
||||
|
||||
/* Atheros Communications/Attansic PHYs. */
|
||||
model ATHEROS F1 0x0001 Atheros F1 10/100/1000 PHY
|
||||
|
||||
/* Broadcom Corp. PHYs. */
|
||||
model BROADCOM 3C905B 0x0012 3c905B 10/100 internal PHY
|
||||
model BROADCOM 3C905C 0x0017 3c905C 10/100 internal PHY
|
||||
|
||||
Loading…
Reference in New Issue
Block a user