Fix offset handling
MFC after: 1 week
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ac4eceb715
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d19f2a3393
@ -403,8 +403,8 @@ static inline int r600_cs_packet3(struct drm_radeon_cs_parser *parser, uint32_t
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DRM_ERROR("bad DRAW_INDEX\n");
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break;
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}
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ib_chunk->kdata[offset_dw + 1] = (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 2] = (upper_32_bits(offset) & 0xff);
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ib_chunk->kdata[offset_dw + 1] += (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 2] += (upper_32_bits(offset) & 0xff);
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break;
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case R600_IT_DRAW_INDEX_AUTO:
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//DRM_INFO("R600_IT_DRAW_INDEX_AUTO\n");
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@ -433,8 +433,8 @@ static inline int r600_cs_packet3(struct drm_radeon_cs_parser *parser, uint32_t
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DRM_ERROR("bad WAIT_REG_MEM\n");
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break;
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}
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ib_chunk->kdata[offset_dw + 2] = (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 3] = (upper_32_bits(offset) & 0xff);
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ib_chunk->kdata[offset_dw + 2] += (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff);
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}
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if (ret)
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DRM_ERROR("bad WAIT_REG_MEM\n");
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@ -469,7 +469,7 @@ static inline int r600_cs_packet3(struct drm_radeon_cs_parser *parser, uint32_t
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break;
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}
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ib_chunk->kdata[offset_dw + 2] += (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 3] |= (upper_32_bits(offset) & 0xff);
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ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff);
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}
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if (ret)
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DRM_ERROR("bad EVENT_WRITE\n");
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@ -488,7 +488,7 @@ static inline int r600_cs_packet3(struct drm_radeon_cs_parser *parser, uint32_t
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break;
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}
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ib_chunk->kdata[offset_dw + 2] += (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + 3] |= (upper_32_bits(offset) & 0xff);
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ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff);
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break;
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case R600_IT_SET_CONFIG_REG:
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//DRM_INFO("R600_IT_SET_CONFIG_REG\n");
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@ -628,7 +628,7 @@ static inline int r600_cs_packet3(struct drm_radeon_cs_parser *parser, uint32_t
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if (ret)
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break;
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ib_chunk->kdata[offset_dw + (i * 7) + 0 + 2] += (offset & 0xffffffff);
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ib_chunk->kdata[offset_dw + (i * 7) + 2 + 2] |= (upper_32_bits(offset) & 0xff);
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ib_chunk->kdata[offset_dw + (i * 7) + 2 + 2] += (upper_32_bits(offset) & 0xff);
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break;
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}
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if (ret)
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