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powerpc: Add support for additional FSCR-managed facilities

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Add support to enable, save, and restore the following facilities:
* Target Address Register (bctar) -- seemingly just another register to
  branch to.
* Event-based branching -- an interrupt-like userspace event handler
  subsystem.
* Load-monitored facility -- A facility that allows monitoring a range of
  physical memory, and triggering an event on access.  Targeted to garbage
  collection software features.
This commit is contained in:
Justin Hibbits 2019-04-27 22:30:22 +00:00
parent 3eb5d5dd25
commit d1d73b0e27
5 changed files with 100 additions and 13 deletions
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12
sys/powerpc/include/pcb.h
View File

@ -48,6 +48,7 @@ struct pcb {
register_t pcb_lr; /* link register */
register_t pcb_dscr; /* dscr value */
register_t pcb_fscr;
register_t pcb_tar;
struct pmap *pcb_pm; /* pmap of our vmspace */
jmp_buf *pcb_onfault; /* For use during
copyin/copyout */
@ -81,6 +82,17 @@ struct pcb {
uint64_t texasr;
uint64_t tfiar;
} pcb_htm;
struct ebb {
uint64_t ebbhr;
uint64_t ebbrr;
uint64_t bescr;
} pcb_ebb;
struct lmon {
uint64_t lmrr;
uint64_t lmser;
} pcb_lm;
union {
struct {

13
sys/powerpc/include/spr.h
View File

@ -135,13 +135,14 @@
#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
#define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */
#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
#define FSCR_SCV 0x0000000000001000ULL /* scv instruction available */
#define FSCR_LM 0x0000000000000800ULL /* Load monitored facilities available */
#define FSCR_MSGP 0x0000000000000400ULL /* msgsndp and SPRs available */
#define FSCR_TAR 0x0000000000000100ULL /* TAR register available */
#define FSCR_EBB 0x0000000000000080ULL /* Event-based branch available */
#define FSCR_DSCR 0x0000000000000004ULL /* DSCR available in PR state */
#define FSCR_SCV 0x0000000000001000 /* scv instruction available */
#define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */
#define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */
#define FSCR_TAR 0x0000000000000100 /* TAR register available */
#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */
#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */
#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */

8
sys/powerpc/powerpc/genassym.c
View File

@ -197,6 +197,7 @@ ASSYM(PCB_CONTEXT, offsetof(struct pcb, pcb_context));
ASSYM(PCB_CR, offsetof(struct pcb, pcb_cr));
ASSYM(PCB_DSCR, offsetof(struct pcb, pcb_dscr));
ASSYM(PCB_FSCR, offsetof(struct pcb, pcb_fscr));
ASSYM(PCB_TAR, offsetof(struct pcb, pcb_tar));
ASSYM(PCB_SP, offsetof(struct pcb, pcb_sp));
ASSYM(PCB_TOC, offsetof(struct pcb, pcb_toc));
ASSYM(PCB_LR, offsetof(struct pcb, pcb_lr));
@ -212,6 +213,13 @@ ASSYM(PCB_BOOKE_DBCR0, offsetof(struct pcb, pcb_cpu.booke.dbcr0));
ASSYM(PCB_VSCR, offsetof(struct pcb, pcb_vec.vscr));
ASSYM(PCB_EBB_EBBHR, offsetof(struct pcb, pcb_ebb.ebbhr));
ASSYM(PCB_EBB_EBBRR, offsetof(struct pcb, pcb_ebb.ebbrr));
ASSYM(PCB_EBB_BESCR, offsetof(struct pcb, pcb_ebb.bescr));
ASSYM(PCB_LMON_LMRR, offsetof(struct pcb, pcb_lm.lmrr));
ASSYM(PCB_LMON_LMSER, offsetof(struct pcb, pcb_lm.lmser));
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));

42
sys/powerpc/powerpc/swtch64.S
View File

@ -134,6 +134,27 @@ ENTRY(cpu_switch)
beq 1f
mfspr %r6, SPR_FSCR
std %r6, PCB_FSCR(%r17)
save_ebb:
andi. %r0, %r6, FSCR_EBB
beq save_lm
mfspr %r7, SPR_EBBHR
std %r7, PCB_EBB_EBBHR(%r17)
mfspr %r7, SPR_EBBRR
std %r7, PCB_EBB_EBBRR(%r17)
mfspr %r7, SPR_BESCR
std %r7, PCB_EBB_BESCR(%r17)
save_lm:
andi. %r0, %r6, FSCR_LM
beq save_tar
mfspr %r7, SPR_LMRR
std %r7, PCB_LMON_LMRR(%r17)
mfspr %r7, SPR_LMSER
std %r7, PCB_LMON_LMSER(%r17)
save_tar:
andi. %r0, %r6, FSCR_TAR
beq 1f
mfspr %r7, SPR_TAR
std %r7, PCB_TAR(%r17)
1:
andi. %r7, %r18, PCB_CDSCR
beq .L0
@ -223,6 +244,27 @@ blocked_loop:
beq .L4
ld %r7, PCB_FSCR(%r17) /* Load the FSCR register*/
mtspr SPR_FSCR, %r7
restore_ebb:
andi. %r0, %r7, FSCR_EBB
beq restore_lm
ld %r6, PCB_EBB_EBBHR(%r17)
mtspr SPR_EBBHR, %r6
ld %r6, PCB_EBB_EBBRR(%r17)
mtspr SPR_EBBRR, %r6
ld %r6, PCB_EBB_BESCR(%r17)
mtspr SPR_BESCR, %r6
restore_lm:
andi. %r0, %r7, FSCR_LM
beq restore_tar
ld %r6, PCB_LMON_LMRR(%r17)
mtspr SPR_LMRR, %r6
ld %r6, PCB_LMON_LMSER(%r17)
mtspr SPR_LMSER, %r6
restore_tar:
andi. %r0, %r7, FSCR_TAR
beq .L4
ld %r6, PCB_TAR(%r17)
mtspr SPR_TAR, %r6
/* thread to restore is in r3 */
.L4:

38
sys/powerpc/powerpc/trap.c
View File

@ -305,17 +305,41 @@ trap(struct trapframe *frame)
case EXC_FAC:
fscr = mfspr(SPR_FSCR);
if ((fscr & FSCR_IC_MASK) == FSCR_IC_HTM) {
CTR0(KTR_TRAP, "Hardware Transactional Memory subsystem disabled");
} else if ((fscr & FSCR_IC_MASK) == FSCR_IC_DSCR) {
switch (fscr & FSCR_IC_MASK) {
case FSCR_IC_HTM:
CTR0(KTR_TRAP,
"Hardware Transactional Memory subsystem disabled");
sig = SIGILL;
ucode = ILL_ILLOPC;
break;
case FSCR_IC_DSCR:
td->td_pcb->pcb_flags |= PCB_CFSCR | PCB_CDSCR;
fscr &= ~FSCR_IC_MASK;
mtspr(SPR_FSCR, fscr | FSCR_DSCR);
fscr |= FSCR_DSCR;
mtspr(SPR_DSCR, 0);
break;
case FSCR_IC_EBB:
td->td_pcb->pcb_flags |= PCB_CFSCR;
fscr |= FSCR_EBB;
mtspr(SPR_EBBHR, 0);
mtspr(SPR_EBBRR, 0);
mtspr(SPR_BESCR, 0);
break;
case FSCR_IC_TAR:
td->td_pcb->pcb_flags |= PCB_CFSCR;
fscr |= FSCR_TAR;
mtspr(SPR_TAR, 0);
break;
case FSCR_IC_LM:
td->td_pcb->pcb_flags |= PCB_CFSCR;
fscr |= FSCR_LM;
mtspr(SPR_LMRR, 0);
mtspr(SPR_LMSER, 0);
break;
default:
sig = SIGILL;
ucode = ILL_ILLOPC;
}
sig = SIGILL;
ucode = ILL_ILLOPC;
mtspr(SPR_FSCR, fscr & ~FSCR_IC_MASK);
break;
case EXC_HEA:
sig = SIGILL;