Minor tweaks to names and comments now that I understand what's going
on better.
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5587b55c63
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d2adb03381
@ -190,10 +190,10 @@ wi_pci_attach(device_t dev)
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sc->wi_bmemhandle = rman_get_bushandle(sc->mem);
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/*
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* From Linux driver:
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* Write COR to enable PC card
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* This is a subset of the protocol that the pccard bus code
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* would do.
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* would do. In theory, we should parse the CIS to find the
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* COR offset. In practice, the COR_OFFSET is always 0x3e0.
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*/
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CSM_WRITE_1(sc, WI_COR_OFFSET, WI_COR_VALUE);
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reg = CSM_READ_1(sc, WI_COR_OFFSET);
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@ -208,10 +208,10 @@ wi_pci_attach(device_t dev)
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if (error)
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return (error);
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CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0080);
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CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET);
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DELAY(250000);
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CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0000);
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CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000);
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DELAY(500000);
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timeout=2000000;
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@ -220,7 +220,7 @@ wi_pci_attach(device_t dev)
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DELAY(10);
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if (timeout == 0) {
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device_printf(dev, "couldn't reset prism2.5 core.\n");
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device_printf(dev, "couldn't reset prism pci core.\n");
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wi_free(dev);
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return(ENXIO);
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}
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@ -51,7 +51,8 @@
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#define WI_LOCAL_INTEN 0x40
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#define WI_HFA384X_SWSUPPORT0_OFF 0x28
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#define WI_PRISM2STA_MAGIC 0x4A2D
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#define WI_HFA384X_PCICOR_OFF 0x26
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#define WI_PCICOR_OFF 0x26
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#define WI_PCICOR_RESET 0x0080
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/* Default port: 0 (only 0 exists on stations) */
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#define WI_DEFAULT_PORT WI_PORT0
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@ -330,7 +331,7 @@
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#define WI_HCR_HOLD 0x000f
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#define WI_HCR_EEHOLD 0x00ce
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#define WI_COR_OFFSET 0x3e0 /* OK for PCI, must be bogus for pccard */
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#define WI_COR_OFFSET 0x3e0 /* OK for PCI, default COR for Prism PC Card */
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#define WI_COR_VALUE 0x41
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/*
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@ -430,6 +431,10 @@ struct wi_ver {
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#define WI_NIC_P3_PCMCIA_ATS_ID 0x801D
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#define WI_NIC_P3_PCMCIA_STR "RF:PRISM3(PCMCIA)"
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#define WI_NIC_P3_USB_AMD_ID 0x801E
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#define WI_NIC_P3_USB_SST_ID 0x801F
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#define WI_NIC_P3_USB_ATL_ID 0x8020
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#define WI_NIC_P3_MINI_AMD_ID 0x8021 /* Prism3 Mini-PCI */
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#define WI_NIC_P3_MINI_SST_ID 0x8022
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#define WI_NIC_P3_MINI_ATL_ID 0x8023
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