Use pci_get_max_read_req() and pci_set_max_read_req() to set maximim
read request size.
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@ -421,7 +421,6 @@ static uint32_t bge_readreg_ind(struct bge_softc *, int);
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#endif
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static void bge_writemem_direct(struct bge_softc *, int, int);
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static void bge_writereg_ind(struct bge_softc *, int, int);
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static void bge_set_max_readrq(struct bge_softc *);
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static int bge_miibus_readreg(device_t, int, int);
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static int bge_miibus_writereg(device_t, int, int, int);
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@ -561,32 +560,6 @@ bge_writemem_ind(struct bge_softc *sc, int off, int val)
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pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
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}
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/*
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* PCI Express only
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*/
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static void
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bge_set_max_readrq(struct bge_softc *sc)
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{
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device_t dev;
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uint16_t val;
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dev = sc->bge_dev;
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val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
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if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
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BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
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if (bootverbose)
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device_printf(dev, "adjust device control 0x%04x ",
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val);
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val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
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val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
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pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
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val, 2);
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if (bootverbose)
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printf("-> 0x%04x\n", val);
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}
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}
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#ifdef notdef
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static uint32_t
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bge_readreg_ind(struct bge_softc *sc, int off)
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@ -2695,7 +2668,8 @@ bge_attach(device_t dev)
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*/
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sc->bge_flags |= BGE_FLAG_PCIE;
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sc->bge_expcap = reg;
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bge_set_max_readrq(sc);
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if (pci_get_max_read_req(dev) != 4096)
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pci_set_max_read_req(dev, 4096);
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} else {
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/*
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* Check if the device is in PCI-X Mode.
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