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The config space registers holding the upper 32-bits of the prefetchable

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memory area's base and limit are optional.  The low 4-bits of the "low"
prefetchable registers indicates whether or not a 32-bit or 64-bit
region is supported.  The PCI-PCI driver had been assuming that all bridges
supported a 64-bit region (and thus the two upper 32-bit registers).  Fix
the driver to only use those registers if the low 4-bits of the "low"
registers indicate that a 64-bit region is supported.  The PCI-PCI bridge
in the XBox happens to be a bridge that only supports a 32-bit region.

Reported by:	rink
MFC after:	1 week
This commit is contained in:
jhb 2008-08-20 18:29:59 +00:00
parent c2eea24c16
commit d2bd463b11
2 changed files with 19 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
sys/dev/pci/pci_pci.c
View File

@ -198,10 +198,22 @@ pcib_attach_common(device_t dev)
if (sc->command & PCIM_CMD_MEMEN) {
sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4),
pci_read_config(dev, PCIR_PMBASEL_1, 2));
sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4),
pci_read_config(dev, PCIR_PMLIMITL_1, 2));
iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
sc->pmembase = PCI_PPBMEMBASE(
pci_read_config(dev, PCIR_PMBASEH_1, 4),
pci_read_config(dev, PCIR_PMBASEL_1, 2));
else
sc->pmembase = PCI_PPBMEMBASE(0,
pci_read_config(dev, PCIR_PMBASEL_1, 2));
iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
sc->pmemlimit = PCI_PPBMEMLIMIT(
pci_read_config(dev, PCIR_PMLIMITH_1, 4),
pci_read_config(dev, PCIR_PMLIMITL_1, 2));
else
sc->pmemlimit = PCI_PPBMEMLIMIT(0,
pci_read_config(dev, PCIR_PMLIMITL_1, 2));
}
/*

3
sys/dev/pci/pcireg.h
View File

@ -180,6 +180,9 @@
#define PCIR_PMLIMITL_1 0x26
#define PCIR_PMBASEH_1 0x28
#define PCIR_PMLIMITH_1 0x2c
#define PCIM_BRPM_32 0x0
#define PCIM_BRPM_64 0x1
#define PCIM_BRPM_MASK 0xf
#define PCIR_BRIDGECTL_1 0x3e