This commit was generated by cvs2svn to compensate for changes in r111756,
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obrien
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@ -1,321 +0,0 @@
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/* Opcode table for the ARC.
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Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
GNU General Public License for more details.
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||||
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You should have received a copy of the GNU General Public License
|
||||
along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* List of the various cpu types.
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The tables currently use bit masks to say whether the instruction or
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whatever is supported by a particular cpu. This lets us have one entry
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apply to several cpus.
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The `base' cpu must be 0. The cpu type is treated independently of
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endianness. The complete `mach' number includes endianness.
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These values are internal to opcodes/bfd/binutils/gas. */
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#define ARC_MACH_5 0
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#define ARC_MACH_6 1
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#define ARC_MACH_7 2
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#define ARC_MACH_8 4
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/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */
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#define ARC_MACH_BIG 16
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/* Mask of number of bits necessary to record cpu type. */
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#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
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/* Mask of number of bits necessary to record cpu type + endianness. */
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#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
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/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */
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typedef unsigned int arc_insn;
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struct arc_opcode {
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char *syntax; /* syntax of insn */
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unsigned long mask, value; /* recognize insn if (op&mask) == value */
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int flags; /* various flag bits */
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/* Values for `flags'. */
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/* Return CPU number, given flag bits. */
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#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* Return MACH number, given flag bits. */
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#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
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/* First opcode flag bit available after machine mask. */
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#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
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/* This insn is a conditional branch. */
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#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
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#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1)
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#define SYNTAX_LENGTH (SYNTAX_3OP )
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#define SYNTAX_2OP (SYNTAX_3OP << 1)
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#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1)
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#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
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#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1)
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#define I(x) (((x) & 31) << 27)
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#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
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#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
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#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
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#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
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/* These values are used to optimize assembly and disassembly. Each insn
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is on a list of related insns (same first letter for assembly, same
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insn code for disassembly). */
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struct arc_opcode *next_asm; /* Next instr to try during assembly. */
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struct arc_opcode *next_dis; /* Next instr to try during disassembly. */
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/* Macros to create the hash values for the lists. */
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#define ARC_HASH_OPCODE(string) \
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((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
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#define ARC_HASH_ICODE(insn) \
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((unsigned int) (insn) >> 27)
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/* Macros to access `next_asm', `next_dis' so users needn't care about the
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underlying mechanism. */
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#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
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#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
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};
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/* this is an "insert at front" linked list per Metaware spec
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that new definitions override older ones. */
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struct arc_opcode *arc_ext_opcodes;
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struct arc_operand_value {
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char *name; /* eg: "eq" */
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short value; /* eg: 1 */
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unsigned char type; /* index into `arc_operands' */
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unsigned char flags; /* various flag bits */
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/* Values for `flags'. */
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/* Return CPU number, given flag bits. */
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#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* Return MACH number, given flag bits. */
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#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
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};
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struct arc_ext_operand_value {
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struct arc_ext_operand_value *next;
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struct arc_operand_value operand;
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} *arc_ext_operands;
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struct arc_operand {
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/* One of the insn format chars. */
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unsigned char fmt;
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/* The number of bits in the operand (may be unused for a modifier). */
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unsigned char bits;
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/* How far the operand is left shifted in the instruction, or
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the modifier's flag bit (may be unused for a modifier. */
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unsigned char shift;
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/* Various flag bits. */
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int flags;
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/* Values for `flags'. */
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/* This operand is a suffix to the opcode. */
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#define ARC_OPERAND_SUFFIX 1
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define ARC_OPERAND_RELATIVE_BRANCH 2
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define ARC_OPERAND_ABSOLUTE_BRANCH 4
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/* This operand is an address. The disassembler
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prints these symbolically if possible. */
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#define ARC_OPERAND_ADDRESS 8
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/* This operand is a long immediate value. */
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#define ARC_OPERAND_LIMM 0x10
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/* This operand takes signed values. */
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#define ARC_OPERAND_SIGNED 0x20
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/* This operand takes signed values, but also accepts a full positive
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range of values. That is, if bits is 16, it takes any value from
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-0x8000 to 0xffff. */
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#define ARC_OPERAND_SIGNOPT 0x40
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define ARC_OPERAND_NEGATIVE 0x80
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/* This operand doesn't really exist. The program uses these operands
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in special ways. */
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#define ARC_OPERAND_FAKE 0x100
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/* separate flags operand for j and jl instructions */
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#define ARC_OPERAND_JUMPFLAGS 0x200
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/* allow warnings and errors to be issued after call to insert_xxxxxx */
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#define ARC_OPERAND_WARN 0x400
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#define ARC_OPERAND_ERROR 0x800
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/* this is a load operand */
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#define ARC_OPERAND_LOAD 0x8000
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/* this is a store operand */
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#define ARC_OPERAND_STORE 0x10000
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/* Modifier values. */
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/* A dot is required before a suffix. Eg: .le */
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#define ARC_MOD_DOT 0x1000
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/* A normal register is allowed (not used, but here for completeness). */
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#define ARC_MOD_REG 0x2000
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/* An auxiliary register name is expected. */
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#define ARC_MOD_AUXREG 0x4000
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/* Sum of all ARC_MOD_XXX bits. */
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#define ARC_MOD_BITS 0x7000
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/* Non-zero if the operand type is really a modifier. */
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#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
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/* enforce read/write only register restrictions */
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#define ARC_REGISTER_READONLY 0x01
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#define ARC_REGISTER_WRITEONLY 0x02
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#define ARC_REGISTER_NOSHORT_CUT 0x04
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (p & ((1 << o->bits) - 1)) << o->shift;
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(I is the instruction which we are filling in, O is a pointer to
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this structure, and OP is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged.
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REG is non-NULL when inserting a register value. */
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arc_insn (*insert) PARAMS ((arc_insn insn,
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const struct arc_operand *operand, int mods,
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const struct arc_operand_value *reg, long value,
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const char **errmsg));
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & ARC_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(I is the instruction, O is a pointer to this structure, and OP
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed.
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INSN is a pointer to an array of two `arc_insn's. The first element is
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the insn, the second is the limm if present.
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Operands that have a printable form like registers and suffixes have
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their struct arc_operand_value pointer stored in OPVAL. */
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long (*extract) PARAMS ((arc_insn *insn,
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const struct arc_operand *operand,
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int mods, const struct arc_operand_value **opval,
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int *invalid));
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};
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/* Bits that say what version of cpu we have. These should be passed to
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arc_init_opcode_tables. At present, all there is is the cpu type. */
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/* CPU number, given value passed to `arc_init_opcode_tables'. */
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#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* MACH number, given value passed to `arc_init_opcode_tables'. */
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#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
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/* Special register values: */
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#define ARC_REG_SHIMM_UPDATE 61
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#define ARC_REG_SHIMM 63
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#define ARC_REG_LIMM 62
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/* Non-zero if REG is a constant marker. */
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#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
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/* Positions and masks of various fields: */
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#define ARC_SHIFT_REGA 21
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#define ARC_SHIFT_REGB 15
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#define ARC_SHIFT_REGC 9
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#define ARC_MASK_REG 63
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/* Delay slot types. */
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#define ARC_DELAY_NONE 0 /* no delay slot */
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#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
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#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
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/* Non-zero if X will fit in a signed 9 bit field. */
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#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
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extern const struct arc_operand arc_operands[];
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extern const int arc_operand_count;
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extern struct arc_opcode arc_opcodes[];
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extern const int arc_opcodes_count;
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extern const struct arc_operand_value arc_suffixes[];
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extern const int arc_suffixes_count;
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extern const struct arc_operand_value arc_reg_names[];
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extern const int arc_reg_names_count;
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extern unsigned char arc_operand_map[];
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/* Utility fns in arc-opc.c. */
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int arc_get_opcode_mach PARAMS ((int, int));
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/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */
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void arc_opcode_init_tables PARAMS ((int));
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void arc_opcode_init_insert PARAMS ((void));
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void arc_opcode_init_extract PARAMS ((void));
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const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
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const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
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int arc_opcode_limm_p PARAMS ((long *));
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const struct arc_operand_value *arc_opcode_lookup_suffix
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PARAMS ((const struct arc_operand *type, int value));
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int arc_opcode_supported PARAMS ((const struct arc_opcode *));
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int arc_opval_supported PARAMS ((const struct arc_operand_value *));
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int arc_limm_fixup_adjust PARAMS ((arc_insn));
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int arc_insn_is_j PARAMS ((arc_insn));
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int arc_insn_not_jl PARAMS ((arc_insn));
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int arc_operand_type PARAMS ((int));
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struct arc_operand_value *get_ext_suffix PARAMS ((char *));
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int arc_get_noshortcut_flag PARAMS ((void));
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File diff suppressed because it is too large
Load Diff
@ -1,422 +0,0 @@
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/* Print GOULD NPL instructions for GDB, the GNU debugger.
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Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
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This file is part of GDB.
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GDB is free software; you can redistribute it and/or modify
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||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 1, or (at your option)
|
||||
any later version.
|
||||
|
||||
GDB is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GDB; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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||||
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struct gld_opcode
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{
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char *name;
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unsigned long opcode;
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unsigned long mask;
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char *args;
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||||
int length;
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||||
};
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||||
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/* We store four bytes of opcode for all opcodes because that
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is the most any of them need. The actual length of an instruction
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||||
is always at least 2 bytes, and at most four. The length of the
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||||
instruction is based on the opcode.
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||||
|
||||
The mask component is a mask saying which bits must match
|
||||
particular opcode in order for an instruction to be an instance
|
||||
of that opcode.
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||||
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||||
The args component is a string containing characters
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||||
that are used to format the arguments to the instruction. */
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||||
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||||
/* Kinds of operands:
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||||
r Register in first field
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R Register in second field
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||||
b Base register in first field
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||||
B Base register in second field
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||||
v Vector register in first field
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||||
V Vector register in first field
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||||
A Optional address register (base register)
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X Optional index register
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||||
I Immediate data (16bits signed)
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O Offset field (16bits signed)
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||||
h Offset field (15bits signed)
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||||
d Offset field (14bits signed)
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||||
S Shift count field
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||||
|
||||
any other characters are printed as is...
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||||
*/
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||||
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||||
/* The assembler requires that this array be sorted as follows:
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||||
all instances of the same mnemonic must be consecutive.
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||||
All instances of the same mnemonic with the same number of operands
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||||
must be consecutive.
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||||
*/
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||||
struct gld_opcode gld_opcodes[] =
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||||
{
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||||
{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
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||||
{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
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||||
{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
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||||
{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
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||||
{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
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{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
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{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
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||||
{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
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||||
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
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{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 },
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||||
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
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||||
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
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||||
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
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||||
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 },
|
||||
{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
|
||||
{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 },
|
||||
{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 },
|
||||
{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 },
|
||||
{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 },
|
||||
{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 },
|
||||
{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 },
|
||||
{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 },
|
||||
{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 },
|
||||
|
||||
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
|
||||
{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 },
|
||||
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
|
||||
{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 },
|
||||
|
||||
{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 },
|
||||
|
||||
{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 },
|
||||
{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 },
|
||||
{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 },
|
||||
{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 },
|
||||
{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
|
||||
{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
|
||||
{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 },
|
||||
|
||||
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 },
|
||||
|
||||
{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 },
|
||||
|
||||
{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
|
||||
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
|
||||
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
|
||||
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
|
||||
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
|
||||
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
|
||||
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
|
||||
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
|
||||
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
|
||||
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
|
||||
{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 },
|
||||
|
||||
{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 },
|
||||
|
||||
{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
|
||||
{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
|
||||
{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 },
|
||||
{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 },
|
||||
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 },
|
||||
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 },
|
||||
{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 },
|
||||
|
||||
{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 },
|
||||
|
||||
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 },
|
||||
{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 },
|
||||
|
||||
{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 },
|
||||
{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 },
|
||||
{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 },
|
||||
|
||||
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 },
|
||||
|
||||
{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 },
|
||||
{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 },
|
||||
|
||||
{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 },
|
||||
{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 },
|
||||
|
||||
{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 },
|
||||
{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 },
|
||||
{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 },
|
||||
{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 },
|
||||
{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 },
|
||||
{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 },
|
||||
{ "exr", 0xf8070000, 0xfc0f0000, "", 4 },
|
||||
{ "halt", 0x00000000, 0xfc0f0000, "", 2 },
|
||||
{ "wait", 0x00010000, 0xfc0f0000, "", 2 },
|
||||
{ "nop", 0x00020000, 0xfc0f0000, "", 2 },
|
||||
{ "eiae", 0x00030000, 0xfc0f0000, "", 2 },
|
||||
{ "efae", 0x000d0000, 0xfc0f0000, "", 2 },
|
||||
{ "diae", 0x000e0000, 0xfc0f0000, "", 2 },
|
||||
{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 },
|
||||
{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 },
|
||||
{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 },
|
||||
{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 },
|
||||
{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 },
|
||||
{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 },
|
||||
{ "attnio", 0x00050000, 0xfc0f0000, "", 2 },
|
||||
{ "fudit", 0x28080000, 0xfc0f0000, "", 2 },
|
||||
{ "break", 0x28090000, 0xfc0f0000, "", 2 },
|
||||
{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 },
|
||||
{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 },
|
||||
{ "block", 0x04060000, 0xfc0f0000, "", 2 },
|
||||
{ "unblock", 0x04070000, 0xfc0f0000, "", 2 },
|
||||
{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fq", 0x04080000, 0xfc0f0000, "r", 2 },
|
||||
{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 },
|
||||
{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 },
|
||||
{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 },
|
||||
{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 },
|
||||
{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 },
|
||||
{ "grun", 0x0c040000, 0xfc0f0000, "", 2 },
|
||||
{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
|
||||
|
||||
{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 },
|
||||
{ "trver", 0x28070000, 0xfc0f0000, "r", 2 },
|
||||
{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 },
|
||||
|
||||
{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 },
|
||||
};
|
||||
|
||||
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
|
||||
|
||||
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
|
||||
sizeof(gld_opcodes[0]);
|
||||
@ -1,282 +0,0 @@
|
||||
/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
|
||||
Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB.
|
||||
|
||||
GDB is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 1, or (at your option)
|
||||
any later version.
|
||||
|
||||
GDB is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GDB; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
struct gld_opcode
|
||||
{
|
||||
char *name;
|
||||
unsigned long opcode;
|
||||
unsigned long mask;
|
||||
char *args;
|
||||
int length;
|
||||
};
|
||||
|
||||
/* We store four bytes of opcode for all opcodes because that
|
||||
is the most any of them need. The actual length of an instruction
|
||||
is always at least 2 bytes, and at most four. The length of the
|
||||
instruction is based on the opcode.
|
||||
|
||||
The mask component is a mask saying which bits must match
|
||||
particular opcode in order for an instruction to be an instance
|
||||
of that opcode.
|
||||
|
||||
The args component is a string containing characters
|
||||
that are used to format the arguments to the instruction. */
|
||||
|
||||
/* Kinds of operands:
|
||||
r Register in first field
|
||||
R Register in second field
|
||||
b Base register in first field
|
||||
B Base register in second field
|
||||
v Vector register in first field
|
||||
V Vector register in first field
|
||||
A Optional address register (base register)
|
||||
X Optional index register
|
||||
I Immediate data (16bits signed)
|
||||
O Offset field (16bits signed)
|
||||
h Offset field (15bits signed)
|
||||
d Offset field (14bits signed)
|
||||
S Shift count field
|
||||
|
||||
any other characters are printed as is...
|
||||
*/
|
||||
|
||||
/* The assembler requires that this array be sorted as follows:
|
||||
all instances of the same mnemonic must be consecutive.
|
||||
All instances of the same mnemonic with the same number of operands
|
||||
must be consecutive.
|
||||
*/
|
||||
struct gld_opcode gld_opcodes[] =
|
||||
{
|
||||
{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 },
|
||||
{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 },
|
||||
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 },
|
||||
{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 },
|
||||
{ "bei", 0x00060000, 0xffff0000, "", 2 },
|
||||
{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 },
|
||||
{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 },
|
||||
{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 },
|
||||
{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 },
|
||||
{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 },
|
||||
{ "bsub", 0x5c080000, 0xff8f0000, "", 2 },
|
||||
{ "bsubm", 0x28080000, 0xfc080000, "", 4 },
|
||||
{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "call", 0x28080000, 0xfc0f0000, "", 2 },
|
||||
{ "callm", 0x5c080000, 0xff880000, "", 4 },
|
||||
{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 },
|
||||
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 },
|
||||
{ "cea", 0x000f0000, 0xffff0000, "", 2 },
|
||||
{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 },
|
||||
{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "dae", 0x000e0000, 0xffff0000, "", 2 },
|
||||
{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 },
|
||||
{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "di", 0xfc010000, 0xfc07ffff, "I", 4 },
|
||||
{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 },
|
||||
{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 },
|
||||
{ "eae", 0x00080000, 0xffff0000, "", 2 },
|
||||
{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 },
|
||||
{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 },
|
||||
{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 },
|
||||
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "es", 0x00040000, 0xfc7f0000, "r", 2 },
|
||||
{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 },
|
||||
{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 },
|
||||
{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 },
|
||||
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "halt", 0x00000000, 0xffff0000, "", 2 },
|
||||
{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 },
|
||||
{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 },
|
||||
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 },
|
||||
{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 },
|
||||
{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 },
|
||||
{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 },
|
||||
{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "nop", 0x00020000, 0xffff0000, "", 2 },
|
||||
{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 },
|
||||
{ "return", 0x280e0000, 0xfc7f0000, "", 2 },
|
||||
{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 },
|
||||
{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 },
|
||||
{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 },
|
||||
{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 },
|
||||
{ "sea", 0x000d0000, 0xffff0000, "", 2 },
|
||||
{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 },
|
||||
{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "sipu", 0x000a0000, 0xffff0000, "", 2 },
|
||||
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
|
||||
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
|
||||
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
|
||||
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
|
||||
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
|
||||
{ "smc", 0x04070000, 0xfc070000, "", 2 },
|
||||
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
|
||||
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
|
||||
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
|
||||
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
|
||||
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
|
||||
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
|
||||
{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 },
|
||||
{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 },
|
||||
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "svc", 0xc8060000, 0xffff0000, "", 4 },
|
||||
{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 },
|
||||
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
|
||||
{ "tccr", 0x28040000, 0xfc7f0000, "", 2 },
|
||||
{ "td", 0xfc050000, 0xfc070000, "r,f", 4 },
|
||||
{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 },
|
||||
{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 },
|
||||
{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 },
|
||||
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trcc", 0x28050000, 0xfc7f0000, "", 2 },
|
||||
{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 },
|
||||
{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "uei", 0x00070000, 0xffff0000, "", 2 },
|
||||
{ "wait", 0x00010000, 0xffff0000, "", 2 },
|
||||
{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 },
|
||||
{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
|
||||
{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 },
|
||||
{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
|
||||
{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 },
|
||||
{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 },
|
||||
{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 },
|
||||
{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 },
|
||||
{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 },
|
||||
};
|
||||
|
||||
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
|
||||
|
||||
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
|
||||
sizeof(gld_opcodes[0]);
|
||||
@ -1,11 +0,0 @@
|
||||
SCRIPT_NAME=elf
|
||||
OUTPUT_FORMAT="elf32-littlearc"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlearc"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigarc"
|
||||
TEXT_START_ADDR=0x0
|
||||
MAXPAGESIZE=0x1000
|
||||
NONPAGED_TEXT_START_ADDR=0x0
|
||||
ARCH=arc
|
||||
MACHINE=
|
||||
ENTRY=start
|
||||
#TEMPLATE_NAME=elf32
|
||||
@ -1,10 +0,0 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf32l4300.sh
|
||||
|
||||
EMBEDDED=yes
|
||||
. ${srcdir}/emulparams/elf32bmip.sh
|
||||
TEXT_START_ADDR=0xa0020000
|
||||
unset NONPAGED_TEXT_START_ADDR
|
||||
unset SHLIB_TEXT_START_ADDR
|
||||
EXECUTABLE_SYMBOLS='_DYNAMIC_LINK = 0;'
|
||||
DYNAMIC_LINK=false
|
||||
@ -1,36 +0,0 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf32b4300.sh elf32bsmip.sh elf32btsmip.sh elf32ebmip.sh elf32lmip.sh
|
||||
|
||||
SCRIPT_NAME=elf
|
||||
OUTPUT_FORMAT="elf32-bigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
TEXT_START_ADDR=0x0400000
|
||||
test -n "${EMBEDDED}" || DATA_ADDR=0x10000000
|
||||
MAXPAGESIZE=0x40000
|
||||
NONPAGED_TEXT_START_ADDR=0x0400000
|
||||
SHLIB_TEXT_START_ADDR=0x5ffe0000
|
||||
test -n "${EMBEDDED}" || TEXT_DYNAMIC=
|
||||
INITIAL_READONLY_SECTIONS="
|
||||
.reginfo ${RELOCATING-0} : { *(.reginfo) }
|
||||
"
|
||||
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
|
||||
OTHER_GOT_SYMBOLS='
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
'
|
||||
OTHER_SDATA_SECTIONS="
|
||||
.lit8 ${RELOCATING-0} : { *(.lit8) }
|
||||
.lit4 ${RELOCATING-0} : { *(.lit4) }
|
||||
"
|
||||
TEXT_START_SYMBOLS='_ftext = . ;'
|
||||
DATA_START_SYMBOLS='_fdata = . ;'
|
||||
OTHER_BSS_SYMBOLS='_fbss = .;'
|
||||
OTHER_SECTIONS='
|
||||
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
|
||||
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
|
||||
'
|
||||
ARCH=mips
|
||||
MACHINE=
|
||||
TEMPLATE_NAME=elf32
|
||||
EXTRA_EM_FILE=mipself
|
||||
GENERATE_SHLIB_SCRIPT=yes
|
||||
@ -1,71 +0,0 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf64bmip.sh elf64btsmip.sh
|
||||
|
||||
# This is an ELF platform.
|
||||
SCRIPT_NAME=elf
|
||||
|
||||
# Handle both big- and little-ended 32-bit MIPS objects.
|
||||
ARCH=mips
|
||||
OUTPUT_FORMAT="elf32-bigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_START_ADDR=0x10000000
|
||||
MAXPAGESIZE=0x100000
|
||||
ENTRY=__start
|
||||
|
||||
# GOT-related settings.
|
||||
OTHER_GOT_SYMBOLS='
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
'
|
||||
OTHER_SDATA_SECTIONS="
|
||||
.lit8 ${RELOCATING-0} : { *(.lit8) }
|
||||
.lit4 ${RELOCATING-0} : { *(.lit4) }
|
||||
.srdata ${RELOCATING-0} : { *(.srdata) }
|
||||
"
|
||||
|
||||
# Magic symbols.
|
||||
TEXT_START_SYMBOLS='_ftext = . ;'
|
||||
DATA_START_SYMBOLS='_fdata = . ;'
|
||||
OTHER_BSS_SYMBOLS='_fbss = .;'
|
||||
# IRIX6 defines these symbols. 0x34 is the size of the ELF header.
|
||||
EXECUTABLE_SYMBOLS="
|
||||
__dso_displacement = 0;
|
||||
__elf_header = ${TEXT_START_ADDR};
|
||||
__program_header_table = ${TEXT_START_ADDR} + 0x34;
|
||||
"
|
||||
|
||||
# There are often dynamic relocations against the .rodata section.
|
||||
# Setting DT_TEXTREL in the .dynamic section does not convince the
|
||||
# IRIX6 linker to permit relocations against the text segment.
|
||||
# Following the IRIX linker, we simply put .rodata in the data
|
||||
# segment.
|
||||
WRITABLE_RODATA=
|
||||
|
||||
OTHER_SECTIONS="
|
||||
.MIPS.events.text ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.events.text${RELOCATING+ .MIPS.events.gnu.linkonce.t*})
|
||||
}
|
||||
.MIPS.content.text ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.content.text${RELOCATING+ .MIPS.content.gnu.linkonce.t*})
|
||||
}
|
||||
.MIPS.events.data ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.events.data${RELOCATING+ .MIPS.events.gnu.linkonce.d*})
|
||||
}
|
||||
.MIPS.content.data ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.content.data${RELOCATING+ .MIPS.content.gnu.linkonce.d*})
|
||||
}
|
||||
.MIPS.events.rodata ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.events.rodata${RELOCATING+ .MIPS.events.gnu.linkonce.r*})
|
||||
}
|
||||
.MIPS.content.rodata ${RELOCATING-0} :
|
||||
{
|
||||
*(.MIPS.content.rodata${RELOCATING+ .MIPS.content.gnu.linkonce.r*})
|
||||
}"
|
||||
@ -1,2 +0,0 @@
|
||||
. ${srcdir}/emulparams/elf32bmip.sh
|
||||
ENTRY=__start
|
||||
@ -1,2 +0,0 @@
|
||||
EMBEDDED=yes
|
||||
. ${srcdir}/emulparams/elf32bmip.sh
|
||||
@ -1,2 +0,0 @@
|
||||
EMBEDDED=yes
|
||||
. ${srcdir}/emulparams/elf32lmip.sh
|
||||
@ -1,4 +0,0 @@
|
||||
. ${srcdir}/emulparams/elf32b4300.sh
|
||||
OUTPUT_FORMAT="elf32-littlemips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
@ -1,7 +0,0 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf32elmip.sh elf32lsmip.sh
|
||||
|
||||
. ${srcdir}/emulparams/elf32bmip.sh
|
||||
OUTPUT_FORMAT="elf32-littlemips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
@ -1,2 +0,0 @@
|
||||
. ${srcdir}/emulparams/elf32lmip.sh
|
||||
ENTRY=__start
|
||||
@ -1,12 +0,0 @@
|
||||
. ${srcdir}/emulparams/elf32bmipn32.sh
|
||||
OUTPUT_FORMAT="elf64-bigmips"
|
||||
BIG_OUTPUT_FORMAT="elf64-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf64-littlemips"
|
||||
ELFSIZE=64
|
||||
|
||||
# IRIX6 defines these symbols. 0x40 is the size of the ELF header.
|
||||
EXECUTABLE_SYMBOLS="
|
||||
__dso_displacement = 0;
|
||||
__elf_header = ${TEXT_START_ADDR};
|
||||
__program_header_table = ${TEXT_START_ADDR} + 0x40;
|
||||
"
|
||||
@ -1,8 +0,0 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# shl.sh
|
||||
|
||||
SCRIPT_NAME=sh
|
||||
OUTPUT_FORMAT="coff-sh"
|
||||
TEXT_START_ADDR=0x8000
|
||||
TARGET_PAGE_SIZE=128
|
||||
ARCH=sh
|
||||
@ -1,2 +0,0 @@
|
||||
. ${srcdir}/emulparams/sh.sh
|
||||
OUTPUT_FORMAT="coff-shl"
|
||||
@ -1,2 +0,0 @@
|
||||
. ${srcdir}/emulparams/shelf.sh
|
||||
OUTPUT_FORMAT="elf32-shl"
|
||||
@ -1,8 +0,0 @@
|
||||
SCRIPT_NAME=aout
|
||||
OUTPUT_FORMAT="a.out-i386"
|
||||
TEXT_START_ADDR=0x1020
|
||||
TARGET_PAGE_SIZE=0x1000
|
||||
SEGMENT_SIZE=0x400000
|
||||
NONPAGED_TEXT_START_ADDR=0x0
|
||||
ARCH=i386
|
||||
|
||||
Loading…
Reference in New Issue
Block a user