ixl: Update to 1.4.27-k.
Changes: Kevin Scott i40e-shared: Save off VSI resource count when updating VSI Anjali Singhai Jain i40e-shared: Expose some registers to program parser, FD and RSS logic Eric Joyner ixl: Fix errors in queue interrupt setup in MSIX mode. Shannon Nelson i40e-shared: implement and use rx ctl helper functions Shannon Nelson i40e-shared: don't use AQ calls from clear_hw Eric Joyner ixl: Use rx ctl read/write functions instead of register accesses in certain places. Shannon Nelson i40e-shared: add adminq commands for rx ctl registers Shannon Nelson i40e-shared: implement and use rx ctl helper functions Jeremiah Kyle i40e-shared: Corrected function name in comment block Deepthi Kavalur i40e-shared: correcting a HW capability display info Shannon Nelson i40e-shared: fixups for (Linux) upstream consistency Eric Joyner ixl: Only stop firmware's LLDP agent on older firmware versions. Differential Revision: https://reviews.freebsd.org/D6211 Reviewed by: sbruno, kmacy, jeffrey.e.pieper@intel.com MFC after: 2 weeks Sponsored by: Intel Corporation
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@ -44,8 +44,8 @@
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**/
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static INLINE bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
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{
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return (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase) ||
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desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update));
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return (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase)) ||
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(desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update));
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}
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/**
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@ -554,6 +554,24 @@ shutdown_arq_out:
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return ret_code;
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}
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/**
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* i40e_resume_aq - resume AQ processing from 0
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* @hw: pointer to the hardware structure
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**/
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static void i40e_resume_aq(struct i40e_hw *hw)
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{
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/* Registers are reset after PF reset */
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hw->aq.asq.next_to_use = 0;
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hw->aq.asq.next_to_clean = 0;
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i40e_config_asq_regs(hw);
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hw->aq.arq.next_to_use = 0;
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hw->aq.arq.next_to_clean = 0;
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i40e_config_arq_regs(hw);
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}
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/**
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* i40e_init_adminq - main initialization routine for Admin Queue
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* @hw: pointer to the hardware structure
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@ -567,10 +585,11 @@ shutdown_arq_out:
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**/
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enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
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{
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enum i40e_status_code ret_code;
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u16 eetrack_lo, eetrack_hi;
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u16 cfg_ptr, oem_hi, oem_lo;
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u16 eetrack_lo, eetrack_hi;
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enum i40e_status_code ret_code;
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int retry = 0;
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/* verify input for valid configuration */
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if ((hw->aq.num_arq_entries == 0) ||
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(hw->aq.num_asq_entries == 0) ||
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@ -579,8 +598,6 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
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ret_code = I40E_ERR_CONFIG;
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goto init_adminq_exit;
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}
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/* initialize spin locks */
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i40e_init_spinlock(&hw->aq.asq_spinlock);
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i40e_init_spinlock(&hw->aq.arq_spinlock);
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@ -681,8 +698,6 @@ enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
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i40e_shutdown_asq(hw);
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i40e_shutdown_arq(hw);
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/* destroy the spinlocks */
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i40e_destroy_spinlock(&hw->aq.asq_spinlock);
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i40e_destroy_spinlock(&hw->aq.arq_spinlock);
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@ -708,7 +723,6 @@ u16 i40e_clean_asq(struct i40e_hw *hw)
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desc = I40E_ADMINQ_DESC(*asq, ntc);
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details = I40E_ADMINQ_DETAILS(*asq, ntc);
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while (rd32(hw, hw->aq.asq.head) != ntc) {
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i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
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"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
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@ -899,7 +913,6 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
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*/
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if (i40e_asq_done(hw))
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break;
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/* ugh! delay while spin_lock */
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i40e_msec_delay(1);
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total_delay++;
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} while (total_delay < hw->aq.asq_cmd_timeout);
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@ -1098,16 +1111,3 @@ clean_arq_element_err:
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return ret_code;
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}
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void i40e_resume_aq(struct i40e_hw *hw)
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{
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/* Registers are reset after PF reset */
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hw->aq.asq.next_to_use = 0;
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hw->aq.asq.next_to_clean = 0;
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i40e_config_asq_regs(hw);
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hw->aq.arq.next_to_use = 0;
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hw->aq.arq.next_to_clean = 0;
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i40e_config_arq_regs(hw);
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}
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@ -159,8 +159,8 @@ static INLINE int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)
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}
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/* general information */
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#define I40E_AQ_LARGE_BUF 512
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#define I40E_ASQ_CMD_TIMEOUT 250 /* msecs */
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#define I40E_AQ_LARGE_BUF 512
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#define I40E_ASQ_CMD_TIMEOUT 250 /* msecs */
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void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
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u16 opcode);
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@ -154,6 +154,8 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_set_port_parameters = 0x0203,
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i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
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i40e_aqc_opc_set_switch_config = 0x0205,
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i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
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i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
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i40e_aqc_opc_add_vsi = 0x0210,
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i40e_aqc_opc_update_vsi_parameters = 0x0211,
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@ -700,6 +702,20 @@ struct i40e_aqc_set_switch_config {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
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/* Read Receive control registers (direct 0x0206)
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* Write Receive control registers (direct 0x0207)
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* used for accessing Rx control registers that can be
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* slow and need special handling when under high Rx load
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*/
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struct i40e_aqc_rx_ctl_reg_read_write {
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__le32 reserved1;
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__le32 address;
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__le32 reserved2;
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__le32 value;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
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/* Add VSI (indirect 0x0210)
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* this indirect command uses struct i40e_aqc_vsi_properties_data
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* as the indirect buffer (128 bytes)
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@ -853,7 +869,7 @@ struct i40e_aqc_vsi_properties_data {
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u8 up_enable_bits;
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u8 sched_reserved;
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/* outer up section */
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__le32 outer_up_table; /* same structure and defines as ingress table */
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__le32 outer_up_table; /* same structure and defines as ingress tbl */
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u8 cmd_reserved[8];
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/* last 32 bytes are written by FW */
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__le16 qs_handle[8];
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@ -1493,7 +1509,8 @@ struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
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u8 reserved1[28];
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};
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I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
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I40E_CHECK_STRUCT_LEN(0x40,
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i40e_aqc_configure_switching_comp_ets_bw_limit_data);
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/* Configure Switching Component Bandwidth Allocation per Tc
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* (indirect 0x0417)
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@ -1888,7 +1905,7 @@ struct i40e_aqc_nvm_config_read {
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#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
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#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
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__le16 element_count;
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__le16 element_id; /* Feature/field ID */
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__le16 element_id; /* Feature/field ID */
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__le16 element_id_msw; /* MSWord of field ID */
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__le32 address_high;
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__le32 address_low;
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@ -1909,9 +1926,10 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
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/* Used for 0x0704 as well as for 0x0705 commands */
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#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
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#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
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#define I40E_AQ_ANVM_FEATURE 0
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#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
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#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
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(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
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#define I40E_AQ_ANVM_FEATURE 0
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#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
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struct i40e_aqc_nvm_config_data_feature {
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__le16 feature_id;
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#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
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@ -1935,7 +1953,7 @@ I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
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/* OEM Post Update (indirect 0x0720)
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* no command data struct used
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*/
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struct i40e_aqc_nvm_oem_post_update {
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struct i40e_aqc_nvm_oem_post_update {
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#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
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u8 sel_data;
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u8 reserved[7];
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@ -2225,7 +2243,8 @@ I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
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*/
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struct i40e_aqc_lldp_stop_start_specific_agent {
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#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
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#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
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#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
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(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
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u8 command;
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u8 reserved[15];
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};
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@ -2247,7 +2266,7 @@ struct i40e_aqc_add_udp_tunnel {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
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struct i40e_aqc_add_udp_tunnel_completion {
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__le16 udp_port;
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__le16 udp_port;
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u8 filter_entry_index;
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u8 multiple_pfs;
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#define I40E_AQC_SINGLE_PF 0x0
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@ -2257,6 +2257,9 @@ enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
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struct i40e_aq_desc desc;
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struct i40e_aqc_add_get_update_vsi *cmd =
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(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
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struct i40e_aqc_add_get_update_vsi_completion *resp =
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(struct i40e_aqc_add_get_update_vsi_completion *)
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&desc.params.raw;
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enum i40e_status_code status;
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i40e_fill_default_direct_cmd_desc(&desc,
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@ -2268,6 +2271,9 @@ enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
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status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
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sizeof(vsi_ctx->info), cmd_details);
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vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
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vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
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return status;
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}
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@ -3507,7 +3513,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
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p->num_msix_vectors = number;
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i40e_debug(hw, I40E_DEBUG_INIT,
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"HW Capability: MSIX vector count = %d\n",
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p->num_msix_vectors_vf);
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p->num_msix_vectors);
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break;
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case I40E_AQ_CAP_ID_VF_MSIX:
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p->num_msix_vectors_vf = number;
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@ -4241,7 +4247,7 @@ enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
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}
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/**
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* i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
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* i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
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* @hw: pointer to the hw struct
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* @flags: component flags
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* @mac_seid: uplink seid (MAC SEID)
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@ -5077,7 +5083,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
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return ret;
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/* Read the PF Queue Filter control register */
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val = rd32(hw, I40E_PFQF_CTL_0);
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val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
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/* Program required PE hash buckets for the PF */
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val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
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@ -5114,7 +5120,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
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if (settings->enable_macvlan)
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val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
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wr32(hw, I40E_PFQF_CTL_0, val);
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i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
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return I40E_SUCCESS;
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}
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@ -6038,6 +6044,128 @@ restore_config:
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return status;
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}
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/**
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* i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: ptr to register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Use the firmware to read the Rx control register,
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* especially useful if the Rx unit is under heavy pressure
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**/
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enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
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u32 reg_addr, u32 *reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
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(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
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enum i40e_status_code status;
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if (reg_val == NULL)
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return I40E_ERR_PARAM;
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i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
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cmd_resp->address = CPU_TO_LE32(reg_addr);
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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if (status == I40E_SUCCESS)
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*reg_val = LE32_TO_CPU(cmd_resp->value);
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return status;
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}
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/**
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* i40e_read_rx_ctl - read from an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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**/
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u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
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{
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enum i40e_status_code status = I40E_SUCCESS;
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bool use_register;
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int retry = 5;
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u32 val = 0;
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use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
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if (!use_register) {
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do_retry:
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status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
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if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
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i40e_msec_delay(1);
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retry--;
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goto do_retry;
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}
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}
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/* if the AQ access failed, try the old-fashioned way */
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if (status || use_register)
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val = rd32(hw, reg_addr);
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return val;
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}
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/**
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* i40e_aq_rx_ctl_write_register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Use the firmware to write to an Rx control register,
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* especially useful if the Rx unit is under heavy pressure
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**/
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enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
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u32 reg_addr, u32 reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_rx_ctl_reg_read_write *cmd =
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(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
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enum i40e_status_code status;
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i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
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cmd->address = CPU_TO_LE32(reg_addr);
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cmd->value = CPU_TO_LE32(reg_val);
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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return status;
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}
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/**
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* i40e_write_rx_ctl - write to an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: register value
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**/
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void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
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{
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enum i40e_status_code status = I40E_SUCCESS;
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bool use_register;
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int retry = 5;
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|
||||
use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
|
||||
if (!use_register) {
|
||||
do_retry:
|
||||
status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
|
||||
reg_val, NULL);
|
||||
if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
|
||||
i40e_msec_delay(1);
|
||||
retry--;
|
||||
goto do_retry;
|
||||
}
|
||||
}
|
||||
|
||||
/* if the AQ access failed, try the old-fashioned way */
|
||||
if (status || use_register)
|
||||
wr32(hw, reg_addr, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_aq_send_msg_to_pf
|
||||
* @hw: pointer to the hardware structure
|
||||
|
@ -75,7 +75,6 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
|
||||
void *desc, void *buffer, u16 buf_len);
|
||||
|
||||
void i40e_idle_aq(struct i40e_hw *hw);
|
||||
void i40e_resume_aq(struct i40e_hw *hw);
|
||||
bool i40e_check_asq_alive(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
|
||||
const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
|
||||
@ -489,6 +488,14 @@ enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
|
||||
u16 vsi_seid);
|
||||
enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
|
||||
enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
|
||||
enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, u8 page,
|
||||
u16 reg, u8 phy_addr, u16 *value);
|
||||
enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, u8 page,
|
||||
|
@ -2054,6 +2054,14 @@
|
||||
#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
|
||||
#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
|
||||
#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
|
||||
#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GL_PRS_FVBM_MAX_INDEX 3
|
||||
#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0
|
||||
#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)
|
||||
#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8
|
||||
#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)
|
||||
#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31
|
||||
#define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)
|
||||
#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */
|
||||
#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
|
||||
#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
|
||||
@ -2225,6 +2233,14 @@
|
||||
#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
|
||||
#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
|
||||
#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
|
||||
#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
|
||||
#define I40E_PRTQF_FD_INSET_MAX_INDEX 63
|
||||
#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
|
||||
#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
|
||||
#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
|
||||
#define I40E_PRTQF_FD_INSET_MAX_INDEX 63
|
||||
#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
|
||||
#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
|
||||
#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
|
||||
#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
|
||||
#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
|
||||
|
@ -177,7 +177,6 @@ enum i40e_memcpy_type {
|
||||
I40E_DMA_TO_NONDMA
|
||||
};
|
||||
|
||||
|
||||
#define I40E_FW_API_VERSION_MINOR_X710 0x0005
|
||||
|
||||
|
||||
|
@ -48,7 +48,7 @@
|
||||
/*********************************************************************
|
||||
* Driver version
|
||||
*********************************************************************/
|
||||
char ixl_driver_version[] = "1.4.24-k";
|
||||
char ixl_driver_version[] = "1.4.27-k";
|
||||
|
||||
/*********************************************************************
|
||||
* PCI Device ID Table
|
||||
@ -557,8 +557,10 @@ ixl_attach(device_t dev)
|
||||
goto err_mac_hmc;
|
||||
}
|
||||
|
||||
/* Disable LLDP from the firmware */
|
||||
i40e_aq_stop_lldp(hw, TRUE, NULL);
|
||||
/* Disable LLDP from the firmware for certain NVM versions */
|
||||
if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
|
||||
(pf->hw.aq.fw_maj_ver < 4))
|
||||
i40e_aq_stop_lldp(hw, TRUE, NULL);
|
||||
|
||||
i40e_get_mac_addr(hw, hw->mac.addr);
|
||||
error = i40e_validate_mac_addr(hw->mac.addr);
|
||||
@ -2582,7 +2584,8 @@ ixl_configure_queue_intr_msix(struct ixl_pf *pf)
|
||||
u16 vector = 1;
|
||||
|
||||
for (int i = 0; i < vsi->num_queues; i++, vector++) {
|
||||
wr32(hw, I40E_PFINT_DYN_CTLN(i), i);
|
||||
wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
|
||||
/* First queue type is RX / 0 */
|
||||
wr32(hw, I40E_PFINT_LNKLSTN(i), i);
|
||||
|
||||
reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
|
||||
@ -2595,11 +2598,8 @@ ixl_configure_queue_intr_msix(struct ixl_pf *pf)
|
||||
reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
|
||||
(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
|
||||
(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
|
||||
((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
|
||||
(IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
|
||||
(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
|
||||
if (i == (vsi->num_queues - 1))
|
||||
reg |= (IXL_QUEUE_EOL
|
||||
<< I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
|
||||
wr32(hw, I40E_QINT_TQCTL(i), reg);
|
||||
}
|
||||
}
|
||||
@ -3882,7 +3882,7 @@ ixl_config_rss(struct ixl_vsi *vsi)
|
||||
|
||||
/* Fill out hash function seed */
|
||||
for (i = 0; i < IXL_KEYSZ; i++)
|
||||
wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]);
|
||||
i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), rss_seed[i]);
|
||||
|
||||
/* Enable PCTYPES for RSS: */
|
||||
#ifdef RSS
|
||||
@ -3915,11 +3915,11 @@ ixl_config_rss(struct ixl_vsi *vsi)
|
||||
((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD);
|
||||
#endif
|
||||
hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
|
||||
((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
|
||||
hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
|
||||
((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
|
||||
hena |= set_hena;
|
||||
wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
|
||||
wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
|
||||
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
|
||||
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
|
||||
|
||||
/* Populate the LUT with max no. of queues in round robin fashion */
|
||||
for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
|
||||
@ -6116,10 +6116,10 @@ ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum,
|
||||
index = qnum / 2;
|
||||
shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT;
|
||||
|
||||
qtable = rd32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num));
|
||||
qtable = i40e_read_rx_ctl(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num));
|
||||
qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift);
|
||||
qtable |= val << shift;
|
||||
wr32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable);
|
||||
i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -6135,7 +6135,7 @@ ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf)
|
||||
* Contiguous mappings aren't actually supported by the hardware,
|
||||
* so we have to use non-contiguous mappings.
|
||||
*/
|
||||
wr32(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num),
|
||||
i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num),
|
||||
I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
|
||||
|
||||
wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num),
|
||||
|
@ -48,7 +48,7 @@
|
||||
/*********************************************************************
|
||||
* Driver version
|
||||
*********************************************************************/
|
||||
char ixlv_driver_version[] = "1.2.10-k";
|
||||
char ixlv_driver_version[] = "1.2.11-k";
|
||||
|
||||
/*********************************************************************
|
||||
* PCI Device ID Table
|
||||
|
Loading…
x
Reference in New Issue
Block a user