diff --git a/sys/mips/include/cache.h b/sys/mips/include/cache.h
index 9fc91595a10d..a95d5d0a255b 100644
--- a/sys/mips/include/cache.h
+++ b/sys/mips/include/cache.h
@@ -161,6 +161,8 @@ extern struct mips_cache_ops mips_cache_ops;
 /* PRIMARY CACHE VARIABLES */
 extern int mips_picache_linesize;
 extern int mips_pdcache_linesize;
+extern int mips_sdcache_linesize;
+extern int mips_dcache_max_linesize;
 
 #define	__mco_noargs(prefix, x)						\
 do {									\
diff --git a/sys/mips/mips/busdma_machdep.c b/sys/mips/mips/busdma_machdep.c
index d9eb9d481065..35d60999f0c2 100644
--- a/sys/mips/mips/busdma_machdep.c
+++ b/sys/mips/mips/busdma_machdep.c
@@ -226,7 +226,7 @@ busdma_init(void *dummy)
 
 	/* Create a cache of buffers in standard (cacheable) memory. */
 	standard_allocator = busdma_bufalloc_create("buffer",
-	    mips_pdcache_linesize,	/* minimum_alignment */
+	    mips_dcache_max_linesize,	/* minimum_alignment */
 	    NULL,			/* uma_alloc func */
 	    NULL,			/* uma_free func */
 	    0);				/* uma_zcreate_flags */
@@ -236,7 +236,7 @@ busdma_init(void *dummy)
 	 * BUS_DMA_COHERENT flag.
 	 */
 	coherent_allocator = busdma_bufalloc_create("coherent",
-	    mips_pdcache_linesize,	/* minimum_alignment */
+	    mips_dcache_max_linesize,	/* minimum_alignment */
 	    busdma_bufalloc_alloc_uncacheable,
 	    busdma_bufalloc_free_uncacheable,
 	    0);				/* uma_zcreate_flags */
@@ -1061,10 +1061,10 @@ _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
 static void
 bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned)
 {
-	char tmp_cl[mips_pdcache_linesize], tmp_clend[mips_pdcache_linesize];
+	char tmp_cl[mips_dcache_max_linesize], tmp_clend[mips_dcache_max_linesize];
 	vm_offset_t buf_cl, buf_clend;
 	vm_size_t size_cl, size_clend;
-	int cache_linesize_mask = mips_pdcache_linesize - 1;
+	int cache_linesize_mask = mips_dcache_max_linesize - 1;
 
 	/*
 	 * dcache invalidation operates on cache line aligned addresses
@@ -1091,7 +1091,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned)
 		buf_cl = buf & ~cache_linesize_mask;
 		size_cl = buf & cache_linesize_mask;
 		buf_clend = buf + len;
-		size_clend = (mips_pdcache_linesize - 
+		size_clend = (mips_dcache_max_linesize -
 		    (buf_clend & cache_linesize_mask)) & cache_linesize_mask;
 	}
 
@@ -1123,7 +1123,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned)
 		if (size_cl)
 			mips_dcache_wbinv_range(buf_cl, size_cl);
 		if (size_clend && (size_cl == 0 ||
-                    buf_clend - buf_cl > mips_pdcache_linesize))
+                    buf_clend - buf_cl > mips_dcache_max_linesize))
 			mips_dcache_wbinv_range(buf_clend, size_clend);
 		break;
 
@@ -1156,7 +1156,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned)
 		if (size_cl)
 			mips_dcache_wbinv_range(buf_cl, size_cl);
 		if (size_clend && (size_cl == 0 ||
-                    buf_clend - buf_cl > mips_pdcache_linesize))
+                    buf_clend - buf_cl > mips_dcache_max_linesize))
 			mips_dcache_wbinv_range(buf_clend, size_clend);
 		break;
 
diff --git a/sys/mips/mips/cache_mipsNN.c b/sys/mips/mips/cache_mipsNN.c
index 50eb76b2feef..7feb60cfd27c 100644
--- a/sys/mips/mips/cache_mipsNN.c
+++ b/sys/mips/mips/cache_mipsNN.c
@@ -97,6 +97,8 @@ xlp_sync(void)
  */
 int mips_picache_linesize;
 int mips_pdcache_linesize;
+int mips_sdcache_linesize;
+int mips_dcache_max_linesize;
 
 static int picache_size;
 static int picache_stride;
@@ -157,6 +159,10 @@ mipsNN_cache_init(struct mips_cpuinfo * cpuinfo)
 	sdcache_size = cpuinfo->l2.dc_size;
 	sdcache_way_mask = cpuinfo->l2.dc_nways - 1;
 
+	mips_sdcache_linesize = cpuinfo->l2.dc_linesize;
+	mips_dcache_max_linesize = MAX(mips_pdcache_linesize,
+	    mips_sdcache_linesize);
+
 #define CACHE_DEBUG
 #ifdef CACHE_DEBUG
 	printf("Cache info:\n");
@@ -166,6 +172,7 @@ mipsNN_cache_init(struct mips_cpuinfo * cpuinfo)
 	printf("  picache_loopcount = %d\n", picache_loopcount);
 	printf("  pdcache_stride    = %d\n", pdcache_stride);
 	printf("  pdcache_loopcount = %d\n", pdcache_loopcount);
+	printf("  max line size     = %d\n", mips_dcache_max_linesize);
 #endif
 }