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Exar driver for X3100 10GbE Server/Storage adapters

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Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
          TSO (TCP segmentation offload), RTH (Receive Traffic Hash).

Submitted by: Sriram Rapuru at Exar
MFC after:	2 weeks
This commit is contained in:
gnn 2011-04-28 14:33:15 +00:00
parent 574178d5e6
commit d580860e12
70 changed files with 107755 additions and 0 deletions
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share/man/man4/vxge.4 Normal file
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.\" Copyright (c) 2002-2011 Exar Corp.
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer as
.\" the first lines of this file unmodified.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd March 16, 2011
.Dt VXGE 1
.Os
.Sh NAME
.Nm vxge
.Nd "Neterion X3100 10GbE Server/Storage adapter driver"
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following line in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device vxge"
.Ed
.Pp
Alternatively, to load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
if_vxge_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver provides support for Neterion X3100 adapters.
The driver supports TCP Segmentation Offload (TSO/LSO),
Large Receive Offlaod (LRO), Jumbo Frames, Receive Traffic Hash (RTH),
VLAN, Promiscuous mode and Multi function mode.
.Pp
The
.Nm
driver supports following function modes:
.Bd -ragged -offset indent
.Cd "SF1_VP17 - 1 function with 17 VPATHs"
.Ed
.Bd -ragged -offset indent
.Cd "MF8_VP2 - 8 functions with 2 VPATHs per function"
.Ed
.Bd -ragged -offset indent
.Cd "MF2_VP8 - 2 functions, 8 Paths/Function"
.Ed
.Bd -ragged -offset indent
.Cd "MF4_VP4 - 4 Functions, 4 Paths/Function"
.Ed
.Bd -ragged -offset indent
.Cd "MF8P_VP2 - 8 functions with 2 VPATHs per function required for DirectIO"
.Ed
.Pp
For general information and support, please visit the Neterion support page
.Pa http://www.neterion.com/support/support.html .
.Pp
Support for Jumbo Frames is provided via the interface MTU setting.
Selecting an MTU larger than 1500 bytes with the
.Xr ifconfig 8
utility configures the adapter to transmit and receive Jumbo Frames.
X3100 adapters support Jumbo Frames up to 9600 bytes.
.Pp
For Jumbo Frames, the driver will try to allocate physically contiguous buffers.
Failures to do so may degrade the performance.
To resolve such problems, please visit
.Pa http://www.neterion.com
where additional information and a kernel patch can be found.
.Pp
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh HARDWARE
The
.Nm
driver supports Neterion X3100 10 Gigabit Ethernet adapters listed in
.Pa http://www.neterion.com .
.Sh SUPPORT
For troubleshooting tips and FAQs, please visit
.Pa http://trac.neterion.com/cgi-bin/trac.cgi/wiki/TitleIndex?anonymous .
.Pp
For any issues please send an email to
.Aq support@neterion.com .
.Sh SEE ALSO
.Xr arp 8 ,
.Xr ifconfig 8
.Sh AUTHORS
The
.Nm
driver was written by
.An Neterion
.Aq support@neterion.com .

1
sys/conf/NOTES
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@ -2094,6 +2094,7 @@ device nxge # Neterion Xframe 10GbE Server/Storage Adapter
device ti # Alteon Networks Tigon I/II gigabit Ethernet
device txp # 3Com 3cR990 (``Typhoon'')
device vx # 3Com 3c590, 3c595 (``Vortex'')
device vxge # Exar/Neterion XFrame 3100 10GbE
# PCI FDDI NICs.
device fpa

18
sys/conf/files
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@ -1970,6 +1970,24 @@ dev/vte/if_vte.c optional vte pci
dev/vx/if_vx.c optional vx
dev/vx/if_vx_eisa.c optional vx eisa
dev/vx/if_vx_pci.c optional vx pci
dev/vxge/vxge.c optional vxge
dev/vxge/vxgehal/vxgehal-ifmsg.c optional vxge
dev/vxge/vxgehal/vxgehal-mrpcim.c optional vxge
dev/vxge/vxgehal/vxge-queue.c optional vxge
dev/vxge/vxgehal/vxgehal-ring.c optional vxge
dev/vxge/vxgehal/vxgehal-swapper.c optional vxge
dev/vxge/vxgehal/vxgehal-mgmt.c optional vxge
dev/vxge/vxgehal/vxgehal-srpcim.c optional vxge
dev/vxge/vxgehal/vxgehal-config.c optional vxge
dev/vxge/vxgehal/vxgehal-blockpool.c optional vxge
dev/vxge/vxgehal/vxgehal-doorbells.c optional vxge
dev/vxge/vxgehal/vxgehal-mgmtaux.c optional vxge
dev/vxge/vxgehal/vxgehal-device.c optional vxge
dev/vxge/vxgehal/vxgehal-mm.c optional vxge
dev/vxge/vxgehal/vxgehal-driver.c optional vxge
dev/vxge/vxgehal/vxgehal-virtualpath.c optional vxge
dev/vxge/vxgehal/vxgehal-channel.c optional vxge
dev/vxge/vxgehal/vxgehal-fifo.c optional vxge
dev/watchdog/watchdog.c standard
dev/wb/if_wb.c optional wb pci
dev/wds/wd7000.c optional wds isa

31
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/*-
* Copyright (c) 2002-2010 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/

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$FreeBSD$
''_Readme for FreeBSD X3100 Series 10GbE PCIe I/O Virtualized Server Adapter Drivers_'''
=== Introduction ===
FreeBSD Driver for X3100 10GbE Server/Storage adapters
* Drivers support all X3100 10GbE adapters with FreeBSD version 7.x, 8.x and 9.x
* Supports both i386 and amd64 architectures
* Features: Jumbo frames (up to 9600),
LRO (Large Receive Offload),
TSO (TCP segmentation offload),
RTH (Receive Traffic Hash).
Also, Extended Message Signaled Interrupts (MSI-X).
''Features''
a. Jumbo frames:
X3110 and X3120 supports MTU up to 9600 bytes, modifiable using ifconfig command.
b. LRO (Large Receive Offload):
LRO can be enabled/disabled before loading driver.
Set lro_enable in vxge.conf to 1 before loading driver.
c. TSO (TCP Segmentation Offload)
TSO can be enabled/disabled before loading driver.
Set tso_enable in vxge.conf to 1 before loading driver.
d. RTH (Receive Traffic Hash)
Receive side steering for better scaling.
Set rth_enable in vxge.conf to 1 before loading driver.
e. MSI-X
Can be enabled on platforms which support it, resulting in noticeable
performance improvement.
f. Multi-VPaths
Up to 17 hardware based transmit and receive data channels, with
multiple steering options.
''X3100 & Driver configuration: vxge.conf''
The vxge.conf contains following attributes.
''msix_enable''
Enable MSI (Message Signaled Interrupts) feature in driver.
0 - INTA
1 - MSI-X
Default: 1
''rth_enable''
Enables Receive side steering for better scaling (RTH - Receive Traffic Hash)
Range: 0 - 1
Default: 1
''lro_enable''
Enables LRO (Large Receive Offload) feature in driver.
Range: 0 - 1
Default: 1
''tso_enable''
Enables TSO (TCP Segmentaton Offload) feature in driver.
Range: 0 - 1
Default: 1
''no_of_vpath''
Specifies maximum VPATH(s) configured for each device function.
Valid range: 1-17
Default: Optimized by driver
''func_mode''
Change PCI function mode
0 - SF1_VP17 (1 function with 17 VPATHs)
1 - MF8_VP2 (8 functions with 2 VPATHs per function)
8 - MF2_VP8 (2 functions, 8 Paths/Function)
9 - MF4_VP4 (4 Functions, 4 Paths/Function)
11 - MF8P_VP2 (8 functions with 2 VPATHS per function required for DirectIO)
Default: -1
''port_mode''
Change the default dual port mode
2 - Active Passive
3 - Single Port
4 - Dual Port
''l2_switch''
Turn on/off the inter function traffic through l2 switch
0 - Disallow inter function traffic
1 - Allow inter function traffic
Default: -1
''bandwidth_0 - bandwidth_7''
Desired max receive/transmit bandwidth,in Mbps for function 0 to function 7
Minimum value is 100 Mbps, for 1 Gbps specify a value of 1024.
''priority_0 - priority_7''
Desired receive/transmit priority for function 0 to function 7
''intr_coalesce''
Adaptive interrupt coalescing
0 - Disable
1 - Enable
''Low Latency''
0 - Disable
1 - Enable
=== Installation Instructions ===
''Identifying the Adapter''
The X3100 adapter is identified by the board ID number on the adapter.
Look for a label that has a barcode and a number, for example,
SXT0425072. The factory-burned MAC address (hardware address)
shows up on the board above the serial number,
(similar to 000CFC000449 -- 00:0C:FC:00:04:49).
''Kernel Driver Source Package''
This package contains kernel_update.sh script which is to be used to copy driver sources to kernel path.
It creates vxge folder with source code in /usr/src/sys/dev and Makefile in /usr/src/sys/modules.
Loadable parameters can be changed by putting below lines in /boot/device.hints and set values as desired.
hint.vxge.0.msix_enable="1"
hint.vxge.0.rth_enable="1"
hint.vxge.0.lro_enable="1"
hint.vxge.0.tso_enable="1"
hint.vxge.0.tx_steering="1"
hint.vxge.0.no_of_vpath="-1"
hint.vxge.0.func_mode="-1"
hint.vxge.0.port_mode="-1"
hint.vxge.0.fw_upgrade="1"
hint.vxge.0.bandwidth_0="-1"
hint.vxge.0.bandwidth_1="-1"
hint.vxge.0.bandwidth_2="-1"
hint.vxge.0.bandwidth_3="-1"
hint.vxge.0.bandwidth_4="-1"
hint.vxge.0.bandwidth_5="-1"
hint.vxge.0.bandwidth_6="-1"
hint.vxge.0.bandwidth_7="-1"
hint.vxge.0.priority_0="-1"
hint.vxge.0.priority_1="-1"
hint.vxge.0.priority_2="-1"
hint.vxge.0.priority_3="-1"
hint.vxge.0.priority_4="-1"
hint.vxge.0.priority_5="-1"
hint.vxge.0.priority_6="-1"
hint.vxge.0.priority_7="-1"
hint.vxge.0.intr_coalesce="0"
hint.vxge.0.low_latency="0"
e.g., set hint.vxge.0.msix_enable to 0 to load driver in INTA mode.
Then reboot the system to add loadable parameters to kenv.
''Standalone Driver Source Package''
vxge (FreeBSD package)
This directory contains FreeBSD driver sources for X3100 device(s),
Makefile, and X3100 Hardware Abstraction headers and sources
(vxgehal and include folders)
vxgehal
This directory contains the X3100 HAL sources.
The driver uses HAL to perform operations on the X3100 hardware.
include
The include subdirectory contains HAL header files.
Source code for vxge-manage tool (used to get statistics, pciconfig and
register dump) are included in the freebsd directory.
''Building the driver''
The driver is distributed in the source form. Driver and installation
utility executables need to be built for the target platform.
In the directory containing Makefile for building Exar driver for FreeBSD,
#make clean
#make
Please unload previously installed Exar drivers before proceeding with following steps.
#make uninstall
''Loading the driver''
Use "kldload" to load driver module vxge.ko.
#kldload ./vxge.ko
Run "kldstat" and find an entry for vxge kernel module to ensure driver installation
was successful.
#kldstat | grep vxge
3 1 0xc22cc000 26000 vxge.ko
''Enabling interface and assigning IP address''
#ifconfig <INTERFACE> <IP_ADDRESS> up
<INTERFACE> will be similar to vxge0, vxge1 etc. and can be
found by executing "ifconfig -a".
Neterion adapters typically have MAC addresses starting with
"00:0C:FC" or "00:11:25".
Example:
#ifconfig vxge0 10.2.2.40 up
Enables vxge0 interface and assigns to it the IP address 10.2.2.40.
vxge0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
options=53b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWTAGGING,JUMBO_MTU,TSO4,LRO>
ether 00:0c:fc:00:da:47
inet6 fe80::20c:fcff:fe00:da47%vxge0 prefixlen 64 scopeid 0x3
inet 10.2.2.40 netmask 0xff000000 broadcast 17.255.255.255
media: Ethernet autoselect (10Gbase-SR <full-duplex>)
status: active
''Disabling the interface''
#ifconfig <INTERFACE> down
Example:
#ifconfig vxge0 down
''Unloading the Driver''
#kldunload vxge.ko
=== Performance Suggestions ===
Sysctl Tuning Parameters
#sysctl net.inet.tcp.sendspace=786432
#sysctl net.inet.tcp.recvspace=786432
#sysctl net.inet.tcp.recvbuf_max=16777216
#sysctl net.inet.tcp.sendbuf_max=16777216
#sysctl net.inet.tcp.blackhole=1
#sysctl net.inet.tcp.rfc1323=1
#sysctl net.inet.tcp.path_mtu_discovery=1
#sysctl net.inet.tcp.inflight.enable=0
#sysctl net.inet.ip.maxfragsperpacket=2147483647
#sysctl kern.ipc.maxsockbuf=8388608
#sysctl kern.ipc.nmbclusters=2147483647
#sysctl kern.ipc.nmbjumbop=262144
#sysctl kern.ipc.maxsockets=81920
#sysctl hw.intr_storm_threshold=9000
''Usage & Troubleshooting''
For general information and support, please visit Neterion support website at
http://www.neterion.com/support/support.html
Make sure that the operating system identifies the X3100 adapter. Note that
Neterion vendor ID is 0x17D5 and X3110 and X3120 adapters can be fixed to both PCIe slots.
The rest of this section details troubleshooting tips and information. Some of
them are general and some are more specific. For online Troubleshooting tips
and faqs, please visit
http://trac.neterion.com/cgi-bin/trac.cgi/wiki/TitleIndex?anonymous
''Loading the driver and initializing the device''
The first time FreeBSD identifies the device it stores the corresponding
device/vendor IDs in an enumerated tree of PCI devices. Note that Neterion
vendor id is 0x17d5.
After cold reboot FreeBSD finds the device and tries to load the corresponding
driver. If it fails, try to switch the card and/or cable. And, in parallel, send
us the "tail" of the "/var/log/messages". We also need traces, register dump and
statistics(Use vxge-manage tool).
''Collect information''
If you're reporting a problem to Neterion, please describe:
host(s) and adapter(s), switch (if used), software version.
''ARP''
If this is a basic connectivity issue (e.g., cannot connect, cannot ping),
make sure first that ARP works
Do you see ARPs coming through a switch (in case switch is used)?
Do you see frame drops at the switch when pinging?
Do you see frame counts increasing via statistics?
''Have you tried''
a. A previous driver release;
b. A different adapter in the same PCI slot;
c. A different PCI slot;
d. Back-to-back setup so that the switch is excluded from the equation.
e. To replace the cables?
f. To use a different PCI slot?
''Start clean''
a. Have you tried to reboot the switch? Cold-reboot the host?
b. Make sure that the latest released driver gets loaded after the host
reboot, and that the 10GE interface shows up via ifconfig.
''LEDs''
Do you see LED going green after everything is connected and drivers loaded?
How/when does the color changes?
''ifconfig''
Run "ifconfig -a" at the command prompt and check whether the output Looks as
expected. Include the output in your problem report.
Note for instance that "all-foxes" i.e, FF:FF:FF:FF:FF:FF MAC address could
explain a general connectivity issue, if that's what you see.
''Log''
Please attach the generated log, with traces enabled.
Note that the driver's logging facility is configurable at compile-time. Errors
and traces can be compiled out on a per-component basis. The components are: HAL
fifos and rings, device, etc., see VXGE_COMPONENT_HAL_??? in the Makefile.
Here's how you enable all except data path traces:
CFLAGS_VXGE = -DVXGE_DEBUG_MODULE_MASK=0xffffffbf \
-DVXGE_DEBUG_ERR_MASK=0xffffffbf
Recompile with traces and include the log in the report.
=== Utilities ===
''Statistics''
To print hardware and software statistics for interface instance 0
(i.e., vxge0), run:
#vxge-manage vxgeX stats common
#vxge-manage vxgeX stats mrpcim
#vxge-manage vxgeX stats driver
#vxge-manage vxgeX pciconfig
#vxge-manage vxgeX hwinfo
#vxge-manage vxgeX bw_pri_get
#vxge-manage vxgeX bw_pri_get vf_id
#vxge-manage vxgeX port_mode_get
The vxge-manage tool generates log file in the working directory. Once done, ping a
few times, and collect the statistics again (Ping both from this and the remote
machines).
Many counters could be of interest. For example, "rx_vld_frms" counts all
valid incoming Ethernet frames seen by the adapter. Information could be derived
from the fact that (for instance) counter stay constant during ping, if that is
what happening. For detailed description of the X3100 counters, please refer
to the "X3100 User Guide".
Please include the statistics into your problem report.
''X3100 registers''
Use vxge-manage to dump all X3100 BAR0 space registers. Include this register dump
into your problem report.
#vxge-manage vxgeX regs
''PCI configuration space''
Use vxge-manage to retrieve PCI vendor, device, etc. Include the PCI configutation
space in your problem report.
#vxge-manage vxgeX pciconfig
''Hardware Info''
To retrieve hardware info of device, e.g, serial / part number and function mode etc.
use vxge-manage
#vxge-manage vxgeX hwinfo
''Bandwidth and Priority''
Use vxge-manage to display Bandwidth and Priority information.
#vxge-manage vxgeX bw_pri_get
or
#vxge-manage vxgeX bw_pri_get vf_id
vxge-manage can also be used to set bandwidth and priority for individual VF.
#vxge-manage vxgeX bw_pri_set vf_id bandwidth
or
#vxge-manage vxgeX bw_pri_set vf_id bandwidth priority
Example:
#vxge-manage vxge0 bw_pri_set 0 1500
or
#vxge-manage vxge0 bw_pri_set 0 1500 1
''Port mode''
Use vxge-manage to display Port mode setting
#vxge-manage vxgeX port_mode_get
vxge-manage can also be used to set Port mode.
#vxge-manage vxgeX port_mode_set port_mode_value
Example:
#vxge-manage vxge0 port_mode_set 2
=== Known Issues ===
=== Available Downloads ===
For latest available drivers or further support please contact your network
adapter provider or neterionsupport@exar.com.
===================================================================
Exar Corp., Proprietary
COPYRIGHT (c) 2002-2011 Exar corp., ALL RIGHTS RESERVED

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/* $FreeBSD$ */
#ifndef BUILD_VERSION_H
#define BUILD_VERSION_H
/* Do not edit! Automatically generated when released. */
#define GENERATED_BUILD_VERSION 22708
#endif /* BUILD_VERSION_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_DEBUG_H
#define VXGE_DEBUG_H
__EXTERN_BEGIN_DECLS
/*
* __FUNCTION__ is, together with __PRETTY_FUNCTION__ or something similar,
* a gcc extension. we'll have to #if defined around that, and provide some
* meaningful replacement for those, so to make some gcc versions happier
*/
#ifndef __func__
#if defined(__FUNCTION__)
#define __func__ __FUNCTION__
#else
#define __func__ " "
#endif
#endif
#define NULL_HLDEV NULL
#define NULL_VPID 0xFFFFFFFF
#define VXGE_DEBUG_MODULE_MASK_DEF 0xFFFFFFFF
#define VXGE_DEBUG_LEVEL_DEF VXGE_TRACE
extern u32 g_debug_level;
#ifndef VXGE_DEBUG_MODULE_MASK
#define VXGE_DEBUG_MODULE_MASK 0
#endif
/*
* enum vxge_debug_level_e
* @VXGE_NONE: debug disabled
* @VXGE_ERR: all errors going to be logged out
* @VXGE_INFO: all errors plus all kind of info tracing print outs
* going to be logged out. noisy.
* @VXGE_TRACE: all errors, all info plus all function entry and exit
* and parameters. Very noisy
*
* This enumeration going to be used to switch between different
* debug levels during runtime if DEBUG macro defined during
* compilation. If DEBUG macro not defined than code will be
* compiled out.
*/
typedef enum vxge_debug_level_e {
VXGE_NONE = 0x0,
VXGE_ERR = 0x1,
VXGE_INFO = 0x2,
VXGE_TRACE = 0x4,
} vxge_debug_level_e;
/*
* @VXGE_COMPONENT_HAL_DEVICE: do debug for vxge core device module
* @VXGE_COMPONENT_HAL_DEVICE_IRQ: do debug for vxge core device module in ISR
* @VXGE_COMPONENT_HAL_VAPTH: do debug for vxge core virtual path module
* @VXGE_COMPONENT_HAL_VAPTH_ISR: do debug for vxge core virtual path module in
* ISR
* @VXGE_COMPONENT_HAL_CONFIG: do debug for vxge core config module
* @VXGE_COMPONENT_HAL_MM: do debug for vxge core memory module
* @VXGE_COMPONENT_HAL_POOL: do debug for vxge core memory pool module
* @VXGE_COMPONENT_HAL_QUEUE: do debug for vxge core queue module
* @VXGE_COMPONENT_HAL_BITMAP: do debug for vxge core BITMAP module
* @VXGE_COMPONENT_HAL_CHANNEL: do debug for vxge core channel module
* @VXGE_COMPONENT_HAL_FIFO: do debug for vxge core fifo module
* @VXGE_COMPONENT_HAL_RING: do debug for vxge core ring module
* @VXGE_COMPONENT_HAL_DMQ: do debug for vxge core DMQ module
* @VXGE_COMPONENT_HAL_UMQ: do debug for vxge core UMQ module
* @VXGE_COMPONENT_HAL_SQ: do debug for vxge core SQ module
* @VXGE_COMPONENT_HAL_SRQ: do debug for vxge core SRQ module
* @VXGE_COMPONENT_HAL_CQRQ: do debug for vxge core CRQ module
* @VXGE_COMPONENT_HAL_NCE: do debug for vxge core NCE module
* @VXGE_COMPONENT_HAL_STAG: do debug for vxge core STAG module
* @VXGE_COMPONENT_HAL_TCP: do debug for vxge core TCP module
* @VXGE_COMPONENT_HAL_LRO: do debug for vxge core LRO module
* @VXGE_COMPONENT_HAL_SPDM: do debug for vxge core SPDM module
* @VXGE_COMPONENT_HAL_SESSION: do debug for vxge core SESSION module
* @VXGE_COMPONENT_HAL_STATS: do debug for vxge core statistics module
* @VXGE_COMPONENT_HAL_MRPCIM: do debug for vxge KMA core mrpcim module
* @VXGE_COMPONENT_HAL_SRPCIM: do debug for vxge KMA core srpcim module
* @VXGE_COMPONENT_OSDEP: do debug for vxge KMA os dependent parts
* @VXGE_COMPONENT_LL: do debug for vxge link layer module
* @VXGE_COMPONENT_ULD: do debug for vxge upper layer driver
* @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions
*
* This enumeration going to be used to distinguish modules
* or libraries during compilation and runtime. Makefile must declare
* VXGE_DEBUG_MODULE_MASK macro and set it to proper value.
*/
#define VXGE_COMPONENT_HAL_DEVICE 0x00000001
#define VXGE_COMPONENT_HAL_DEVICE_IRQ 0x00000002
#define VXGE_COMPONENT_HAL_VPATH 0x00000004
#define VXGE_COMPONENT_HAL_VPATH_IRQ 0x00000008
#define VXGE_COMPONENT_HAL_CONFIG 0x00000010
#define VXGE_COMPONENT_HAL_MM 0x00000020
#define VXGE_COMPONENT_HAL_POOL 0x00000040
#define VXGE_COMPONENT_HAL_QUEUE 0x00000080
#define VXGE_COMPONENT_HAL_BITMAP 0x00000100
#define VXGE_COMPONENT_HAL_CHANNEL 0x00000200
#define VXGE_COMPONENT_HAL_FIFO 0x00000400
#define VXGE_COMPONENT_HAL_RING 0x00000800
#define VXGE_COMPONENT_HAL_DMQ 0x00001000
#define VXGE_COMPONENT_HAL_UMQ 0x00002000
#define VXGE_COMPONENT_HAL_SQ 0x00004000
#define VXGE_COMPONENT_HAL_SRQ 0x00008000
#define VXGE_COMPONENT_HAL_CQRQ 0x00010000
#define VXGE_COMPONENT_HAL_NCE 0x00020000
#define VXGE_COMPONENT_HAL_STAG 0x00040000
#define VXGE_COMPONENT_HAL_TCP 0x00080000
#define VXGE_COMPONENT_HAL_LRO 0x00100000
#define VXGE_COMPONENT_HAL_SPDM 0x00200000
#define VXGE_COMPONENT_HAL_SESSION 0x00400000
#define VXGE_COMPONENT_HAL_STATS 0x00800000
#define VXGE_COMPONENT_HAL_MRPCIM 0x01000000
#define VXGE_COMPONENT_HAL_MRPCIM_IRQ 0x02000000
#define VXGE_COMPONENT_HAL_SRPCIM 0x04000000
#define VXGE_COMPONENT_HAL_SRPCIM_IRQ 0x08000000
#define VXGE_COMPONENT_HAL_DRIVER 0x10000000
/* space for CORE_XXX */
#define VXGE_COMPONENT_OSDEP 0x20000000
#define VXGE_COMPONENT_LL 0x40000000
#define VXGE_COMPONENT_ULD 0x80000000
#define VXGE_COMPONENT_ALL 0xffffffff
__EXTERN_END_DECLS
#endif /* VXGE_DEBUG_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_DEFS_H
#define VXGE_DEFS_H
#define VXGE_PCI_VENDOR_ID 0x17D5
#define VXGE_PCI_DEVICE_ID_TITAN_1 0x5833
#define VXGE_PCI_REVISION_TITAN_1 1
#define VXGE_PCI_DEVICE_ID_TITAN_1A 0x5833
#define VXGE_PCI_REVISION_TITAN_1A 2
#define VXGE_PCI_DEVICE_ID_TITAN_2 0x5834
#define VXGE_PCI_REVISION_TITAN_2 1
#define VXGE_MIN_FW_MAJOR_VERSION 1
#define VXGE_MIN_FW_MINOR_VERSION 8
#define VXGE_MIN_FW_BUILD_NUMBER 1
#define VXGE_DRIVER_VENDOR "Exar Corp."
#define VXGE_CHIP_FAMILY "X3100"
#define VXGE_SUPPORTED_MEDIA_0 "Fiber"
#define VXGE_DRIVER_NAME \
"Neterion X3100 10GbE PCIe Server Adapter Driver"
/*
* mBIT(loc) - set bit at offset
*/
#define mBIT(loc) (0x8000000000000000ULL >> (loc))
/*
* vBIT(val, loc, sz) - set bits at offset
*/
#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
/*
* bVALx(bits, loc) - Get the value of x bits at location
*/
#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF)
#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F)
#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F)
#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F)
#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF)
#define bVAL9(bits, loc) ((((u64)bits) >> (64-(loc+9))) & 0x1FF)
#define bVAL11(bits, loc) ((((u64)bits) >> (64-(loc+11))) & 0x7FF)
#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF)
#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
#define bVAL15(bits, loc) ((((u64)bits) >> (64-(loc+15))) & 0x7FFF)
#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
#define bVAL17(bits, loc) ((((u64)bits) >> (64-(loc+17))) & 0x1FFFF)
#define bVAL18(bits, loc) ((((u64)bits) >> (64-(loc+18))) & 0x3FFFF)
#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFFULL)
#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFFULL)
#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFFULL)
#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFFULL)
#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFFULL)
#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFFULL)
#define bVAL60(bits, loc) \
((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFFULL)
#define bVAL61(bits, loc) \
((((u64)bits) >> (64-(loc+61))) & 0x1FFFFFFFFFFFFFFFULL)
#define VXGE_HAL_VPATH_BMAP_START 47
#define VXGE_HAL_VPATH_BMAP_END 63
#define VXGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_MAX_VIRTUAL_PATHS 17
#define VXGE_HAL_MAX_FUNCTIONS 8
#define VXGE_HAL_MAX_ITABLE_ENTRIES 256
#define VXGE_HAL_MAX_RSS_KEY_SIZE 40
#define VXGE_HAL_MAC_MAX_WIRE_PORTS 2
#define VXGE_HAL_MAC_SWITCH_PORT 2
#define VXGE_HAL_MAC_MAX_AGGR_PORTS 2
#define VXGE_HAL_MAC_MAX_PORTS 3
#define VXGE_HAL_INTR_ALARM (1<<4)
#define VXGE_HAL_INTR_TX (1<<(3-VXGE_HAL_VPATH_INTR_TX))
#define VXGE_HAL_INTR_RX (1<<(3-VXGE_HAL_VPATH_INTR_RX))
#define VXGE_HAL_INTR_EINTA (1<<(3-VXGE_HAL_VPATH_INTR_EINTA))
#define VXGE_HAL_INTR_BMAP (1<<(3-VXGE_HAL_VPATH_INTR_BMAP))
#define VXGE_HAL_PCI_CONFIG_SPACE_SIZE VXGE_OS_PCI_CONFIG_SIZE
#define VXGE_HAL_DEFAULT_32 0xffffffff
#define VXGE_HAL_DEFAULT_64 0xffffffffffffffff
#define VXGE_HAL_DUMP_BUF_SIZE 0x10000
#define VXGE_HAL_VPD_BUFFER_SIZE 128
#define VXGE_HAL_VPD_LENGTH 80
/* Check whether an address is multicast. */
#define VXGE_HAL_IS_NULL(Address) (Address == 0x0000000000000000ULL)
/* Check whether an address is multicast. */
#define VXGE_HAL_IS_MULTICAST(Address) (Address & 0x0000010000000000ULL)
/* Check whether an address is broadcast. */
#define VXGE_HAL_IS_BROADCAST(Address) \
((Address & 0x0000FFFF00000000ULL) == 0x0000FFFF00000000ULL)
#define VXGE_HAL_IS_UNICAST(Address) \
(!(VXGE_HAL_IS_NULL(Address) || \
VXGE_HAL_IS_MULTICAST(Address) || \
VXGE_HAL_IS_BROADCAST(Address)))
/* frames sizes */
#define VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14
#define VXGE_HAL_HEADER_802_2_SIZE 3
#define VXGE_HAL_HEADER_SNAP_SIZE 5
#define VXGE_HAL_HEADER_VLAN_SIZE 4
#define VXGE_HAL_MAC_HEADER_MAX_SIZE \
(VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
VXGE_HAL_HEADER_802_2_SIZE + \
VXGE_HAL_HEADER_SNAP_SIZE)
#define VXGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64)
/* 32bit alignments */
/* A receive data corruption can occur resulting in either a single-bit or
double-bit ECC error being flagged in the ASIC if starting offset of a
buffer in single buffer mode is 0x2 to 0xa. Single bit ECC error will not
lock up the card but can hide the data corruption while the double-bit ECC
error will lock up the card. Limiting the starting offset of the buffers to
0x0, 0x1 or to a value greater than 0xF will workaround this issue.
VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
aligned. The start of buffer of 0x2 will cause this problem to occur.
To avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start
of buffer is outside of the problem causing offsets.
*/
#define VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 0x12
#define VXGE_HAL_HEADER_802_2_SNAP_ALIGN 2
#define VXGE_HAL_HEADER_802_2_ALIGN 3
#define VXGE_HAL_HEADER_SNAP_ALIGN 1
#define VXGE_HAL_MIN_MTU 46
#define VXGE_HAL_MAX_MTU 9600
#define VXGE_HAL_DEFAULT_MTU 1500
#define VXGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920
#if defined(__EXTERN_BEGIN_DECLS)
#undef __EXTERN_BEGIN_DECLS
#endif
#if defined(__EXTERN_END_DECLS)
#undef __EXTERN_END_DECLS
#endif
#if defined(__cplusplus)
#define __EXTERN_BEGIN_DECLS extern "C" {
#define __EXTERN_END_DECLS }
#else
#define __EXTERN_BEGIN_DECLS
#define __EXTERN_END_DECLS
#endif
__EXTERN_BEGIN_DECLS
/* --------------------------- common stuffs ------------------------------ */
/*
* VXGE_OS_DMA_REQUIRES_SYNC - should be defined or
* NOT defined in the Makefile
*/
#define VXGE_OS_DMA_CACHELINE_ALIGNED 0x1
/*
* Either STREAMING or CONSISTENT should be used.
* The combination of both or none is invalid
*/
#define VXGE_OS_DMA_STREAMING 0x2
#define VXGE_OS_DMA_CONSISTENT 0x4
#define VXGE_OS_SPRINTF_STRLEN 64
/* --------------------------- common stuffs ------------------------------ */
#ifndef VXGE_OS_LLXFMT
#define VXGE_OS_LLXFMT "%llx"
#endif
#ifndef VXGE_OS_LLDFMT
#define VXGE_OS_LLDFMT "%lld"
#endif
#ifndef VXGE_OS_STXFMT
#define VXGE_OS_STXFMT "%zx"
#endif
#ifndef VXGE_OS_STDFMT
#define VXGE_OS_STDFMT "%zd"
#endif
__EXTERN_END_DECLS
#endif /* VXGE_DEFS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_LIST_H
#define VXGE_LIST_H
__EXTERN_BEGIN_DECLS
/*
* struct vxge_list_t - List item.
* @prev: Previous list item.
* @next: Next list item.
*
* Item of a bi-directional linked list.
*/
typedef struct vxge_list_t {
struct vxge_list_t *prev;
struct vxge_list_t *next;
} vxge_list_t;
/*
* vxge_list_init - Initialize linked list.
* @header: first element of the list (head)
*
* Initialize linked list.
* See also: vxge_list_t {}.
*/
static inline void vxge_list_init(vxge_list_t *header)
{
vxge_assert(header != NULL);
header->next = header;
header->prev = header;
}
/*
* vxge_list_is_empty - Is the list empty?
* @header: first element of the list (head)
*
* Determine whether the bi-directional list is empty. Return '1' in
* case of 'empty'.
* See also: vxge_list_t {}.
*/
static inline int vxge_list_is_empty(vxge_list_t *header)
{
vxge_assert(header != NULL);
return (header->next == header);
}
/*
* vxge_list_first_get - Return the first item from the linked list.
* @header: first element of the list (head)
*
* Returns the next item from the header.
* Returns NULL if the next item is header itself
* See also: vxge_list_remove(), vxge_list_insert(), vxge_list_t {}.
*/
static inline vxge_list_t *vxge_list_first_get(vxge_list_t *header)
{
vxge_assert(header != NULL);
vxge_assert(header->next != NULL);
vxge_assert(header->prev != NULL);
if (header->next == header)
return (NULL);
else
return (header->next);
}
/*
* vxge_list_remove - Remove the specified item from the linked list.
* @item: element of the list
*
* Remove item from a list.
* See also: vxge_list_insert(), vxge_list_t {}.
*/
static inline void vxge_list_remove(vxge_list_t *item)
{
vxge_assert(item != NULL);
vxge_assert(item->next != NULL);
vxge_assert(item->prev != NULL);
item->next->prev = item->prev;
item->prev->next = item->next;
#if defined(VXGE_DEBUG_ASSERT)
item->next = item->prev = NULL;
#endif
}
/*
* vxge_list_insert - Insert a new item after the specified item.
* @new_item: new element of the list
* @prev_item: element of the list after which the new element is
* inserted
*
* Insert new item (new_item) after given item (prev_item).
* See also: vxge_list_remove(), vxge_list_insert_before(), vxge_list_t {}.
*/
static inline void vxge_list_insert(vxge_list_t *new_item,
vxge_list_t *prev_item)
{
vxge_assert(new_item != NULL);
vxge_assert(prev_item != NULL);
vxge_assert(prev_item->next != NULL);
new_item->next = prev_item->next;
new_item->prev = prev_item;
prev_item->next->prev = new_item;
prev_item->next = new_item;
}
/*
* vxge_list_insert_before - Insert a new item before the specified item.
* @new_item: new element of the list
* @next_item: element of the list after which the new element is inserted
*
* Insert new item (new_item) before given item (next_item).
*/
static inline void vxge_list_insert_before(vxge_list_t *new_item,
vxge_list_t * next_item)
{
vxge_assert(new_item != NULL);
vxge_assert(next_item != NULL);
vxge_assert(next_item->next != NULL);
new_item->next = next_item;
new_item->prev = next_item->prev;
next_item->prev->next = new_item;
next_item->prev = new_item;
}
#define vxge_list_for_each(_p, _h) \
for (_p = (_h)->next, vxge_os_prefetch(_p->next); _p != (_h); \
_p = _p->next, vxge_os_prefetch(_p->next))
#define vxge_list_for_each_safe(_p, _n, _h) \
for (_p = (_h)->next, _n = _p->next; _p != (_h); \
_p = _n, _n = _p->next)
#define vxge_list_for_each_prev_safe(_p, _n, _h) \
for (_p = (_h)->prev, _n = _p->prev; _p != (_h); \
_p = _n, _n = _p->prev)
#if defined(__GNUC__)
/*
* vxge_container_of - Given a member, return the containing structure.
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
* Cast a member of a structure out to the containing structure.
*/
#define vxge_container_of(ptr, type, member) (\
{ __typeof(((type *)0)->member) *__mptr = (ptr); \
(type *)(void *)((char *)__mptr - ((ptr_t)&((type *)0)->member)); })
#else
/* type unsafe version */
#define vxge_container_of(ptr, type, member) \
((type *)(void *)((char *)(ptr) - ((ptr_t)&((type *)0)->member)))
#endif
/*
* vxge_offsetof - Offset of the member in the containing structure.
* @t: struct name.
* @m: the name of the member within the struct.
*
* Return the offset of the member @m in the structure @t.
*/
#define vxge_offsetof(t, m) ((ptr_t)(&((t *)0)->m))
__EXTERN_END_DECLS
#endif /* VXGE_LIST_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_OS_DEBUG_H
#define VXGE_OS_DEBUG_H
__EXTERN_BEGIN_DECLS
#ifndef VXGE_DEBUG_INLINE_FUNCTIONS
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
#define vxge_trace_aux(hldev, vpid, fmt, ...) \
vxge_os_vasprintf(hldev, vpid, fmt, __VA_ARGS__)
#else
#define vxge_trace_aux(hldev, vpid, fmt, ...) \
vxge_os_vaprintf(hldev, vpid, fmt, __VA_ARGS__)
#endif
#define vxge_debug(module, level, hldev, vpid, fmt, ...) \
{ \
if (((u32)level <= \
((vxge_hal_device_t *)hldev)->debug_level) && \
((u32)module & \
((vxge_hal_device_t *)hldev)->debug_module_mask)) \
vxge_trace_aux((vxge_hal_device_h)hldev, \
vpid, fmt, __VA_ARGS__); \
}
/*
* vxge_debug_driver
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for OS Dependent functions. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
#define vxge_debug_driver(level, hldev, vpid, fmt, ...) \
if ((u32)level <= g_debug_level) \
vxge_os_vaprintf((vxge_hal_device_h)hldev, \
vpid, fmt, __VA_ARGS__);
#else
#define vxge_debug_driver(level, hldev, vpid, fmt, ...)
#endif
/*
* vxge_debug_osdep
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for OS Dependent functions. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
#if (VXGE_COMPONENT_OSDEP & VXGE_DEBUG_MODULE_MASK)
#define vxge_debug_osdep(level, hldev, vpid, fmt, ...) \
vxge_debug(VXGE_COMPONENT_OSDEP, level, hldev, vpid, fmt, __VA_ARGS__)
#else
#define vxge_debug_osdep(level, hldev, vpid, fmt, ...)
#endif
/*
* vxge_debug_ll
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for LL driver. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
#define vxge_debug_ll(level, hldev, vpid, fmt, ...) \
vxge_debug(VXGE_COMPONENT_LL, level, hldev, vpid, fmt, __VA_ARGS__)
#else
#define vxge_debug_ll(level, hldev, vpid, fmt, ...)
#endif
/*
* vxge_debug_uld
* @component: The Component mask
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for LL driver. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
#if (VXGE_COMPONENT_ULD & VXGE_DEBUG_MODULE_MASK)
#define vxge_debug_uld(component, level, hldev, vpid, fmt, ...) \
vxge_debug(component, level, hldev, vpid, fmt, __VA_ARGS__)
#else
#define vxge_debug_uld(level, hldev, vpid, fmt, ...)
#endif
#else /* VXGE_DEBUG_INLINE_FUNCTIONS */
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
#define vxge_trace_aux(hldev, vpid, fmt) \
vxge_os_vasprintf(hldev, vpid, fmt)
#else
#define vxge_trace_aux(hldev, vpid, fmt) \
vxge_os_vaprintf(hldev, vpid, fmt)
#endif
#define vxge_debug(module, level, hldev, vpid, fmt) \
{ \
if (((u32)level <= ((vxge_hal_device_t *)hldev)->debug_level) && \
((u32)module & ((vxge_hal_device_t *)hldev)->debug_module_mask))\
vxge_trace_aux((vxge_hal_device_h)hldev, vpid, fmt); \
}
/*
* vxge_debug_driver
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for OS Dependent functions. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
static inline void vxge_debug_driver(
vxge_debug_level_e level,
vxge_hal_device_h hldev,
u32 vpid,
char *fmt, ...)
{
#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
if ((u32) level <= g_debug_level)
vxge_os_vaprintf((vxge_hal_device_h) hldev, vpid, fmt);
#endif
}
/*
* vxge_debug_osdep
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for OS Dependent functions. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
static inline void vxge_debug_osdep(
vxge_debug_level_e level,
vxge_hal_device_h hldev,
u32 vpid,
char *fmt, ...)
{
#if (VXGE_COMPONENT_OSDEP & VXGE_DEBUG_MODULE_MASK)
vxge_debug(VXGE_COMPONENT_OSDEP, level, hldev, vpid, fmt)
#endif
}
/*
* vxge_debug_ll
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for LL driver. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
static inline void vxge_debug_ll(
vxge_debug_level_e level,
vxge_hal_device_h hldev,
u32 vpid,
char *fmt, ...)
{
#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
vxge_debug(VXGE_COMPONENT_LL, level, hldev, vpid, fmt)
#endif
}
/*
* vxge_debug_uld
* @component: The Component mask
* @level: level of debug verbosity.
* @hldev: HAL Device
* @vpid: Vpath id
* @fmt: printf like format string
*
* Provides logging facilities for LL driver. Can be customized
* with debug levels. Input parameters, except level, are the same
* as posix printf. This function may be compiled out if DEBUG macro
* was never defined.
* See also: vxge_debug_level_e{}.
*/
static inline void vxge_debug_uld(
u32 component,
vxge_debug_level_e level,
vxge_hal_device_h hldev,
u32 vpid,
char *fmt, ...)
{
#if (VXGE_COMPONENT_ULD & VXGE_DEBUG_MODULE_MASK)
vxge_debug(component, level, hldev, vpid, fmt)
#endif
}
#endif /* end of VXGE_DEBUG_INLINE_FUNCTIONS */
__EXTERN_END_DECLS
#endif /* VXGE_OS_DEBUG_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_OS_PAL_H
#define VXGE_OS_PAL_H
__EXTERN_BEGIN_DECLS
/* --------------------------- platform switch ------------------------------ */
/* platform specific header */
#include <dev/vxge/vxge-osdep.h>
#define IN
#define OUT
#if !defined(VXGE_OS_PLATFORM_64BIT) && !defined(VXGE_OS_PLATFORM_32BIT)
#error "either 32bit or 64bit switch must be defined!"
#endif
#if !defined(VXGE_OS_HOST_BIG_ENDIAN) && !defined(VXGE_OS_HOST_LITTLE_ENDIAN)
#error "either little endian or big endian switch must be defined!"
#endif
#if defined(VXGE_OS_PLATFORM_64BIT)
#define VXGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a5a5a5a5a
#else
#define VXGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a
#endif
#if defined(VXGE_DEBUG_ASSERT)
/*
* vxge_assert
* @test: C-condition to check
* @fmt: printf like format string
*
* This function implements traditional assert. By default assertions
* are enabled. It can be disabled by defining VXGE_DEBUG_ASSERT macro in
* compilation
* time.
*/
#define vxge_assert(test) { \
if (!(test)) vxge_os_bug("bad cond: "#test" at %s:%d\n", \
__FILE__, __LINE__); }
#else
#define vxge_assert(test)
#endif /* end of VXGE_DEBUG_ASSERT */
__EXTERN_END_DECLS
#endif /* VXGE_OS_PAL_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_QUEUE_H
#define VXGE_QUEUE_H
__EXTERN_BEGIN_DECLS
#define VXGE_QUEUE_BUF_SIZE 0x1000
#define VXGE_DEFAULT_EVENT_MAX_DATA_SIZE 16
/*
* enum vxge_queue_status_e - Enumerates return codes of the vxge_queue
* manipulation APIs.
* @VXGE_QUEUE_IS_FULL: Queue is full, need to grow.
* @VXGE_QUEUE_IS_EMPTY: Queue is empty.
* @VXGE_QUEUE_OUT_OF_MEMORY: Out of memory.
* @VXGE_QUEUE_NOT_ENOUGH_SPACE: Exceeded specified event size,
* see vxge_queue_consume().
* @VXGE_QUEUE_OK: Neither one of the codes listed above.
*
* Enumerates return codes of vxge_queue_consume()
* and vxge_queue_produce() APIs.
*/
typedef enum vxge_queue_status_e {
VXGE_QUEUE_OK = 0,
VXGE_QUEUE_IS_FULL = 1,
VXGE_QUEUE_IS_EMPTY = 2,
VXGE_QUEUE_OUT_OF_MEMORY = 3,
VXGE_QUEUE_NOT_ENOUGH_SPACE = 4
} vxge_queue_status_e;
typedef void *vxge_queue_h;
/*
* struct vxge_queue_item_t - Queue item.
* @item: List item. Note that the queue is "built" on top of
* the bi-directional linked list.
* @event_type: Event type. Includes (but is not restricted to)
* one of the vxge_hal_event_e {} enumerated types.
* @data_size: Size of the enqueued user data. Note that vxge_queue_t
* items are allowed to have variable sizes.
* @is_critical: For critical events, e.g. ECC.
* @context: Opaque (void *) "context", for instance event producer object.
*
* Item of the vxge_queue_t {}. The queue is protected
* in terms of multi-threaded concurrent access.
* See also: vxge_queue_t {}.
*/
typedef struct vxge_queue_item_t {
vxge_list_t item;
vxge_hal_event_e event_type;
u32 data_size;
u32 is_critical;
void *context;
} vxge_queue_item_t;
/*
* function vxge_queued_f - Item-enqueued callback.
* @data: Per-queue context independent of the event. E.g., device handle.
* @event_type: HAL or ULD-defined event type. Note that HAL own
* events are enumerated by vxge_hal_event_e {}.
*
* Per-queue optional callback. If not NULL, called by HAL each
* time an event gets added to the queue.
*/
typedef void (*vxge_queued_f) (void *data, u32 event_type);
/*
* struct vxge_queue_t - Protected dynamic queue of variable-size items.
* @start_ptr: Points to the start of the queue.
* @end_ptr: Points to the end of the queue.
* @head_ptr: Points to the head of the queue. It gets changed during queue
* produce/consume operations.
* @tail_ptr: Points to the tail of the queue. It gets changed during queue
* produce/consume operations.
* @lock: Lock for queue operations(syncronization purpose).
* @pages_initial:Number of pages to be initially allocated at the time
* of queue creation.
* @pages_max: Max number of pages that can be allocated in the queue.
* @pages_current: Number of pages currently allocated
* @list_head: Points to the list of queue elements that are produced, but yet
* to be consumed.
* @hldev: HAL device handle
* @pdev: PCI device handle
* @irqh: PCI device IRQ handle.
* @queued_func: Optional callback function to be called each time a new
* item is added to the queue.
* @queued_data: Arguments to the callback function.
* @has_critical_event: Non-zero, if the queue contains a critical event,
* see vxge_hal_event_e {}.
* Protected dynamically growing queue. The queue is used to support multiple
* producer/consumer type scenarios. The queue is a strict FIFO: first come
* first served.
* Queue users may "produce" (see vxge_queue_produce()) and "consume"
* (see vxge_queue_consume()) items (a.k.a. events) variable sizes.
* See also: vxge_queue_item_t {}.
*/
typedef struct vxge_queue_t {
void *start_ptr;
void *end_ptr;
void *head_ptr;
void *tail_ptr;
spinlock_t lock;
u32 pages_initial;
u32 pages_max;
u32 pages_current;
vxge_list_t list_head;
vxge_hal_device_h hldev;
pci_dev_h pdev;
pci_irq_h irqh;
vxge_queued_f queued_func;
void *queued_data;
u32 has_critical_event;
} vxge_queue_t;
/* ========================== PUBLIC API ================================= */
/*
* vxge_queue_create - Create protected first-in-first-out queue.
* @devh: HAL device handle.
* @pages_initial: Number of pages to be initially allocated at the
* time of queue creation.
* @pages_max: Max number of pages that can be allocated in the queue.
* @queued_func: Optional callback function to be called each time a new item is
* added to the queue.
* @queued_data: Argument to the callback function.
*
* Create protected (fifo) queue.
*
* Returns: Pointer to vxge_queue_t structure,
* NULL - on failure.
*
* See also: vxge_queue_item_t {}, vxge_queue_destroy().
*/
vxge_queue_h
vxge_queue_create(vxge_hal_device_h devh,
u32 pages_initial,
u32 pages_max,
vxge_queued_f queued_func,
void *queued_data);
/*
* vxge_queue_destroy - Destroy vxge_queue_t object.
* @queueh: Queue handle.
*
* Destroy the specified vxge_queue_t object.
*
* See also: vxge_queue_item_t {}, vxge_queue_create().
*/
void
vxge_queue_destroy(vxge_queue_h queueh);
/*
* vxge_queue_item_data - Get item's data.
* @item: Queue item.
*
* Returns: item data(variable size). Note that vxge_queue_t
* contains items comprized of a fixed vxge_queue_item_t "header"
* and a variable size data. This function returns the variable
* user-defined portion of the queue item.
*/
void *
vxge_queue_item_data(vxge_queue_item_t *item);
/*
* vxge_queue_produce - Enqueue an item (see vxge_queue_item_t {})
* into the specified queue.
* @queueh: Queue handle.
* @event_type: Event type. One of the enumerated event types
* that both consumer and producer "understand".
* For an example, please refer to vxge_hal_event_e.
* @context: Opaque (void *) "context", for instance event producer object.
* @is_critical: For critical event, e.g. ECC.
* @data_size: Size of the @data.
* @data: User data of variable @data_size that is _copied_ into
* the new queue item (see vxge_queue_item_t {}). Upon return
* from the call the @data memory can be re-used or released.
*
* Enqueue a new item.
*
* Returns: VXGE_QUEUE_OK - success.
* VXGE_QUEUE_IS_FULL - Queue is full.
* VXGE_QUEUE_OUT_OF_MEMORY - Memory allocation failed.
*
* See also: vxge_queue_item_t {}, vxge_queue_consume().
*/
vxge_queue_status_e
vxge_queue_produce(vxge_queue_h queueh,
u32 event_type,
void *context,
u32 is_critical,
const u32 data_size,
void *data);
/*
* vxge_queue_produce_context - Enqueue context.
* @queueh: Queue handle.
* @event_type: Event type. One of the enumerated event types
* that both consumer and producer "understand".
* For an example, please refer to vxge_hal_event_e.
* @context: Opaque (void *) "context", for instance event producer object.
*
* Enqueue Context.
*
* Returns: VXGE_QUEUE_OK - success.
* VXGE_QUEUE_IS_EMPTY - Queue is empty.
* VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
* is too small to accomodate an item from the queue.
*
* See also: vxge_queue_item_t {}, vxge_queue_produce().
*/
static inline vxge_queue_status_e
/* LINTED */
vxge_queue_produce_context(vxge_queue_h queueh,
u32 event_type,
void *context)
{
return (vxge_queue_produce(queueh, event_type, context, 0, 0, 0));
}
/*
* vxge_queue_consume - Dequeue an item from the specified queue.
* @queueh: Queue handle.
* @data_max_size: Maximum expected size of the item.
* @item: Memory area into which the item is _copied_ upon return
* from the function.
*
* Dequeue an item from the queue. The caller is required to provide
* enough space for the item.
*
* Returns: VXGE_QUEUE_OK - success.
* VXGE_QUEUE_IS_EMPTY - Queue is empty.
* VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
* is too small to accomodate an item from the queue.
*
* See also: vxge_queue_item_t {}, vxge_queue_produce().
*/
vxge_queue_status_e
vxge_queue_consume(vxge_queue_h queueh,
u32 data_max_size,
vxge_queue_item_t *item);
/*
* vxge_queue_flush - Flush, or empty, the queue.
* @queueh: Queue handle.
*
* Flush the queue, i.e. make it empty by consuming all events
* without invoking the event processing logic (callbacks, etc.)
*/
void
vxge_queue_flush(vxge_queue_h queueh);
/*
* vxge_io_queue_grow - Dynamically increases the size of the queue.
* @queueh: Queue handle.
*
* This function is called in the case of no slot avaialble in the queue
* to accomodate the newly received event.
* Note that queue cannot grow beyond the max size specified for the
* queue.
*
* Returns VXGE_QUEUE_OK: On success.
* VXGE_QUEUE_OUT_OF_MEMORY : No memory is available.
*/
vxge_queue_status_e
vxge_io_queue_grow(vxge_queue_h qh);
/*
* vxge_queue_get_reset_critical - Check for critical events in the queue,
* @queueh: Queue handle.
*
* Check for critical event(s) in the queue, and reset the
* "has-critical-event" flag upon return.
* Returns: 1 - if the queue contains atleast one critical event.
* 0 - If there are no critical events in the queue.
*/
u32
vxge_queue_get_reset_critical(vxge_queue_h queueh);
__EXTERN_END_DECLS
#endif /* VXGE_QUEUE_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_MGMT_H
#define VXGE_HAL_MGMT_H
__EXTERN_BEGIN_DECLS
/*
* struct vxge_hal_mgmt_about_info_t - About info.
* @vendor: PCI Vendor ID.
* @device: PCI Device ID.
* @subsys_vendor: PCI Subsystem Vendor ID.
* @subsys_device: PCI Subsystem Device ID.
* @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
* @vendor_name: Exar Corp.
* @chip_name: X3100.
* @media: Fiber, copper.
* @hal_major: HAL major version number.
* @hal_minor: HAL minor version number.
* @hal_fix: HAL fix number.
* @hal_build: HAL build number.
* @ll_major: Link-layer ULD major version number.
* @ll_minor: Link-layer ULD minor version number.
* @ll_fix: Link-layer ULD fix version number.
* @ll_build: Link-layer ULD build number.
*/
typedef struct vxge_hal_mgmt_about_info_t {
u16 vendor;
u16 device;
u16 subsys_vendor;
u16 subsys_device;
u8 board_rev;
char vendor_name[16];
char chip_name[16];
char media[16];
char hal_major[4];
char hal_minor[4];
char hal_fix[4];
char hal_build[16];
char ll_major[4];
char ll_minor[4];
char ll_fix[4];
char ll_build[16];
} vxge_hal_mgmt_about_info_t;
/*
* vxge_hal_mgmt_about - Retrieve about info.
* @devh: HAL device handle.
* @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
* @size: Pointer to buffer containing the Size of the @buffer_info.
* HAL will return an error if the size is smaller than
* sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
*
* Retrieve information such as PCI device and vendor IDs, board
* revision number, HAL version number, etc.
*
* Returns: VXGE_HAL_OK - success;
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
* VXGE_HAL_FAIL - Failed to retrieve the information.
*
* See also: vxge_hal_mgmt_about_info_t {}.
*/
vxge_hal_status_e
vxge_hal_mgmt_about(vxge_hal_device_h devh,
vxge_hal_mgmt_about_info_t *about_info,
u32 *size);
/*
* vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
* @devh: HAL device handle.
* @buffer: Buffer for PCI configuration space.
* @size: Pointer to buffer containing the Size of the @buffer.
* HAL will return an error if the size is smaller than
* sizeof(vxge_hal_pci_config_t) and returns required size in this field
*
* Get PCI configuration. Permits to retrieve at run-time configuration
* values that were used to configure the device at load-time.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
*
*/
vxge_hal_status_e
vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size);
/*
* struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities
* @pm_cap_ver: Version
* @pm_cap_pme_clock: PME clock required
* @pm_cap_aux_power: Auxilliary power support
* @pm_cap_dsi: Device specific initialization
* @pm_cap_aux_current: auxiliary current requirements
* @pm_cap_cap_d0: D1 power state support
* @pm_cap_cap_d1: D2 power state support
* @pm_cap_pme_d0: PME# can be asserted from D3hot
* @pm_cap_pme_d1: PME# can be asserted from D3hot
* @pm_cap_pme_d2: PME# can be asserted from D3hot
* @pm_cap_pme_d3_hot: PME# can be asserted from D3hot
* @pm_cap_pme_d3_cold: PME# can be asserted from D3cold
* @pm_ctrl_state: Current power state (D0 to D3)
* @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0
* @pm_ctrl_pme_enable: PME pin enable
* @pm_ctrl_pme_data_sel: Data select
* @pm_ctrl_pme_data_scale: Data scale
* @pm_ctrl_pme_status: PME pin status
* @pm_ppb_ext_b2_b3: Stop clock when in D3hot
* @pm_ppb_ext_ecc_en: Bus power/clock control enable
* @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel
*
* Power Management Capabilities structure
*/
typedef struct vxge_hal_mgmt_pm_cap_t {
u32 pm_cap_ver;
u32 pm_cap_pme_clock;
u32 pm_cap_aux_power;
u32 pm_cap_dsi;
u32 pm_cap_aux_current;
u32 pm_cap_cap_d0;
u32 pm_cap_cap_d1;
u32 pm_cap_pme_d0;
u32 pm_cap_pme_d1;
u32 pm_cap_pme_d2;
u32 pm_cap_pme_d3_hot;
u32 pm_cap_pme_d3_cold;
u32 pm_ctrl_state;
u32 pm_ctrl_no_soft_reset;
u32 pm_ctrl_pme_enable;
u32 pm_ctrl_pme_data_sel;
u32 pm_ctrl_pme_data_scale;
u32 pm_ctrl_pme_status;
u32 pm_ppb_ext_b2_b3;
u32 pm_ppb_ext_ecc_en;
u32 pm_data_reg;
} vxge_hal_mgmt_pm_cap_t;
/*
* vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
* @devh: HAL device handle.
* @pm_cap: Power Management Capabilities
*
* Return the pm capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
vxge_hal_mgmt_pm_cap_t *pm_cap);
/*
* struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities
* @sid_number_of_slots: Number of solts
* @sid_first_in_chasis: First in chasis flag
* @sid_chasis_number: Chasis Number
*
* Slot ID Capabilities structure
*/
typedef struct vxge_hal_mgmt_sid_cap_t {
u32 sid_number_of_slots;
u32 sid_first_in_chasis;
u32 sid_chasis_number;
} vxge_hal_mgmt_sid_cap_t;
/*
* vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
* @devh: HAL device handle.
* @sid_cap: Slot Id Capabilities
*
* Return the pm capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
vxge_hal_mgmt_sid_cap_t *sid_cap);
/*
* struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities
* @enable: 1 - MSI enabled, 0 - MSI not enabled
* @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only)
* @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only
* (valid for get only)
* @vectors_allocated: Number of vectors allocated
* 000-1 vectors
* 001-2 vectors
* 010-4 vectors
* 011-8 vectors
* 100-16 vectors
* 101-32 vectors
* @max_vectors_capable: Maximum number of vectors that can be allocated
* (valid for get only)
* 000-1 vectors
* 001-2 vectors
* 010-4 vectors
* 011-8 vectors
* 100-16 vectors
* 101-32 vectors
* @address: MSI address
* @data: MSI Data
* @mask_bits: For each Mask bit that is set, the function is prohibited from
* sending the associated message
* @pending_bits: For each Pending bit that is set, the function has a
* pending associated message.
*
* MSI Capabilities structure
*/
typedef struct vxge_hal_mgmt_msi_cap_t {
u32 enable;
u32 is_pvm_capable;
u32 is_64bit_addr_capable;
u32 vectors_allocated;
u32 max_vectors_capable;
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4
#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5
u64 address;
u16 data;
u32 mask_bits;
u32 pending_bits;
} vxge_hal_mgmt_msi_cap_t;
/*
* vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
* @devh: HAL device handle.
* @msi_cap: MSI Capabilities
*
* Return the msi capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
vxge_hal_mgmt_msi_cap_t *msi_cap);
/*
* vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
* @devh: HAL device handle.
* @msi_cap: MSI Capabilities
*
* Sets the msi capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
vxge_hal_mgmt_msi_cap_t *msi_cap);
/*
* struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities
* @enable: 1 - MSIX enabled, 0 - MSIX not enabled
* @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors
* @table_size: MSIX Table Size-1
* @table_offset: Offset of the table from the table_bir
* @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
* @pba_offset: Offset of the PBA from the pba_bir
* @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
*
* MSIS Capabilities structure
*/
typedef struct vxge_hal_mgmt_msix_cap_t {
u32 enable;
u32 mask_all_vect;
u32 table_size;
u32 table_offset;
u32 table_bir;
#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0
#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2
#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4
u32 pba_offset;
u32 pba_bir;
#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0
#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2
#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4
} vxge_hal_mgmt_msix_cap_t;
/*
* vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
* @devh: HAL device handle.
* @msix_cap: MSIX Capabilities
*
* Return the msix capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
vxge_hal_mgmt_msix_cap_t *msix_cap);
/*
* struct vxge_hal_pci_err_cap_t - PCI Error Capabilities
* @pci_err_header: Error header
* @pci_err_uncor_status: Uncorrectable error status
* 0x00000001 - Training
* 0x00000010 - Data Link Protocol
* 0x00001000 - Poisoned TLP
* 0x00002000 - Flow Control Protocol
* 0x00004000 - Completion Timeout
* 0x00008000 - Completer Abort
* 0x00010000 - Unexpected Completion
* 0x00020000 - Receiver Overflow
* 0x00040000 - Malformed TLP
* 0x00080000 - ECRC Error Status
* 0x00100000 - Unsupported Request
* @pci_err_uncor_mask: Uncorrectable mask
* @pci_err_uncor_server: Uncorrectable server
* @pci_err_cor_status: Correctable status
* 0x00000001 - Receiver Error Status
* 0x00000040 - Bad TLP Status
* 0x00000080 - Bad DLLP Status
* 0x00000100 - REPLAY_NUM Rollover
* 0x00001000 - Replay Timer Timeout
* VXGE_HAL_PCI_ERR_COR_MASK 20
* @pci_err_cap: Error capability
* 0x00000020 - ECRC Generation Capable
* 0x00000040 - ECRC Generation Enable
* 0x00000080 - ECRC Check Capable
* 0x00000100 - ECRC Check Enable
* @err_header_log: Error header log
* @unused: Reserved
* @pci_err_root_command: Error root command
* @pci_err_root_status: Error root status
* @pci_err_root_cor_src: Error root correctible source
* @pci_err_root_src: Error root source
*
* MSIS Capabilities structure
*/
typedef struct vxge_hal_pci_err_cap_t {
u32 pci_err_header;
u32 pci_err_uncor_status;
#define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */
#define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */
#define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */
#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
#define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */
#define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
#define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
#define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */
#define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */
u32 pci_err_uncor_mask;
u32 pci_err_uncor_server;
u32 pci_err_cor_status;
#define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */
#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
#define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */
#define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */
#define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */
u32 pci_err_cap;
#define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */
#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */
#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */
#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */
#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */
u32 err_header_log;
#define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */
u32 unused[3];
u32 pci_err_root_command;
u32 pci_err_root_status;
u32 pci_err_root_cor_src;
u32 pci_err_root_src;
} vxge_hal_pci_err_cap_t;
/*
* vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
* @devh: HAL device handle.
* @err_cap: PCI-E Extended Error Capabilities
*
* Return the PCI-E Extended Error capabilities
*/
vxge_hal_status_e
vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
vxge_hal_pci_err_cap_t *err_cap);
/*
* vxge_hal_mgmt_driver_config - Retrieve driver configuration.
* @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
* @size: Pointer to buffer containing the Size of the @drv_config.
* HAL will return an error if the size is smaller than
* sizeof(vxge_hal_driver_config_t) and returns required size in this field
*
* Get driver configuration. Permits to retrieve at run-time configuration
* values that were used to configure the device at load-time.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
*
* See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
*/
vxge_hal_status_e
vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size);
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
/*
* vxge_hal_mgmt_trace_read - Read trace buffer contents.
* @buffer: Buffer to store the trace buffer contents.
* @buf_size: Size of the buffer.
* @offset: Offset in the internal trace buffer to read data.
* @read_length: Size of the valid data in the buffer.
*
* Read HAL trace buffer contents starting from the offset
* upto the size of the buffer or till EOF is reached.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_trace_read(char *buffer,
unsigned buf_size,
unsigned *offset,
unsigned *read_length);
#endif
/*
* vxge_hal_mgmt_device_config - Retrieve device configuration.
* @devh: HAL device handle.
* @dev_config: Device configuration, see vxge_hal_device_config_t {}.
* @size: Pointer to buffer containing the Size of the @dev_config.
* HAL will return an error if the size is smaller than
* sizeof(vxge_hal_device_config_t) and returns required size in this field
*
* Get device configuration. Permits to retrieve at run-time configuration
* values that were used to initialize and configure the device.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
*
* See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
*/
vxge_hal_status_e
vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
vxge_hal_device_config_t *dev_config, u32 *size);
/*
* vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
* offset.
* @devh: HAL device handle.
* @offset: Offset in the 256 byte PCI configuration space.
* @value_bits: 8, 16, or 32 (bits) to read.
* @value: Value returned by HAL.
*
* Read PCI configuration, given device and offset in the PCI space.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
* valid.
* VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
* values(8/16/32).
*
*/
vxge_hal_status_e
vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
int value_bits, u32 *value);
/*
* enum vxge_hal_mgmt_reg_type_e - Register types.
*
* @vxge_hal_mgmt_reg_type_legacy: Legacy registers
* @vxge_hal_mgmt_reg_type_toc: TOC Registers
* @vxge_hal_mgmt_reg_type_common: Common Registers
* @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers
* @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers
* @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers
* @vxge_hal_mgmt_reg_type_srpcim: srpcim registers
* @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers
* @vxge_hal_mgmt_reg_type_vpath: vpath registers
*
* Register type enumaration
*/
typedef enum vxge_hal_mgmt_reg_type_e {
vxge_hal_mgmt_reg_type_legacy = 0,
vxge_hal_mgmt_reg_type_toc = 1,
vxge_hal_mgmt_reg_type_common = 2,
vxge_hal_mgmt_reg_type_memrepair = 3,
vxge_hal_mgmt_reg_type_pcicfgmgmt = 4,
vxge_hal_mgmt_reg_type_mrpcim = 5,
vxge_hal_mgmt_reg_type_srpcim = 6,
vxge_hal_mgmt_reg_type_vpmgmt = 7,
vxge_hal_mgmt_reg_type_vpath = 8
} vxge_hal_mgmt_reg_type_e;
/*
* vxge_hal_mgmt_reg_read - Read X3100 register.
* @devh: HAL device handle.
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
* @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
* ignored for others
* @offset: Register offset in the register space qualified by the type and
* index.
* @value: Register value. Returned by HAL.
* Read X3100 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
vxge_hal_mgmt_reg_type_e type,
u32 index,
u32 offset,
u64 *value);
/*
* vxge_hal_mgmt_reg_Write - Write X3100 register.
* @devh: HAL device handle.
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
* @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
* ignored for others
* @offset: Register offset in the register space qualified by the type and
* index.
* @value: Register value to be written.
* Write X3100 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
vxge_hal_mgmt_reg_type_e type,
u32 index,
u32 offset,
u64 value);
/*
* vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
* from bar0.
* @devh: HAL device handle.
* @offset: Register offset from bar0
* @value: Register value. Returned by HAL.
* Read X3100 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
u32 offset,
u64 *value);
/*
* vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
* from bar1.
* @devh: HAL device handle.
* @offset: Register offset from bar1
* @value: Register value. Returned by HAL.
* Read X3100 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
u32 offset,
u64 *value);
/*
* vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
* from bar0.
* @devh: HAL device handle.
* @offset: Register offset from bar0
* @value: Register value to be written.
* Write X3100 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
*
*/
vxge_hal_status_e
vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
u32 offset,
u64 value);
/*
* vxge_hal_mgmt_register_config - Retrieve register configuration.
* @devh: HAL device handle.
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
* @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
* ignored for others
* @config: Device configuration, see vxge_hal_device_config_t {}.
* @size: Pointer to buffer containing the Size of the @reg_config.
* HAL will return an error if the size is smaller than
* requested register space and returns required size in this field
*
* Get register configuration. Permits to retrieve register values.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
*
*/
vxge_hal_status_e
vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
vxge_hal_mgmt_reg_type_e type,
u32 vp_id,
u8 *config,
u32 *size);
/*
* vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
* @devh: HAL device handle.
* @port: Port number
*
* This routine only gets the temperature for XFP modules. Also, updating of the
* NVRAM can sometimes fail and so the reading we might get may not be uptodate.
*/
u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port);
/*
* vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
* @devh: HAL device handle.
* @port: Port number
* @enable:Boolean set to 1 to enable and 0 to disable.
*
* Enable or disable PMA loopback.
* Return value:
* 0 on success.
*/
vxge_hal_status_e
vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
/*
* vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
* @devh: HAL device handle.
* @port: Port number
* @enable:Boolean set to 1 to enable and 0 to disable.
*
* Enable or disable xgmii loopback.
* Return value:
* 0 on success.
*/
vxge_hal_status_e
vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_MGMT_H */

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sys/dev/vxge/include/vxgehal-mgmtaux.h Normal file
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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_MGMTAUX_H
#define VXGE_HAL_MGMTAUX_H
__EXTERN_BEGIN_DECLS
/*
* vxge_hal_aux_about_read - Retrieve and format about info.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Retrieve about info (using vxge_hal_mgmt_about()) and sprintf it
* into the provided @retbuf.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
* VXGE_HAL_FAIL - Failed to retrieve the information.
*
* See also: vxge_hal_mgmt_about(), vxge_hal_aux_device_dump().
*/
vxge_hal_status_e vxge_hal_aux_about_read(vxge_hal_device_h devh, int bufsize,
char *retbuf, int *retsize);
/*
* vxge_hal_aux_driver_config_read - Read Driver configuration.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read driver configuration,
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
*
* See also: vxge_hal_aux_device_config_read().
*/
vxge_hal_status_e
vxge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_pci_config_read - Retrieve and format PCI Configuration
* info.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Retrieve about info (using vxge_hal_mgmt_pci_config()) and sprintf it
* into the provided @retbuf.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
*
* See also: vxge_hal_mgmt_pci_config(), vxge_hal_aux_device_dump().
*/
vxge_hal_status_e
vxge_hal_aux_pci_config_read(vxge_hal_device_h devh,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_device_config_read - Read device configuration.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device configuration,
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
*
* See also: vxge_hal_aux_driver_config_read().
*/
vxge_hal_status_e
vxge_hal_aux_device_config_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_bar0_read - Read and format X3100 BAR0 register.
* @devh: HAL device handle.
* @offset: Register offset in the BAR0 space.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read X3100 register from BAR0 space. The result is formatted as an
* ascii string.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
* valid.
*
* See also: vxge_hal_mgmt_reg_read().
*/
vxge_hal_status_e
vxge_hal_aux_bar0_read(vxge_hal_device_h devh,
unsigned int offset, int bufsize, char *retbuf,
int *retsize);
/*
* vxge_hal_aux_bar1_read - Read and format X3100 BAR1 register.
* @devh: HAL device handle.
* @offset: Register offset in the BAR1 space.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read X3100 register from BAR1 space. The result is formatted as ascii string
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
* valid.
*
*/
vxge_hal_status_e
vxge_hal_aux_bar1_read(vxge_hal_device_h devh,
unsigned int offset, int bufsize, char *retbuf,
int *retsize);
/*
* vxge_hal_aux_bar0_write - Write BAR0 register.
* @devh: HAL device handle.
* @offset: Register offset in the BAR0 space.
* @value: Regsister value (to write).
*
* Write BAR0 register.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
* valid.
*
* See also: vxge_hal_mgmt_reg_write().
*/
vxge_hal_status_e
vxge_hal_aux_bar0_write(vxge_hal_device_h devh,
unsigned int offset, u64 value);
/*
* vxge_hal_aux_stats_vpath_hw_read - Read vpath hardware statistics.
* @vpath_handle: HAL Vpath handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read vpath hardware statistics. This is a subset of stats counters
* from vxge_hal_vpath_stats_hw_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_vpath_hw_read(
vxge_hal_vpath_h vpath_handle,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_stats_device_hw_read - Read device hardware statistics.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device hardware statistics. This is a subset of stats counters
* from vxge_hal_device_stats_hw_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_device_hw_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_stats_vpath_sw_fifo_read - Read vpath fifo software statistics.
* @vpath_handle: HAL Vpath handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read vpath fifo software statistics. This is a subset of stats counters
* from vxge_hal_vpath_stats_sw_fifo_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_fifo_read(
vxge_hal_vpath_h vpath_handle,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_stats_vpath_sw_ring_read - Read vpath ring software statistics.
* @vpath_handle: HAL Vpath handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read vpath ring software statistics. This is a subset of stats counters
* from vxge_hal_vpath_stats_sw_ring_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_ring_read(
vxge_hal_vpath_h vpath_handle,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_stats_vpath_sw_err_read - Read vpath err software statistics.
* @vpath_handle: HAL Vpath handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read vpath err software statistics. This is a subset of stats counters
* from vxge_hal_vpath_stats_sw_err_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_err_read(
vxge_hal_vpath_h vpath_handle,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_stats_vpath_sw_read - Read vpath soft statistics.
* @vpath_handle: HAL Vpath handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device hardware statistics. This is a subset of stats counters
* from vxge_hal_vpath_stats_sw_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_read(
vxge_hal_vpath_h vpath_handle,
int bufsize,
char *retbuf,
int *retsize);
/*
* vxge_hal_aux_stats_device_sw_read - Read device software statistics.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device software statistics. This is a subset of stats counters
* from vxge_hal_device_stats_sw_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_device_sw_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_stats_device_sw_err_read - Read device software error statistics
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device software error statistics. This is a subset of stats counters
* from vxge_hal_device_stats_sw_info_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_device_sw_err_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_stats_device_read - Read device statistics.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device statistics. This is a subset of stats counters
* from vxge_hal_device_stats_t {}.
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_device_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_stats_xpak_read - Read device xpak statistics.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read device xpak statistics. This is valid for function 0 device only
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_xpak_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_stats_mrpcim_read - Read device mrpcim statistics.
* @devh: HAL device handle.
* @bufsize: Buffer size.
* @retbuf: Buffer pointer.
* @retsize: Size of the result. Cannot be greater than @bufsize.
*
* Read mrpcim statistics. This is valid for function 0 device only
*
*/
vxge_hal_status_e
vxge_hal_aux_stats_mrpcim_read(vxge_hal_device_h devh,
int bufsize, char *retbuf, int *retsize);
/*
* vxge_hal_aux_vpath_ring_dump - Dump vpath ring.
* @vpath_handle: Vpath handle.
*
* Dump vpath ring.
*/
vxge_hal_status_e
vxge_hal_aux_vpath_ring_dump(vxge_hal_vpath_h vpath_handle);
/*
* vxge_hal_aux_vpath_fifo_dump - Dump vpath fifo.
* @vpath_handle: Vpath handle.
*
* Dump vpath fifo.
*/
vxge_hal_status_e
vxge_hal_aux_vpath_fifo_dump(vxge_hal_vpath_h vpath_handle);
/*
* vxge_hal_aux_device_dump - Dump driver "about" info and device state.
* @devh: HAL device handle.
*
* Dump driver & device "about" info and device state,
* including all BAR0 registers, hardware and software statistics, PCI
* configuration space.
*/
vxge_hal_status_e vxge_hal_aux_device_dump(vxge_hal_device_h devh);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_MGMTAUX_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_TYPES_H
#define VXGE_HAL_TYPES_H
__EXTERN_BEGIN_DECLS
/*
* enum vxge_hal_reopen_e - Open, close, or reopen option.
* @VXGE_HAL_RESET_ONLY: Do not (de)allocate
* @VXGE_HAL_OPEN_NORMAL: Do (de)allocate
*
* Enumerates options used with ring, fifo, sq, srq, cqrq, dmq and umq
* open and close operations. The @VXGE_HAL_RESET_ONLY can be used when
* resetting the device; in this case there is actually no need to free
* and then again malloc the memory (including DMA-able memory).
*/
typedef enum vxge_hal_reopen_e {
VXGE_HAL_RESET_ONLY = 1,
VXGE_HAL_OPEN_NORMAL = 2
} vxge_hal_reopen_e;
/*
* struct vxge_hal_version_t - HAL version info
* @version_major: Major version
* @version_minor: Minor version
* @version_fix: version fix
* @version_build: Version Build
*
* Structure to store version info
*/
typedef struct vxge_hal_version_t {
u32 version_major;
u32 version_minor;
u32 version_fix;
u32 version_build;
} vxge_hal_version_t;
/*
* VXGE_HAL_ETH_ALEN
*/
#define VXGE_HAL_ETH_ALEN 6
/*
* typedef macaddr_t - Ethernet address type
*/
typedef u8 macaddr_t[VXGE_HAL_ETH_ALEN];
/*
* struct vxge_hal_ipv4 - IP version 4 address type
* @addr: IP address
*/
typedef struct vxge_hal_ipv4 {
u32 addr;
} vxge_hal_ipv4;
/*
* struct vxge_hal_ipv6 - IP version 6 address type
* @addr: IP address
*/
typedef struct vxge_hal_ipv6 {
u64 addr[2];
} vxge_hal_ipv6;
/*
* union vxge_hal_ipaddr_t - IP address type
* @ipv4: IP V4 address
* @ipv6: IP V6 address
*/
typedef union vxge_hal_ipaddr_t {
vxge_hal_ipv4 ipv4;
vxge_hal_ipv6 ipv6;
} vxge_hal_ipaddr_t;
/*
* typedef vxge_hal_obj_id_t - Object Id type used for Session,
* SRQ, CQRQ, STAG, LRO, SPDM etc objects
*/
typedef u64 vxge_hal_obj_id_t;
/* basic handles */
/*
* typedef vxge_hal_device_h - Handle to the adapter object
*/
typedef void *vxge_hal_device_h;
/*
* typedef vxge_hal_vpath_h - Handle to the virtual path object returned to LL
*/
typedef void *vxge_hal_vpath_h;
/*
* typedef vxge_hal_client_h - Handle passed by client for client's private data
*/
typedef void *vxge_hal_client_h;
/*
* typedef vxge_hal_ring_h - Handle to the ring object used for non offload
* receive
*/
typedef void *vxge_hal_ring_h;
/*
* typedef vxge_hal_fifo_h - Handle to the fifo object used for non offload send
*/
typedef void *vxge_hal_fifo_h;
/*
* typedef vxge_hal_txdl_h - Handle to the transmit desriptor list object used
* for nonoffload send
*/
typedef void *vxge_hal_txdl_h;
/*
* typedef vxge_hal_rxd_h - Handle to the receive desriptor object used for
* nonoffload receive
*/
typedef void *vxge_hal_rxd_h;
/*
* typedef vxge_hal_up_msg_h - Handle to the up message queue
*/
typedef void *vxge_hal_up_msg_h;
/*
* typedef vxge_hal_down_msg_h - Handle to the down message queue
*/
typedef void *vxge_hal_down_msg_h;
/*
* typedef vxge_hal_callback_h - Handle to callback function
*/
typedef void *vxge_hal_callback_h;
/*
* enum vxge_hal_message_type_e - Enumerated message types.
*
* @VXGE_HAL_MSG_TYPE_NCE_CREATE_REQ: The NCE Create Request
* message is used by the host to create an NCE on the adapter.
* @VXGE_HAL_MSG_TYPE_NCE_CREATE_RESP:The NCE Create Response
* message is sent in response to the NCE Create Request
* message from the host to indicate the status of the operation
* and return the NCE ID.
* @VXGE_HAL_MSG_TYPE_NCE_DELETE_REQ:The NCE Delete Request
* messag is sent by the host to delete an NCE after it is no
* longer required.
* @VXGE_HAL_MSG_TYPE_NCE_DELETE_RESP:The NCE Delete Response
* message is sent in response to the NCE Delete Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_REQ:The NCE Update MAC Request
* message is used by the host to modify the MAC address for
* an NCE on the adapter.
* @VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_RESP:The NCE Update MAC Response
* message is sent in response to the NCE Update MAC Request
* message from the host to indicate the status of the
* operation.
* @VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_REQ:The NCE Update Rch Time
* Request message is used by the host to update the
* Reachability time for an NCE on the adapter.
* @VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_RESP:The NCE Update
* Rch Time Response message is sent in response to the NCE
* Update Rch Time Request message from the host to indicate
* the status of updating the reachability time for the NCE.
* @VXGE_HAL_MSG_TYPE_NCE_QUERY_REQ:The NCE Query Request message
* is used by the host to query an NCE on the adapter.
* @VXGE_HAL_MSG_TYPE_NCE_QUERY_RESP:The NCE Query Response
* message is sent in response to the NCE Query Request message
* from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_NCE_RCH_TIME_EXCEEDED:This is an unsolicited message
* sent to the host by the adapter when the NCE Reach Time has
* been exceeded.
* @VXGE_HAL_MSG_TYPE_CQRQ_CREATE_REQ:The CQRQ Create Request
* message is used by the host to create a CQRQ on the adapter.
* @VXGE_HAL_MSG_TYPE_CQRQ_CREATE_RESP:The CQRQ Create Response
* message is sent in response to the CQRQ Create Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_CQRQ_DELETE_REQ:The CQRQ Delete Request
* message is used by the host to destroy a CQRQ on the adapter.
* @VXGE_HAL_MSG_TYPE_CQRQ_DELETE_RESP:The CQRQ Delete Response
* message is sent in response to the CQRQ Delete Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_REQ:The CQRQ Modify Request
* message is used by the host to modify fields for an
* CQRQ on the adapter. The adapter will make the following
* checks
* - The CQRQ ID is valid
* All other checks must be performed by the host software.
* @VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_RESP:The CQRQ Modify Response
* message is sent in response to the CQRQ Modify Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_CQRQ_QUERY_REQ:The CQRQ Query Request
* message is used by the host to query the properties of a CQRQ
* on the adapter
* @VXGE_HAL_MSG_TYPE_CQRQ_QUERY_RESP:The CQRQ Query Response
* message is sent in response to the CQRQ Query Request
* message from the host to indicate the status of the operation
* and return any CQRQ properties to the host.
* @VXGE_HAL_MSG_TYPE_CQRQ_ARM_REQ:The CQRQ Arm Request message
* is used by the host to change the armed state of a CQRQ on the
* adapter. The armed state determines how the adapter will
* interrupt the host when RDMA messages arrive.
* @VXGE_HAL_MSG_TYPE_CQRQ_ARM_RESP:The CQRQ Arm Response message
* is sent in response to the CQRQ Arm Request message from the
* host to indicate the status of arming the CQRQ
* @VXGE_HAL_MSG_TYPE_CQRQ_EVENT_NOTIF:The CQRQ Event Notification
* message is sent to host when the adapter encounters a
* problem when DMAing CQEs from host memory. There are three
* conditions, EOL, Low Threshold, Drained
* @VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_REQ:The CQRQ
* First CQE BW Notification Request message is used by the
* host to notify the adapter after it has configured the first
* CQE block wrapper(s). It is required to pass the host address
* and number of bytes of the first CQE block wrapper in host
* memory.
* @VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_RESP:The CQRQ
* First CQE BW Notification Response message is sent in
* response to the CQRQ First CQE BW Notification Request
* message from the host to acknowledge the notification from
* host and return the status of updating the CQRQ record with
* the address and bytes of the first CQE block wrapper.
* @VXGE_HAL_MSG_TYPE_SRQ_CREATE_REQ:The SRQ Create Request
* message is used by the host to create an SRQ on the adapter.
* @VXGE_HAL_MSG_TYPE_SRQ_CREATE_RESP:The SRQ Create Response
* message is sent in response to the SRQ Create Request
* message from the host to indicate the status of the operation
* and return the SRQ ID to the host.
* @VXGE_HAL_MSG_TYPE_SRQ_DELETE_REQ:The SRQ Delete Request
* message is used by the host to delete an SRQ on the adapter.
* @VXGE_HAL_MSG_TYPE_SRQ_DELETE_RESP:The SRQ Delete Response
* message is sent in response to the SRQ Delete Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_SRQ_MODIFY_REQ:The SRQ Modify Request
* message is used by the host to modify an SRQ on the adapter.
* The host must send down all the fields to modify. To simplify
* the adapter firmware there will be no mask to modify individual
* fields.
* @VXGE_HAL_MSG_TYPE_SRQ_MODIFY_RESP:The SRQ Modify Response
* message is sent in response to the SRQ Modify Request
* message from the host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_SRQ_QUERY_REQ:The SRQ Query Request message
* is used by the host to query the properties of an SRQ on the
* adapter.
* @VXGE_HAL_MSG_TYPE_SRQ_QUERY_RESP:The SRQ Query Response
* message is sent in response to the SRQ Query Request message
* from the host to indicate the status of the operation and
* return any SRQ properties to the host
* @VXGE_HAL_MSG_TYPE_SRQ_ARM_REQ:The SRQ Arm Request message is
* sent to the adapter to arm or re-arm the SRQ limit.
* @VXGE_HAL_MSG_TYPE_SRQ_ARM_RESP:The SRQ Arm Response is sent
* to the host to acknowledge the SRQ Arm Request and indicate
* the status of arming or re-arming the SRQ limit.
* @VXGE_HAL_MSG_TYPE_SRQ_EVENT_NOTIF:The SRQ Event Notification
* iMSG is used to alert the host that the adapter has encountered
* one of the following conditions when DMAing WQEs from host
* memory - EOL (End of list of WQEs in host memory),Low Threshold
* (The adapter is running low on available WQEs),Drained (Adapter
* out of WQEs because of EOL condition or adapter use faster than
* DMA), SRQ Limit (The number of available WQEs on adapter + host
* less than SRQ limit and the SRQ limit is armed).
* @VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_REQ:The SRQ First
* WQE BW Notification Request is used to alert the adapter of
* the location of the first WQE block wrapper after initially
* creating the SRQ. It is required because the host cannot
* pre-post WQEs when creating the SRQ.
* @VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_RESP:The SRQ First
* WQE BW Notification Response message is sent in response to
* the SRQ First WQE BW Notification Request message from the
* host to indicate the status of the operation.
* @VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_REQ:The SRQ
* WQE Blocks Added Notification Request is used to alert the
* adapter that new WQEs have been posted in host memory. This is
* required in order for the adapter to support the concept of SRQ
* limit.
* @VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_RESP:The SRQ
* WQE Blocks Added Notification Response is sent by the adapter
* in response to the SRQ WQE Blocks Added Notification Request
* to acknowledge the notification from the host and to return any
* status in the event a problem occurred.
* @VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_REQ:The SRQ Return WQEs
* Request message may be sent by the host to reclaim unused
* WQEs from the head of the WQE block wrapper list. Its purpose
* is to reclaim over-provisioned WQEs for an SRQ. The host may
* choose to reclaim WQEs from an SRQ at any time.
* @VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_RESP:The SRQ Return WQEs
* is sent in reply to the SRQ Return WQEs Request message
* to reclaim unused WQEs from an over-provisioned SRQ.
* @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_REQ:This downward message
* commands the adapter to create a new non-shared memory region
* (NSMR) in the invalid state. This message is used to implement
* the Allocate Non-Shared Memory Region memory management verb.
* @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG Allocate NSMR Request message
* @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_REQ:This downward message
* commands the adapter to allocate a new memory window (MW).
* This message is used to implement the Allocate Memory Window
* memory management verb.
* @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG Allocate MW Request message.
* @VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_REQ:This downward message
* commands the adapter to deallocate the specified STag, freeing
* up any on-adapter resources
* @VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG De-allocate Request message.
* @VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_REQ:This downward message
* commands the adapter to register a non-shared memory region.
* This message is used to implement Register NSMR memory
* management verb Fast registration cannot be performed with
* this . It can only be done via the PostSQ TOWI.
* @VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG Register NSMR Request message.
* @VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_REQ:This downward
* message commands the adapter to change the memory registration
* of an existing NSMR to create a new NSMR in the valid state.
* This message is used to implement the Reregister Non-Shared
* Memory Region memory management verb.
* @VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG Re-register NSMR Request message
* @VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_REQ:This downward message
* commands the adapter to create a shared memory region (SMR)
* based on an existing memory region, either shared(SMR) or
* non-shared(NSMR). This message is used to implement the
* Register Shared Memory Region verb.
* @VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_RESP:This upward message
* communicates to the host the success or failure of the
* corresponding STAG Re-register NSMR Request message.
* @VXGE_HAL_MSG_TYPE_STAG_QUERY_REQ:This downward message commands
* the adapter to return the specifics of the specified STag.
* This message is used to implement the Query Memory Region
* memory management verb and the Query Memory Window memory
* management verb. Memory region and memory window querying
* could be handled entirely by the host software without any
* adapter involvement. The STAG Query Request and STAG
* Query Response messages allow the host to implement
* adapter-based STag querying.
* @VXGE_HAL_MSG_TYPE_STAG_QUERY_RESP:This upward message
* communicates to the host the specifics of the queried STag.
* The response message does not return the underlying the PBL.
* @VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_REQ:This message
* commands the adapter to transition an invalid STag to the
* valid state without changing any of its other attributes.
* The Validate-STag-/Validate-STag-Response- messages
* allow a Neterion-proprietary ability to revalidate an invalid
* STag without changing any of its attributes or its PBL. This
* is expected to be useful in situations where an STag is
* invalidated and then revalidated with the same attributes
* including PBL. Using this message, rather than the more
* general Reregister NSMR, saves the overhead of transferring
* the PBL to the adapter.
* @VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_RESP:This upward message
* communicates to the host the success of failure of the
* corresponding STAG Validate Local Tag Request message.
* @VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_REQ: The STAG
* Invalidate Local Tag Request message is used by the host to
* invalidate a local STAG. This message provides an alternative
* route for the normal TOWI based STAG Invalidation. It allows a
* kernel mode process to invalidate an STAG without writing
* a TOWI.
* @VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_RESP: This upward
* message communicates to the host the success or failure of the
* corresponding STAG Invalidate Local Tag Request message.
* @VXGE_HAL_MSG_TYPE_STAG_BIND_MW_REQ: This downward message commands
* the adapter to bind an existing (invalid) MW to an existing
* (valid) MR. This message provides an alternative to the TOWI
* based implementation allowing the path be used for MW binding
* @VXGE_HAL_MSG_TYPE_STAG_BIND_MW_RESP: This upward message
* communicates to the host the success or failure of the
* corresponding STAG Bind MW Request message.
* @VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_REQ: The STAG Fast
* Register NSMR Request provides an alternative way to fast
* register an NSMR instead of going to the TOWI path.
* @VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_RESP: The STag Fast
* Register NSMR Response message is sent to the host from
* the adapter in response to the original message. It
* indicates the status of fast registering the NSMR.
* @VXGE_HAL_MSG_TYPE_TCP_OPEN_REQ:The TCP Open Request message
* is sent by the host to open a TCP connection on the adapter.
* @VXGE_HAL_MSG_TYPE_TCP_OPEN_RESP:The TCP Open Response message
* is sent in response to a TCP Open Request message to indicate
* that the TCP session has been opened
* @VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_REQ:The TCP Promote to
* iWARP Request message is sent from the host to the adapter
* in order to migrate an existing bytestream session to iWARP
* mode.
* @VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_RESP:The TCP Promote to
* iWARP Response message is sent to the host to indicate the
* status of promoting an existing bytestream session to iWARP
* mode.
* @VXGE_HAL_MSG_TYPE_TCP_MODIFY_REQ:The TCP Modify Request message
* is sent by the host to modify the attributes associated with a
* bytestream or iWARP session.
* @VXGE_HAL_MSG_TYPE_TCP_MODIFY_RESP:The TCP Modify Response message
* is sent to the host in response to a TCP Modify Request message
* to indicate the status of changing the attributes associated
* with the bytestream or iWARP session.
* @VXGE_HAL_MSG_TYPE_TCP_DELETE_REQ:The TCP Delete Request
* message is sent by the host to delete a bytestream TCP session
* on the adapter.
* @VXGE_HAL_MSG_TYPE_TCP_DELETE_RESP:The TCP Delete Response
* message is sent in response to a TCP Delete Request message
* to indicate that the TCP session has been deleted.
* @VXGE_HAL_MSG_TYPE_TCP_ABORT_REQ: The TCP Abort Request message
* is used to abort a bytestream or iWARP session.
* @VXGE_HAL_MSG_TYPE_TCP_ABORT_RESP: The TCP Abort Response
* message is sent to the host from the adapter after aborting the
* bytestream or iWARP session.
* @VXGE_HAL_MSG_TYPE_TCP_ESTABLISHED: The TCP Established message is
* an un-solicited event sent from the adapter to the host when
* the SYN+ACK segment arrives (active opener) or the ACK segment
* (passive opener) arrives at the adapter.
* @VXGE_HAL_MSG_TYPE_TCP_FIN_RECEIVED: The TCP FIN Received message
* is an un-solicited event sent from the adapter to the host on
* session teardown. It indicates that the FIN segment has been
* received from the remote end and the session is now in TIME
* WAIT state.
* @VXGE_HAL_MSG_TYPE_TCP_TIME_WAIT_DONE: The TCP Time Wait Done message
* is sent from the adapter to the host to indicate when the TCP
* session leaves the TIME WAIT state.
* @VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN: This message is used for receive
* window updates, both for rx window flow control updates(updates
* to rcv_buf as data is consumed by the application on the host)
* and for maximum receive window size updates (when the receive
* buffer size changes on the host)
* @VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS: This is sent by the host to the
* adapter to update the MSS for the session.
* @VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER: The TCP Update IP Header
* is used to update the IP TOS and IP flow label in the IP header
* @VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE: The TCP Update Keepalive
* message is sent from the host to the adapter to update the
* keep-alive timer for the session.
* @VXGE_HAL_MSG_TYPE_TCP_UPDATE_FAILURE: The TCP Update Failure
* message is sent to the host from the adapter in the event that
* one of the TCP update messages failed for the session. Normally
* these messages do not require a reply and therefore there is no
* response from the adapter. The TCP Update messages include:
* VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN
* VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS
* VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER
* VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE
* @VXGE_HAL_MSG_TYPE_TCP_FIN_ACK_RECEIVED:The TCP FIN ACK Received
* message is an unsolicited message sent to the host from the
* adapter on received of the ACK segment acknowledging that the
* remote end has received the FIN. It is required for Sun's KPI
* interface.
* @VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_REQ:The TCP Relink to NCE
* Request would be used to change the NCE entry associated
* with a particular bytestream or iWARP session. This message
* could be used to change the NCE of a group of sessions if a
* particular path went down and need to be replaced by a new path
* The host is responsible for tracking the mapping of sessions to
* NCEs so that when de-allocating an NCE it does not de-allocate
* on that is still in use by a particular session.
* @VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_RESP:This message is sent in
* response to the TCP Relink to NCE Request to indicate the
* status of re-linking the TCP session to a particular NCE.
* @VXGE_HAL_MSG_TYPE_TCP_QP_LIMIT_EXCEEDED:The TCP QP Limit Exceeded
* Notification message is sent to the host when an iWARP
* session has reached its QP Limit and the QP limit was armed.
* @VXGE_HAL_MSG_TYPE_TCP_RDMA_TERMINATE_RECEIVED:The TCP RDMA Terminate
* Received message is an un-solicited event sent from the
* adapter to the host when an RDMA terminate message has been
* received from the remote end.
* @VXGE_HAL_MSG_TYPE_LRO_OPEN_REQ:The LRO Open Request message
* is sent by the host to open an LRO connection on the adapter.
* There is no PE context for an LRO session. The PE is involved
* for timer purposes and transferring messages to the RPE but it
* contains no session context.
* @VXGE_HAL_MSG_TYPE_LRO_OPEN_RESP:The LRO Open Response message
* is sent in response to a LRO Open Request message to
* indicate that the LRO session has been opened.
* @VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_REQ:The LRO End
* Classification Request is sent by the host before the LRO
* Delete Request to tell the adapter to stop steering Rx
* frames from that session into the LRO path. The host would
* later call LRO Delete Request . Separating these two calls
* allows enough time to pass so that frames already in the FB can
* be drained out, thereby avoiding the need for frame reversion.
* @VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_RESP:The LRO End
* Classification Response message is sent in response to a
* LRO End Classification Request message to indicate that
* classification has been stopped for the LRO session and the
* host can proceed with deleting the LRO session.
* @VXGE_HAL_MSG_TYPE_LRO_DELETE_REQ:The LRO Delete Request
* message is sent by the host to delete a LRO session on the
* adapter.It might be possible in the future to replace this
* message and the TCP Delete Request with a single common
* message since there doesn't seem to be any difference between
* the two anymore.
* @VXGE_HAL_MSG_TYPE_LRO_DELETE_RESP:The LRO Delete Response
* message is sent in response to a LRO Delete Request message
* to indicate that the LRO session has been deleted.
* @VXGE_HAL_MSG_TYPE_LRO_SESSION_CANDIDATE_NOTIF:This msg
* indicates to the host that the adapter's autoLRO feature has
* identified a candidate LRO session. No response from the host
* is required. (If the host did decide to act on this information
* from the adapter, the host would use the usual LRO Open Request
* ).
* @VXGE_HAL_MSG_TYPE_SPDM_OPEN_REQ:The SPDM Open Request message
* is sent by the host to open an SPDM connection on the adapter.
* There is no RPE or PE context for an SPDM session. The ONE is
* not involved in this type of classification.
* @VXGE_HAL_MSG_TYPE_SPDM_OPEN_RESP:The SPDM Open Response
* message is sent in response to a SPDM Open Request message
* to indicate the status of creating the SPDM session.
* @VXGE_HAL_MSG_TYPE_SPDM_DELETE_REQ:The SPDM Delete Request
* message is sent by the host to delete an SPDM session on the
* adapter. It might be possible in the future to replace this
* message and the LRO/TCP Delete Request with a single common
* message since there doesn't seem to be any difference between
* the two anymore.
* @VXGE_HAL_MSG_TYPE_SPDM_DELETE_RESP:The SPDM Delete Response
* message is sent in response to a SPDM Delete Request message
* to indicate that the SPDM session has been deleted.
* @VXGE_HAL_MSG_TYPE_SESSION_EVENT_NOTIF:The Session Event
* Notification message is an unsolicited message from the
* adapter used to inform the host about an unexpected condition
* on a bytestream or iWARP session.
* @VXGE_HAL_MSG_TYPE_SESSION_QUERY_REQ:The Session Query Request
* message is sent by the host to query the attributes of an
* existing offloaded session. This message may be used to query
* the attributes of an SPDM, LRO, bytestream or iWARP session.
* Initially this will be a single message used for all purposes.
* In the future this may be split up into multiple messages
* allowing the user to query the pecific context for an SPDM,
* LRO, iWARP, or bytestream session.
* @VXGE_HAL_MSG_TYPE_SESSION_QUERY_RESP:The Session Query Response
* message is sent in response to a Session Query Request
* message to return the attributes associated with the specified
* session
* @VXGE_HAL_MSG_TYPE_SESSION_RETURN_IN_PROG_WQES: This message is
* generated by the adapter during deletion of a session to return
* any WQEs that may be in the in-progress list for the session.If
* a WQE is in the in-progress list it is owned by the session and
* cannot be returned to the head of WQE list for an SRQ because
* of ordering issues. Therefore, it must be returned to the host
* at which point the host may choose to destroy the resource or
* simply re-post the WQE for re-use.
* @VXGE_HAL_MSG_TYPE_SESSION_FRAME_WRITE:The Frame Write message is
* generated by the adapter in order to send certain frames to the
* host via the path instead of the normal path. Frames will be
* sent to the host under the following conditions:
* 1) mis-aligned frames that the adapter cannot place
* 2) during debugging to look at the contents of the frame
* In addition to this,a RDMA terminate message will also be sent
* via a message but in this case it will be sent in a TCP RDMA
* Terminate Received message. Frames arriving in the will
* not have markers stripped. Instead the host will be responsible
* for stripping markers and taking appropriate action on the
* received frame.
* @VXGE_HAL_MSG_TYPE_SQ_CREATE_REQ: This is HAL private message for.
* SQ create. Never used.
* @VXGE_HAL_MSG_TYPE_SQ_CREATE_RESP: This is HAL private message
* for SQ create response. This is reported to clients by HAL.
* @VXGE_HAL_MSG_TYPE_SQ_DELETE_REQ: This is HAL private message for.
* SQ delete. Never used.
* @VXGE_HAL_MSG_TYPE_SQ_DELETE_RESP:This is HAL private message
* for SQ delete response. This is reported to clients by HAL.
*
* Message types supported by the adapter and HAL Private messages.
*/
typedef enum vxge_hal_message_type_e {
VXGE_HAL_MSG_TYPE_NCE_CREATE_REQ = 1,
VXGE_HAL_MSG_TYPE_NCE_CREATE_RESP = 2,
VXGE_HAL_MSG_TYPE_NCE_DELETE_REQ = 3,
VXGE_HAL_MSG_TYPE_NCE_DELETE_RESP = 4,
VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_REQ = 5,
VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_RESP = 6,
VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_REQ = 7,
VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_RESP = 8,
VXGE_HAL_MSG_TYPE_NCE_QUERY_REQ = 9,
VXGE_HAL_MSG_TYPE_NCE_QUERY_RESP = 10,
VXGE_HAL_MSG_TYPE_NCE_RCH_TIME_EXCEEDED = 86,
VXGE_HAL_MSG_TYPE_CQRQ_CREATE_REQ = 11,
VXGE_HAL_MSG_TYPE_CQRQ_CREATE_RESP = 12,
VXGE_HAL_MSG_TYPE_CQRQ_DELETE_REQ = 13,
VXGE_HAL_MSG_TYPE_CQRQ_DELETE_RESP = 14,
VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_REQ = 16,
VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_RESP = 17,
VXGE_HAL_MSG_TYPE_CQRQ_QUERY_REQ = 18,
VXGE_HAL_MSG_TYPE_CQRQ_QUERY_RESP = 19,
VXGE_HAL_MSG_TYPE_CQRQ_ARM_REQ = 20,
VXGE_HAL_MSG_TYPE_CQRQ_ARM_RESP = 21,
VXGE_HAL_MSG_TYPE_CQRQ_EVENT_NOTIF = 22,
VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_REQ = 23,
VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_RESP = 24,
VXGE_HAL_MSG_TYPE_SRQ_CREATE_REQ = 27,
VXGE_HAL_MSG_TYPE_SRQ_CREATE_RESP = 28,
VXGE_HAL_MSG_TYPE_SRQ_DELETE_REQ = 29,
VXGE_HAL_MSG_TYPE_SRQ_DELETE_RESP = 30,
VXGE_HAL_MSG_TYPE_SRQ_MODIFY_REQ = 31,
VXGE_HAL_MSG_TYPE_SRQ_MODIFY_RESP = 32,
VXGE_HAL_MSG_TYPE_SRQ_QUERY_REQ = 33,
VXGE_HAL_MSG_TYPE_SRQ_QUERY_RESP = 34,
VXGE_HAL_MSG_TYPE_SRQ_ARM_REQ = 35,
VXGE_HAL_MSG_TYPE_SRQ_ARM_RESP = 36,
VXGE_HAL_MSG_TYPE_SRQ_EVENT_NOTIF = 37,
VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_REQ = 38,
VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_RESP = 39,
VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_REQ = 40,
VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_RESP = 41,
VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_REQ = 96,
VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_RESP = 42,
VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_REQ = 43,
VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_RESP = 44,
VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_REQ = 45,
VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_RESP = 46,
VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_REQ = 47,
VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_RESP = 48,
VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_REQ = 49,
VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_RESP = 50,
VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_REQ = 51,
VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_RESP = 52,
VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_REQ = 53,
VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_RESP = 54,
VXGE_HAL_MSG_TYPE_STAG_QUERY_REQ = 55,
VXGE_HAL_MSG_TYPE_STAG_QUERY_RESP = 56,
VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_REQ = 57,
VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_RESP = 58,
VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_REQ = 87,
VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_RESP = 88,
VXGE_HAL_MSG_TYPE_STAG_BIND_MW_REQ = 89,
VXGE_HAL_MSG_TYPE_STAG_BIND_MW_RESP = 90,
VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_REQ = 91,
VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_RESP = 92,
VXGE_HAL_MSG_TYPE_TCP_OPEN_REQ = 59,
VXGE_HAL_MSG_TYPE_TCP_OPEN_RESP = 60,
VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_REQ = 61,
VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_RESP = 62,
VXGE_HAL_MSG_TYPE_TCP_MODIFY_REQ = 98,
VXGE_HAL_MSG_TYPE_TCP_MODIFY_RESP = 99,
VXGE_HAL_MSG_TYPE_TCP_DELETE_REQ = 63,
VXGE_HAL_MSG_TYPE_TCP_DELETE_RESP = 64,
VXGE_HAL_MSG_TYPE_TCP_ABORT_REQ = 65,
VXGE_HAL_MSG_TYPE_TCP_ABORT_RESP = 66,
VXGE_HAL_MSG_TYPE_TCP_ESTABLISHED = 78,
VXGE_HAL_MSG_TYPE_TCP_FIN_RECEIVED = 79,
VXGE_HAL_MSG_TYPE_TCP_TIME_WAIT_DONE = 80,
VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN = 81,
VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS = 82,
VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER = 83,
VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE = 84,
VXGE_HAL_MSG_TYPE_TCP_UPDATE_FAILURE = 85,
VXGE_HAL_MSG_TYPE_TCP_FIN_ACK_RECEIVED = 87,
VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_REQ = 88,
VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_RESP = 89,
VXGE_HAL_MSG_TYPE_TCP_QP_LIMIT_EXCEEDED = 100,
VXGE_HAL_MSG_TYPE_TCP_RDMA_TERMINATE_RECEIVED = 101,
VXGE_HAL_MSG_TYPE_LRO_OPEN_REQ = 67,
VXGE_HAL_MSG_TYPE_LRO_OPEN_RESP = 68,
VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_REQ = 69,
VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_RESP = 70,
VXGE_HAL_MSG_TYPE_LRO_DELETE_REQ = 71,
VXGE_HAL_MSG_TYPE_LRO_DELETE_RESP = 72,
VXGE_HAL_MSG_TYPE_LRO_SESSION_CANDIDATE_NOTIF = 73,
VXGE_HAL_MSG_TYPE_SPDM_OPEN_REQ = 74,
VXGE_HAL_MSG_TYPE_SPDM_OPEN_RESP = 75,
VXGE_HAL_MSG_TYPE_SPDM_DELETE_REQ = 76,
VXGE_HAL_MSG_TYPE_SPDM_DELETE_RESP = 77,
VXGE_HAL_MSG_TYPE_SESSION_EVENT_NOTIF = 102,
VXGE_HAL_MSG_TYPE_SESSION_QUERY_REQ = 103,
VXGE_HAL_MSG_TYPE_SESSION_QUERY_RESP = 104,
VXGE_HAL_MSG_TYPE_SESSION_RETURN_IN_PROG_WQES = 97,
VXGE_HAL_MSG_TYPE_SESSION_FRAME_WRITE = 105,
/* The following are private for HAL */
VXGE_HAL_MSG_TYPE_SQ_CREATE_REQ = 65537,
VXGE_HAL_MSG_TYPE_SQ_CREATE_RESP = 65538,
VXGE_HAL_MSG_TYPE_SQ_DELETE_REQ = 65539,
VXGE_HAL_MSG_TYPE_SQ_DELETE_RESP = 65540
} vxge_hal_message_type_e;
/*
* struct vxge_hal_opaque_handle_t - Opaque handle used by the hal and clients
* to save their contexts
* @vpath_handle: Virtual path handle
* @hal_priv: Private data which HAL assigns
* @client_priv: Client assigned private data
*
* This structure is used to store the client and hal data and pass as
* opaque handle in the messages.
*/
typedef struct vxge_hal_opaque_handle_t {
vxge_hal_vpath_h vpath_handle;
#define VXGE_HAL_OPAQUE_HANDLE_GET_VPATH_HANDLE(op) ((op)->vpath_handle)
#define VXGE_HAL_OPAQUE_HANDLE_VPATH_HANDLE(op, vrh) (op)->vpath_handle = vrh
u64 hal_priv;
#define VXGE_HAL_OPAQUE_HANDLE_GET_HAL_PRIV(op) ((op)->hal_priv)
#define VXGE_HAL_OPAQUE_HANDLE_HAL_PRIV(op, priv) (op)->hal_priv = (u64)priv
u64 client_priv;
#define VXGE_HAL_OPAQUE_HANDLE_GET_CLIENT_PRIV(op) ((op)->client_priv)
#define VXGE_HAL_OPAQUE_HANDLE_CLIENT_PRIV(op, priv) \
(op)->client_priv = (u64)priv
} vxge_hal_opaque_handle_t;
/*
* vxge_hal_vpath_callback_f - Callback to receive up messages.
* @client_handle: handle passed by client in attach or open function
* @msgh: Message handle.
* @msg_type: Type of message
* @obj_id: Object Id of object to which message belongs
* @result: Result code
* @opaque_handle: Opaque handle passed when the request was made.
*
* Callback function registered when opening vpath to receive the messages
* This callback function passed to vxge_hal_vpath_open and
* vxge_hal_vpath_attach routine to get replys to all asynchronous functions.
* The format of the reply is a message along with the parameters that are
* common fro all replys. The message handle passed to this callback is
* opaque for the iWARP/RDMA module and the information from the message can
* be got by calling appropriate get function depending on the message type
* passed as one of the parameter to the callback. The message types that
* are to be passed to the callback are the ones that are responses and
* notifications
*/
typedef vxge_hal_status_e(*vxge_hal_vpath_callback_f) (
vxge_hal_client_h client_handle,
vxge_hal_up_msg_h msgh,
vxge_hal_message_type_e msg_type,
vxge_hal_obj_id_t obj_id,
vxge_hal_status_e result,
vxge_hal_opaque_handle_t *opaque_handle);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_TYPES_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_VERSION_H
#define VXGE_HAL_VERSION_H
#include <dev/vxge/include/build-version.h>
/*
* VXGE_HAL_VERSION_MAJOR - HAL major version
*/
#define VXGE_HAL_VERSION_MAJOR 0
/*
* VXGE_HAL_VERSION_MINOR - HAL minor version
*/
#define VXGE_HAL_VERSION_MINOR 0
/*
* VXGE_HAL_VERSION_FIX - HAL version fix
*/
#define VXGE_HAL_VERSION_FIX 0
/*
* VXGE_HAL_VERSION_BUILD - HAL build version
*/
#define VXGE_HAL_VERSION_BUILD GENERATED_BUILD_VERSION
/*
* VXGE_HAL_VERSION - HAL version
*/
#define VXGE_HAL_VERSION "VXGE_HAL_VERSION_MAJOR.VXGE_HAL_VERSION_MINOR.\
VXGE_HAL_VERSION_FIX.VXGE_HAL_VERSION_BUILD"
/*
* VXGE_HAL_DESC - HAL Description
*/
#define VXGE_HAL_DESC VXGE_DRIVER_NAME" v."VXGE_HAL_VERSION
/* Link Layer versioning */
#include <dev/vxge/vxgell-version.h>
#endif /* VXGE_HAL_VERSION_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
/* LINTLIBRARY */
#ifndef _VXGE_OSDEP_H_
#define _VXGE_OSDEP_H_
#include <sys/param.h>
#include <sys/systm.h>
#if __FreeBSD_version >= 800000
#include <sys/buf_ring.h>
#endif
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/sockio.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/rman.h>
#include <sys/stddef.h>
#include <sys/proc.h>
#include <sys/endian.h>
#include <sys/sysctl.h>
#include <sys/pcpu.h>
#include <sys/smp.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/bpf.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <net/if_var.h>
#include <net/if_vlan_var.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <netinet/ip.h>
#include <netinet/ip6.h>
#include <netinet/tcp.h>
#include <netinet/tcp_lro.h>
#include <netinet/udp.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/clock.h>
#include <machine/stdarg.h>
#include <machine/in_cksum.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pci_private.h>
#include <dev/vxge/include/vxge-defs.h>
/*
* ------------------------- includes and defines -------------------------
*/
#if BYTE_ORDER == BIG_ENDIAN
#define VXGE_OS_HOST_BIG_ENDIAN
#else
#define VXGE_OS_HOST_LITTLE_ENDIAN
#endif
#if __LONG_BIT == 64
#define VXGE_OS_PLATFORM_64BIT
#else
#define VXGE_OS_PLATFORM_32BIT
#endif
#define VXGE_OS_PCI_CONFIG_SIZE 256
#define VXGE_OS_HOST_PAGE_SIZE 4096
#define VXGE_LL_IP_FAST_CSUM(hdr, len) 0
#ifndef __DECONST
#define __DECONST(type, var) ((type)(uintrptr_t)(const void *)(var))
#endif
typedef struct ifnet *ifnet_t;
typedef struct mbuf *mbuf_t;
typedef struct mbuf *OS_NETSTACK_BUF;
typedef struct _vxge_bus_res_t {
u_long bus_res_len;
bus_space_tag_t bus_space_tag; /* DMA Tag */
bus_space_handle_t bus_space_handle; /* Bus handle */
struct resource *bar_start_addr; /* BAR address */
} vxge_bus_res_t;
typedef struct _vxge_dma_alloc_t {
bus_addr_t dma_paddr; /* Physical Address */
caddr_t dma_vaddr; /* Virtual Address */
bus_dma_tag_t dma_tag; /* DMA Tag */
bus_dmamap_t dma_map; /* DMA Map */
bus_dma_segment_t dma_segment; /* DMA Segment */
bus_size_t dma_size; /* Size */
int dma_nseg; /* scatter-gather */
} vxge_dma_alloc_t;
typedef struct _vxge_pci_info {
device_t ndev; /* Device */
void *reg_map[3]; /* BAR Resource */
struct resource *bar_info[3]; /* BAR tag and handle */
} vxge_pci_info_t;
/*
* ---------------------- fixed size primitive types -----------------------
*/
typedef size_t ptr_t;
typedef int8_t s8;
typedef uint8_t u8;
typedef uint16_t u16;
typedef int32_t s32;
typedef uint32_t u32;
typedef unsigned long long int u64;
typedef boolean_t bool;
typedef bus_addr_t dma_addr_t;
typedef struct mtx spinlock_t;
typedef struct resource *pci_irq_h;
typedef vxge_pci_info_t *pci_dev_h;
typedef vxge_pci_info_t *pci_cfg_h;
typedef vxge_bus_res_t *pci_reg_h;
typedef vxge_dma_alloc_t pci_dma_h;
typedef vxge_dma_alloc_t pci_dma_acc_h;
/*
* -------------------------- "libc" functionality -------------------------
*/
#define vxge_os_curr_time systime
#define vxge_os_strcpy strcpy
#define vxge_os_strlcpy strlcpy
#define vxge_os_strlen strlen
#define vxge_os_sprintf sprintf
#define vxge_os_snprintf snprintf
#define vxge_os_println(buf) printf("%s\n", buf)
#define vxge_os_memzero bzero
#define vxge_os_memcmp memcmp
#define vxge_os_memcpy(dst, src, size) bcopy(src, dst, size)
#define vxge_os_timestamp(buff) { \
struct timeval cur_time; \
gettimeofday(&cur_time, 0); \
snprintf(buff, sizeof(buff), "%08li.%08li: ", \
cur_time.tv_sec, cur_time.tv_usec); \
}
#define vxge_os_printf(fmt...) { \
printf(fmt); \
printf("\n"); \
}
#define vxge_os_vaprintf(fmt...) \
vxge_os_printf(fmt);
#define vxge_os_vasprintf(fmt...) { \
vxge_os_printf(fmt); \
}
#define vxge_trace(trace, fmt, args...) \
vxge_debug_uld(VXGE_COMPONENT_ULD, \
trace, hldev, vpid, fmt, ## args)
/*
* -------------------- synchronization primitives -------------------------
*/
/* Initialize the spin lock */
#define vxge_os_spin_lock_init(lockp, ctxh) { \
if (mtx_initialized(lockp) == 0) \
mtx_init((lockp), "vxge", NULL, MTX_DEF); \
}
/* Initialize the spin lock (IRQ version) */
#define vxge_os_spin_lock_init_irq(lockp, ctxh) { \
if (mtx_initialized(lockp) == 0) \
mtx_init((lockp), "vxge", NULL, MTX_DEF); \
}
/* Destroy the lock */
#define vxge_os_spin_lock_destroy(lockp, ctxh) { \
if (mtx_initialized(lockp) != 0) \
mtx_destroy(lockp); \
}
/* Destroy the lock (IRQ version) */
#define vxge_os_spin_lock_destroy_irq(lockp, ctxh) { \
if (mtx_initialized(lockp) != 0) \
mtx_destroy(lockp); \
}
/* Acquire the lock */
#define vxge_os_spin_lock(lockp) { \
if (mtx_owned(lockp) == 0) \
mtx_lock(lockp); \
}
/* Release the lock */
#define vxge_os_spin_unlock(lockp) mtx_unlock(lockp)
/* Acquire the lock (IRQ version) */
#define vxge_os_spin_lock_irq(lockp, flags) { \
flags = MTX_QUIET; \
if (mtx_owned(lockp) == 0) \
mtx_lock_flags(lockp, flags); \
}
/* Release the lock (IRQ version) */
#define vxge_os_spin_unlock_irq(lockp, flags) { \
flags = MTX_QUIET; \
mtx_unlock_flags(lockp, flags); \
}
/* Write memory barrier */
#if __FreeBSD_version < 800000
#if defined(__i386__) || defined(__amd64__)
#define mb() __asm volatile("mfence" ::: "memory")
#define wmb() __asm volatile("sfence" ::: "memory")
#define rmb() __asm volatile("lfence" ::: "memory")
#else
#define mb()
#define rmb()
#define wmb()
#endif
#endif
#define vxge_os_wmb() wmb()
#define vxge_os_udelay(x) DELAY(x)
#define vxge_os_stall(x) DELAY(x)
#define vxge_os_mdelay(x) DELAY(x * 1000)
#define vxge_os_xchg (targetp, newval)
/*
* ------------------------- misc primitives -------------------------------
*/
#define vxge_os_be32 u32
#define vxge_os_unlikely(x) (x)
#define vxge_os_prefetch(x) (x = x)
#define vxge_os_prefetchw(x) (x = x)
#define vxge_os_bug vxge_os_printf
#define vxge_os_ntohs ntohs
#define vxge_os_ntohl ntohl
#define vxge_os_ntohll be64toh
#define vxge_os_htons htons
#define vxge_os_htonl htonl
#define vxge_os_htonll htobe64
#define vxge_os_in_multicast IN_MULTICAST
#define VXGE_OS_INADDR_BROADCAST INADDR_BROADCAST
/*
* -------------------------- compiler stuff ------------------------------
*/
#define __vxge_os_cacheline_size CACHE_LINE_SIZE
#define __vxge_os_attr_cacheline_aligned __aligned(__vxge_os_cacheline_size)
/*
* ---------------------- memory primitives --------------------------------
*/
#if defined(VXGE_OS_MEMORY_CHECK)
typedef struct _vxge_os_malloc_t {
u_long line;
u_long size;
void *ptr;
const char *file;
} vxge_os_malloc_t;
#define VXGE_OS_MALLOC_CNT_MAX 64*1024
extern u32 g_malloc_cnt;
extern vxge_os_malloc_t g_malloc_arr[VXGE_OS_MALLOC_CNT_MAX];
#define VXGE_OS_MEMORY_CHECK_MALLOC(_vaddr, _size, _file, _line) { \
if (_vaddr) { \
u32 i; \
for (i = 0; i < g_malloc_cnt; i++) { \
if (g_malloc_arr[i].ptr == NULL) \
break; \
} \
if (i == g_malloc_cnt) { \
g_malloc_cnt++; \
if (g_malloc_cnt >= VXGE_OS_MALLOC_CNT_MAX) { \
vxge_os_bug("g_malloc_cnt exceed %d\n", \
VXGE_OS_MALLOC_CNT_MAX); \
} else { \
g_malloc_arr[i].ptr = _vaddr; \
g_malloc_arr[i].size = _size; \
g_malloc_arr[i].file = _file; \
g_malloc_arr[i].line = _line; \
} \
} \
} \
}
#define VXGE_OS_MEMORY_CHECK_FREE(_vaddr, _size, _file, _line) { \
u32 i; \
for (i = 0; i < VXGE_OS_MALLOC_CNT_MAX; i++) { \
if (g_malloc_arr[i].ptr == _vaddr) { \
g_malloc_arr[i].ptr = NULL; \
if (_size && g_malloc_arr[i].size != _size) { \
vxge_os_printf("freeing wrong size " \
"%lu allocated %s:%lu:" \
VXGE_OS_LLXFMT":%lu\n", \
_size, \
g_malloc_arr[i].file, \
g_malloc_arr[i].line, \
(u64)(u_long) g_malloc_arr[i].ptr, \
g_malloc_arr[i].size); \
} \
break; \
} \
} \
}
#else
#define VXGE_OS_MEMORY_CHECK_MALLOC(prt, size, file, line)
#define VXGE_OS_MEMORY_CHECK_FREE(vaddr, size, file, line)
#endif
static inline void *
vxge_mem_alloc_ex(u_long size, const char *file, int line)
{
void *vaddr = NULL;
vaddr = malloc(size, M_DEVBUF, M_ZERO | M_NOWAIT);
if (NULL != vaddr) {
VXGE_OS_MEMORY_CHECK_MALLOC((void *)vaddr, size, file, line)
vxge_os_memzero(vaddr, size);
}
return (vaddr);
}
static inline void
vxge_mem_free_ex(const void *vaddr, u_long size, const char *file, int line)
{
if (NULL != vaddr) {
VXGE_OS_MEMORY_CHECK_FREE(vaddr, size, file, line)
free(__DECONST(void *, vaddr), M_DEVBUF);
}
}
#define vxge_os_malloc(pdev, size) \
vxge_mem_alloc_ex(size, __FILE__, __LINE__)
#define vxge_os_free(pdev, vaddr, size) \
vxge_mem_free_ex(vaddr, size, __FILE__, __LINE__)
#define vxge_mem_alloc(size) \
vxge_mem_alloc_ex(size, __FILE__, __LINE__)
#define vxge_mem_free(vaddr, size) \
vxge_mem_free_ex(vaddr, size, __FILE__, __LINE__)
#define vxge_free_packet(x) \
if (NULL != x) { m_freem(x); x = NULL; }
/*
* --------------------------- pci primitives ------------------------------
*/
#define vxge_os_pci_read8(pdev, cfgh, where, val) \
(*(val) = pci_read_config(pdev->ndev, where, 1))
#define vxge_os_pci_write8(pdev, cfgh, where, val) \
pci_write_config(pdev->ndev, where, val, 1)
#define vxge_os_pci_read16(pdev, cfgh, where, val) \
(*(val) = pci_read_config(pdev->ndev, where, 2))
#define vxge_os_pci_write16(pdev, cfgh, where, val) \
pci_write_config(pdev->ndev, where, val, 2)
#define vxge_os_pci_read32(pdev, cfgh, where, val) \
(*(val) = pci_read_config(pdev->ndev, where, 4))
#define vxge_os_pci_write32(pdev, cfgh, where, val) \
pci_write_config(pdev->ndev, where, val, 4)
static inline u32
vxge_os_pci_res_len(pci_dev_h pdev, pci_reg_h regh)
{
return (((vxge_bus_res_t *) regh)->bus_res_len);
}
static inline u8
vxge_os_pio_mem_read8(pci_dev_h pdev, pci_reg_h regh, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
return bus_space_read_1(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr));
}
static inline u16
vxge_os_pio_mem_read16(pci_dev_h pdev, pci_reg_h regh, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
return bus_space_read_2(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr));
}
static inline u32
vxge_os_pio_mem_read32(pci_dev_h pdev, pci_reg_h regh, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
return bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr));
}
static inline u64
vxge_os_pio_mem_read64(pci_dev_h pdev, pci_reg_h regh, void *addr)
{
u64 val, val_l, val_u;
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
val_l = bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) (((caddr_t) addr) + 4 - vaddr));
val_u = bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr));
val = ((val_l << 32) | val_u);
return (val);
}
static inline void
vxge_os_pio_mem_write8(pci_dev_h pdev, pci_reg_h regh, u8 val, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) regh)->bar_start_addr);
bus_space_write_1(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr), val);
}
static inline void
vxge_os_pio_mem_write16(pci_dev_h pdev, pci_reg_h regh, u16 val, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
bus_space_write_2(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr), val);
}
static inline void
vxge_os_pio_mem_write32(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
{
caddr_t vaddr =
(caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
bus_space_write_4(((vxge_bus_res_t *) regh)->bus_space_tag,
((vxge_bus_res_t *) regh)->bus_space_handle,
(bus_size_t) ((caddr_t) (addr) - vaddr), val);
}
static inline void
vxge_os_pio_mem_write64(pci_dev_h pdev, pci_reg_h regh, u64 val, void *addr)
{
u32 val_l = (u32) (val & 0xffffffff);
u32 val_u = (u32) (val >> 32);
vxge_os_pio_mem_write32(pdev, regh, val_l, addr);
vxge_os_pio_mem_write32(pdev, regh, val_u, (caddr_t) addr + 4);
}
#define vxge_os_flush_bridge vxge_os_pio_mem_read64
/*
* --------------------------- dma primitives -----------------------------
*/
#define VXGE_OS_DMA_DIR_TODEVICE 0
#define VXGE_OS_DMA_DIR_FROMDEVICE 1
#define VXGE_OS_DMA_DIR_BIDIRECTIONAL 2
#define VXGE_OS_INVALID_DMA_ADDR ((bus_addr_t)0)
static void
vxge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
if (error)
return;
*(bus_addr_t *) arg = segs->ds_addr;
}
static inline void *
vxge_os_dma_malloc(pci_dev_h pdev, u_long bytes, int dma_flags,
pci_dma_h * p_dmah, pci_dma_acc_h * p_dma_acch)
{
int error = 0;
bus_addr_t bus_addr = BUS_SPACE_MAXADDR;
bus_size_t boundary, max_size, alignment = PAGE_SIZE;
if (bytes > PAGE_SIZE) {
boundary = 0;
max_size = bytes;
} else {
boundary = PAGE_SIZE;
max_size = PAGE_SIZE;
}
error = bus_dma_tag_create(
bus_get_dma_tag(pdev->ndev), /* Parent */
alignment, /* Alignment */
boundary, /* Bounds */
bus_addr, /* Low Address */
bus_addr, /* High Address */
NULL, /* Filter Func */
NULL, /* Filter Func Argument */
bytes, /* Maximum Size */
1, /* Number of Segments */
max_size, /* Maximum Segment Size */
BUS_DMA_ALLOCNOW, /* Flags */
NULL, /* Lock Func */
NULL, /* Lock Func Arguments */
&(p_dmah->dma_tag)); /* DMA Tag */
if (error != 0) {
device_printf(pdev->ndev, "bus_dma_tag_create failed\n");
goto _exit0;
}
p_dmah->dma_size = bytes;
error = bus_dmamem_alloc(p_dmah->dma_tag, (void **)&p_dmah->dma_vaddr,
(BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT),
&p_dmah->dma_map);
if (error != 0) {
device_printf(pdev->ndev, "bus_dmamem_alloc failed\n");
goto _exit1;
}
VXGE_OS_MEMORY_CHECK_MALLOC(p_dmah->dma_vaddr, p_dmah->dma_size,
__FILE__, __LINE__);
return (p_dmah->dma_vaddr);
_exit1:
bus_dma_tag_destroy(p_dmah->dma_tag);
_exit0:
return (NULL);
}
static inline void
vxge_dma_free(pci_dev_h pdev, const void *vaddr, u_long size,
pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch,
const char *file, int line)
{
VXGE_OS_MEMORY_CHECK_FREE(p_dmah->dma_vaddr, size, file, line)
bus_dmamem_free(p_dmah->dma_tag, p_dmah->dma_vaddr, p_dmah->dma_map);
bus_dma_tag_destroy(p_dmah->dma_tag);
p_dmah->dma_map = NULL;
p_dmah->dma_tag = NULL;
p_dmah->dma_vaddr = NULL;
}
extern void
vxge_hal_blockpool_block_add(void *, void *, u32, pci_dma_h *, pci_dma_acc_h *);
static inline void
vxge_os_dma_malloc_async(pci_dev_h pdev, void *devh,
u_long size, int dma_flags)
{
pci_dma_h dma_h;
pci_dma_acc_h acc_handle;
void *block_addr = NULL;
block_addr = vxge_os_dma_malloc(pdev, size, dma_flags,
&dma_h, &acc_handle);
vxge_hal_blockpool_block_add(devh, block_addr, size,
&dma_h, &acc_handle);
}
static inline void
vxge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_paddr,
u64 dma_offset, size_t length, int dir)
{
bus_dmasync_op_t dmasync_op;
switch (dir) {
case VXGE_OS_DMA_DIR_TODEVICE:
dmasync_op = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_POSTWRITE;
break;
case VXGE_OS_DMA_DIR_FROMDEVICE:
dmasync_op = BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD;
break;
default:
case VXGE_OS_DMA_DIR_BIDIRECTIONAL:
dmasync_op = BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE;
break;
}
bus_dmamap_sync(dmah.dma_tag, dmah.dma_map, dmasync_op);
}
static inline dma_addr_t
vxge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah, void *vaddr, u_long size,
int dir, int dma_flags)
{
int error;
error = bus_dmamap_load(dmah.dma_tag, dmah.dma_map, dmah.dma_vaddr,
dmah.dma_size, vxge_dmamap_cb, &(dmah.dma_paddr), BUS_DMA_NOWAIT);
if (error != 0)
return (VXGE_OS_INVALID_DMA_ADDR);
dmah.dma_size = size;
return (dmah.dma_paddr);
}
static inline void
vxge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_paddr,
u32 size, int dir)
{
bus_dmamap_unload(dmah.dma_tag, dmah.dma_map);
}
#define vxge_os_dma_free(pdev, vaddr, size, dma_flags, p_dma_acch, p_dmah) \
vxge_dma_free(pdev, vaddr, size, p_dma_acch, p_dmah, \
__FILE__, __LINE__)
static inline int
vxge_os_is_my_packet(void *pdev, unsigned long addr)
{
return (0);
}
#endif /* _VXGE_OSDEP_H_ */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _VXGE_H_
#define __VXGE_H_
#include <dev/vxge/vxgehal/vxgehal.h>
#include <dev/vxge/vxge-osdep.h>
#include "vxge-firmware.h"
#define VXGE_GET_PARAM(str_kenv, to, param, hardcode) { \
static int __CONCAT(param, __LINE__); \
if (testenv(str_kenv) == 1) \
TUNABLE_INT_FETCH(str_kenv, \
&__CONCAT(param, __LINE__)); \
else \
__CONCAT(param, __LINE__) = hardcode; \
\
to.param = __CONCAT(param, __LINE__); \
}
#define VXGE_BUFFER_ALIGN(buffer_length, to) { \
if (buffer_length % to) \
buffer_length += \
(to - (buffer_length % to)); \
}
#define VXGE_HAL_VPATH_MSIX_ACTIVE 4
#define VXGE_HAL_VPATH_MSIX_ALARM_ID 2
#define VXGE_MSIX_ALARM_ID(hldev, i) \
((__hal_device_t *) hldev)->first_vp_id * \
VXGE_HAL_VPATH_MSIX_ACTIVE + i;
#define VXGE_DUAL_PORT_MODE 2
#define VXGE_DUAL_PORT_MAP 0xAAAAULL
#define VXGE_BAUDRATE 1000000000
#define VXGE_MAX_SEGS VXGE_HAL_MAX_FIFO_FRAGS
#define VXGE_TSO_SIZE 65600
#define VXGE_STATS_BUFFER_SIZE 65536
#define VXGE_PRINT_BUF_SIZE 128
#define VXGE_PMD_INFO_LEN 24
#define VXGE_RXD_REPLENISH_COUNT 4
#define VXGE_TX_LOW_THRESHOLD 32
/* Default configuration parameters */
#define VXGE_DEFAULT_USER_HARDCODED -1
#define VXGE_DEFAULT_CONFIG_VALUE 0xFF
#define VXGE_DEFAULT_CONFIG_ENABLE 1
#define VXGE_DEFAULT_CONFIG_DISABLE 0
#if __FreeBSD_version >= 800000
#define VXGE_DEFAULT_CONFIG_MQ_ENABLE 1
#else
#define VXGE_DEFAULT_CONFIG_MQ_ENABLE 0
#endif
#define VXGE_DEFAULT_CONFIG_IFQ_MAXLEN 1024
#define VXGE_DEFAULT_BR_SIZE 4096
#define VXGE_DEFAULT_RTH_BUCKET_SIZE 8
#define VXGE_DEFAULT_RING_BLOCK 2
#define VXGE_DEFAULT_SUPPORTED_DEVICES 1
#define VXGE_DEFAULT_DEVICE_POLL_MILLIS 2000
#define VXGE_DEFAULT_FIFO_ALIGNED_FRAGS 1
#define VXGE_DEFAULT_VPATH_PRIORITY_LOW 3
#define VXGE_DEFAULT_VPATH_PRIORITY_HIGH 0
#define VXGE_DEFAULT_ALL_VID_ENABLE \
VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE
#define VXGE_DEFAULT_STRIP_VLAN_TAG \
VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE
#define VXGE_DEFAULT_TTI_BTIMER_VAL 250000
#define VXGE_DEFAULT_TTI_LTIMER_VAL 80
#define VXGE_DEFAULT_TTI_RTIMER_VAL 0
#define VXGE_DEFAULT_RTI_BTIMER_VAL 250
#define VXGE_DEFAULT_RTI_LTIMER_VAL 100
#define VXGE_DEFAULT_RTI_RTIMER_VAL 0
#define VXGE_TTI_RTIMER_ADAPT_VAL 10
#define VXGE_RTI_RTIMER_ADAPT_VAL 15
#define VXGE_DEFAULT_TTI_TX_URANGE_A 5
#define VXGE_DEFAULT_TTI_TX_URANGE_B 15
#define VXGE_DEFAULT_TTI_TX_URANGE_C 40
#define VXGE_DEFAULT_RTI_RX_URANGE_A 5
#define VXGE_DEFAULT_RTI_RX_URANGE_B 15
#define VXGE_DEFAULT_RTI_RX_URANGE_C 40
#define VXGE_DEFAULT_TTI_TX_UFC_A 1
#define VXGE_DEFAULT_TTI_TX_UFC_B 5
#define VXGE_DEFAULT_TTI_TX_UFC_C 15
#define VXGE_DEFAULT_TTI_TX_UFC_D 40
#define VXGE_DEFAULT_RTI_RX_UFC_A 1
#define VXGE_DEFAULT_RTI_RX_UFC_B 20
#define VXGE_DEFAULT_RTI_RX_UFC_C 40
#define VXGE_DEFAULT_RTI_RX_UFC_D 100
#define VXGE_MAX_RX_INTERRUPT_COUNT 100
#define VXGE_MAX_TX_INTERRUPT_COUNT 200
#define is_multi_func(func_mode) \
((func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2) || \
(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8) || \
(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4) || \
(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2))
#define is_single_func(func_mode) \
(func_mode == VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17)
#define VXGE_DRV_STATS(v, x) v->driver_stats.x++
#define VXGE_MAX_MSIX_MESSAGES (VXGE_HAL_MAX_VIRTUAL_PATHS * 2 + 2)
#define VXGE_DRV_LOCK(x) mtx_lock(&(x)->mtx_drv)
#define VXGE_DRV_UNLOCK(x) mtx_unlock(&(x)->mtx_drv)
#define VXGE_DRV_LOCK_DESTROY(x) mtx_destroy(&(x)->mtx_drv)
#define VXGE_DRV_LOCK_ASSERT(x) mtx_assert(&(x)->mtx_drv, MA_OWNED)
#define VXGE_TX_LOCK(x) mtx_lock(&(x)->mtx_tx)
#define VXGE_TX_TRYLOCK(x) mtx_trylock(&(x)->mtx_tx)
#define VXGE_TX_UNLOCK(x) mtx_unlock(&(x)->mtx_tx)
#define VXGE_TX_LOCK_DESTROY(x) mtx_destroy(&(x)->mtx_tx)
#define VXGE_TX_LOCK_ASSERT(x) mtx_assert(&(x)->mtx_tx, MA_OWNED)
const char *
vxge_port_mode[6] =
{
"Default",
"Reserved",
"Active/Passive",
"Single Port",
"Dual Port",
"Disabled"
};
const char *
vxge_port_failure[3] =
{
"No Failover",
"Failover only",
"Failover & Failback"
};
/* IOCTLs to identify vxge-manage requests */
typedef enum _vxge_query_device_info_e {
VXGE_GET_PCI_CONF = 100,
VXGE_GET_MRPCIM_STATS = 101,
VXGE_GET_DEVICE_STATS = 102,
VXGE_GET_DEVICE_HWINFO = 103,
VXGE_GET_DRIVER_STATS = 104,
VXGE_GET_INTR_STATS = 105,
VXGE_GET_VERSION = 106,
VXGE_GET_TCODE = 107,
VXGE_GET_VPATH_COUNT = 108,
VXGE_GET_BANDWIDTH = 109,
VXGE_SET_BANDWIDTH = 110,
VXGE_GET_PORT_MODE = 111,
VXGE_SET_PORT_MODE = 112
} vxge_query_device_info_e;
typedef enum _vxge_firmware_upgrade_e {
VXGE_FW_UPGRADE_NONE = 0,
VXGE_FW_UPGRADE_ALL = 1,
VXGE_FW_UPGRADE_FORCE = 2
} vxge_firmware_upgrade_e;
typedef enum _vxge_free_resources_e {
VXGE_FREE_NONE = 0,
VXGE_FREE_MUTEX = 1,
VXGE_FREE_PCI_INFO = 2,
VXGE_FREE_BAR0 = 3,
VXGE_FREE_BAR1 = 4,
VXGE_FREE_BAR2 = 5,
VXGE_FREE_ISR_RESOURCE = 6,
VXGE_FREE_MEDIA = 7,
VXGE_FREE_INTERFACE = 8,
VXGE_FREE_DEVICE_CONFIG = 9,
VXGE_FREE_TERMINATE_DEVICE = 10,
VXGE_FREE_TERMINATE_DRIVER = 11,
VXGE_DISABLE_PCI_BUSMASTER = 12,
VXGE_FREE_VPATH = 13,
VXGE_FREE_ALL = 14
} vxge_free_resources_e;
typedef enum _vxge_device_attributes_e {
VXGE_PRINT_DRV_VERSION = 0,
VXGE_PRINT_PCIE_INFO = 1,
VXGE_PRINT_SERIAL_NO = 2,
VXGE_PRINT_PART_NO = 3,
VXGE_PRINT_FW_VERSION = 4,
VXGE_PRINT_FW_DATE = 5,
VXGE_PRINT_FUNC_MODE = 6,
VXGE_PRINT_INTR_MODE = 7,
VXGE_PRINT_VPATH_COUNT = 8,
VXGE_PRINT_MTU_SIZE = 9,
VXGE_PRINT_LRO_MODE = 10,
VXGE_PRINT_RTH_MODE = 11,
VXGE_PRINT_TSO_MODE = 12,
VXGE_PRINT_PMD_PORTS_0 = 13,
VXGE_PRINT_PMD_PORTS_1 = 14,
VXGE_PRINT_ADAPTER_TYPE = 15,
VXGE_PRINT_PORT_MODE = 16,
VXGE_PRINT_PORT_FAILURE = 17,
VXGE_PRINT_ACTIVE_PORT = 18,
VXGE_PRINT_L2SWITCH_MODE = 19
} vxge_device_attribute_e;
typedef struct _vxge_isr_info_t {
int irq_rid;
void *irq_handle;
struct resource *irq_res;
} vxge_isr_info_t;
typedef struct _vxge_drv_stats_t {
u64 isr_msix;
u64 tx_xmit;
u64 tx_posted;
u64 tx_compl;
u64 tx_tso;
u64 tx_tcode;
u64 tx_low_dtr_cnt;
u64 tx_reserve_failed;
u64 tx_no_dma_setup;
u64 tx_max_frags;
u64 tx_again;
u64 rx_compl;
u64 rx_tcode;
u64 rx_no_buf;
u64 rx_map_fail;
u64 rx_lro_queued;
u64 rx_lro_flushed;
} vxge_drv_stats_t;
typedef struct vxge_dev_t vxge_dev_t;
/* Rx descriptor private structure */
typedef struct _vxge_rxd_priv_t {
mbuf_t mbuf_pkt;
bus_size_t dma_sizes[1];
bus_addr_t dma_addr[1];
bus_dmamap_t dma_map;
} vxge_rxd_priv_t;
/* Tx descriptor private structure */
typedef struct _vxge_txdl_priv_t {
mbuf_t mbuf_pkt;
bus_dmamap_t dma_map;
bus_dma_segment_t dma_buffers[VXGE_MAX_SEGS];
} vxge_txdl_priv_t;
typedef struct _vxge_vpath_t {
u32 vp_id;
u32 vp_index;
u32 is_open;
u32 lro_enable;
int msix_vec;
int msix_vec_alarm;
u32 is_configured;
u64 rxd_posted;
macaddr_t mac_addr;
macaddr_t mac_mask;
int tx_ticks;
int rx_ticks;
u32 tti_rtimer_val;
u32 rti_rtimer_val;
u64 tx_interrupts;
u64 rx_interrupts;
int tx_intr_coalesce;
int rx_intr_coalesce;
vxge_dev_t *vdev;
vxge_hal_vpath_h handle;
char mtx_tx_name[16];
bus_dma_tag_t dma_tag_tx;
bus_dma_tag_t dma_tag_rx;
bus_dmamap_t extra_dma_map;
vxge_drv_stats_t driver_stats;
struct mtx mtx_tx;
struct lro_ctrl lro;
#if __FreeBSD_version >= 800000
struct buf_ring *br;
#endif
} vxge_vpath_t;
typedef struct _vxge_bw_info_t {
char query;
u64 func_id;
int priority;
int bandwidth;
} vxge_bw_info_t;
typedef struct _vxge_port_info_t {
char query;
int port_mode;
int port_failure;
} vxge_port_info_t;
typedef struct _vxge_device_hw_info_t {
vxge_hal_device_hw_info_t hw_info;
vxge_hal_xmac_nwif_dp_mode port_mode;
vxge_hal_xmac_nwif_behavior_on_failure port_failure;
} vxge_device_hw_info_t;
typedef struct _vxge_config_t {
u32 intr_mode;
int lro_enable;
int rth_enable;
int tso_enable;
int tx_steering;
int rth_bkt_sz;
int ifq_maxlen;
int no_of_vpath;
int ifq_multi;
int intr_coalesce;
int low_latency;
int l2_switch;
int port_mode;
int function_mode;
char nic_attr[20][128];
vxge_hal_device_hw_info_t hw_info;
vxge_firmware_upgrade_e fw_option;
vxge_hal_xmac_nwif_behavior_on_failure port_failure;
vxge_bw_info_t bw_info[VXGE_HAL_MAX_FUNCTIONS];
vxge_isr_info_t isr_info[VXGE_MAX_MSIX_MESSAGES];
} vxge_config_t;
struct vxge_dev_t {
device_t ndev;
bool is_privilaged;
bool is_initialized;
bool is_active;
int intr_count;
bool fw_upgrade;
int no_of_vpath;
u64 active_port;
u32 no_of_func;
u32 all_multi_flag;
u32 hw_fw_version;
u32 max_supported_vpath;
int rx_mbuf_sz;
int if_flags;
int ifm_optics;
ifnet_t ifp;
vxge_hal_xmac_nwif_dp_mode port_mode;
vxge_hal_xmac_nwif_l2_switch_status l2_switch;
vxge_hal_xmac_nwif_behavior_on_failure port_failure;
char ndev_name[16];
char mtx_drv_name[16];
struct mtx mtx_drv;
struct ifmedia media;
vxge_pci_info_t *pdev;
vxge_hal_device_t *devh;
vxge_vpath_t *vpaths;
vxge_config_t config;
vxge_hal_device_config_t *device_config;
vxge_hal_vpath_h vpath_handles[VXGE_HAL_MAX_VIRTUAL_PATHS];
};
int vxge_probe(device_t);
int vxge_attach(device_t);
int vxge_detach(device_t);
int vxge_shutdown(device_t);
int vxge_alloc_resources(vxge_dev_t *);
int vxge_alloc_isr_resources(vxge_dev_t *);
int vxge_alloc_bar_resources(vxge_dev_t *, int);
void vxge_free_resources(device_t, vxge_free_resources_e);
void vxge_free_isr_resources(vxge_dev_t *);
void vxge_free_bar_resources(vxge_dev_t *, int);
int vxge_device_hw_info_get(vxge_dev_t *);
int vxge_firmware_verify(vxge_dev_t *);
vxge_hal_status_e
vxge_driver_init(vxge_dev_t *);
vxge_hal_status_e
vxge_firmware_upgrade(vxge_dev_t *);
vxge_hal_status_e
vxge_func_mode_set(vxge_dev_t *);
vxge_hal_status_e
vxge_port_mode_set(vxge_dev_t *);
vxge_hal_status_e
vxge_port_behavior_on_failure_set(vxge_dev_t *);
vxge_hal_status_e
vxge_l2switch_mode_set(vxge_dev_t *);
void vxge_init(void *);
void vxge_init_locked(vxge_dev_t *);
void vxge_stop(vxge_dev_t *);
void vxge_stop_locked(vxge_dev_t *);
void vxge_reset(vxge_dev_t *);
int vxge_ifp_setup(device_t);
int vxge_isr_setup(vxge_dev_t *);
void vxge_media_init(vxge_dev_t *);
int vxge_media_change(ifnet_t);
void vxge_media_status(ifnet_t, struct ifmediareq *);
void vxge_mutex_init(vxge_dev_t *);
void vxge_mutex_destroy(vxge_dev_t *);
void vxge_link_up(vxge_hal_device_h, void *);
void vxge_link_down(vxge_hal_device_h, void *);
void vxge_crit_error(vxge_hal_device_h, void *, vxge_hal_event_e, u64);
int vxge_ioctl(ifnet_t, u_long, caddr_t);
int vxge_ioctl_regs(vxge_dev_t *, struct ifreq *);
int vxge_ioctl_stats(vxge_dev_t *, struct ifreq *);
void vxge_promisc_set(vxge_dev_t *);
void vxge_vpath_config(vxge_dev_t *);
int vxge_vpath_open(vxge_dev_t *);
void vxge_vpath_close(vxge_dev_t *);
void vxge_vpath_reset(vxge_dev_t *);
int vxge_change_mtu(vxge_dev_t *, unsigned long);
u32 vxge_ring_length_get(u32);
void vxge_isr_line(void *);
int vxge_isr_filter(void *);
void vxge_isr_msix(void *);
void vxge_isr_msix_alarm(void *);
void
vxge_intr_coalesce_tx(vxge_vpath_t *);
void
vxge_intr_coalesce_rx(vxge_vpath_t *);
vxge_hal_status_e
vxge_msix_enable(vxge_dev_t *);
vxge_hal_status_e
vxge_rth_config(vxge_dev_t *);
int vxge_dma_tags_create(vxge_vpath_t *);
void vxge_device_hw_info_print(vxge_dev_t *);
int vxge_driver_config(vxge_dev_t *);
#if __FreeBSD_version >= 800000
int
vxge_mq_send(ifnet_t, mbuf_t);
static inline int
vxge_mq_send_locked(ifnet_t, vxge_vpath_t *, mbuf_t);
void
vxge_mq_qflush(ifnet_t);
#endif
void
vxge_send(ifnet_t);
static inline void
vxge_send_locked(ifnet_t, vxge_vpath_t *);
static inline int
vxge_xmit(ifnet_t, vxge_vpath_t *, mbuf_t *);
static inline int
vxge_dma_mbuf_coalesce(bus_dma_tag_t, bus_dmamap_t,
mbuf_t *, bus_dma_segment_t *, int *);
static inline void
vxge_rx_checksum(vxge_hal_ring_rxd_info_t, mbuf_t);
static inline void
vxge_rx_input(ifnet_t, mbuf_t, vxge_vpath_t *);
static inline vxge_hal_vpath_h
vxge_vpath_handle_get(vxge_dev_t *, int);
static inline int
vxge_vpath_get(vxge_dev_t *, mbuf_t);
void
vxge_tso_config(vxge_dev_t *);
vxge_hal_status_e
vxge_tx_replenish(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
u32, void *, vxge_hal_reopen_e);
vxge_hal_status_e
vxge_tx_compl(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
vxge_hal_fifo_tcode_e, void *);
void
vxge_tx_term(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
vxge_hal_txdl_state_e, void *, vxge_hal_reopen_e);
vxge_hal_status_e
vxge_rx_replenish(vxge_hal_vpath_h, vxge_hal_rxd_h, void *,
u32, void *, vxge_hal_reopen_e);
vxge_hal_status_e
vxge_rx_compl(vxge_hal_vpath_h, vxge_hal_rxd_h, void *, u8, void *);
void
vxge_rx_term(vxge_hal_vpath_h, vxge_hal_rxd_h, void *,
vxge_hal_rxd_state_e, void *, vxge_hal_reopen_e);
void
vxge_rx_rxd_1b_get(vxge_vpath_t *, vxge_hal_rxd_h, void *);
int
vxge_rx_rxd_1b_set(vxge_vpath_t *, vxge_hal_rxd_h, void *);
int
vxge_bw_priority_config(vxge_dev_t *);
vxge_hal_status_e
vxge_bw_priority_get(vxge_dev_t *, vxge_bw_info_t *);
int
vxge_bw_priority_set(vxge_dev_t *, struct ifreq *);
int
vxge_bw_priority_update(vxge_dev_t *, u32, bool);
int
vxge_port_mode_update(vxge_dev_t *);
vxge_hal_status_e
vxge_port_mode_get(vxge_dev_t *, vxge_port_info_t *);
void
vxge_pmd_port_type_get(vxge_dev_t *, u32, char *, u8);
void
vxge_active_port_update(vxge_dev_t *);
static inline void
vxge_null_terminate(char *, size_t);
#endif /* _VXGE_H_ */

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sys/dev/vxge/vxgehal/vxge-queue.c Normal file
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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* vxge_queue_item_data - Get item's data.
* @item: Queue item.
*
* Returns: item data(variable size). Note that vxge_queue_t
* contains items comprized of a fixed vxge_queue_item_t "header"
* and a variable size data. This function returns the variable
* user-defined portion of the queue item.
*/
void *
vxge_queue_item_data(vxge_queue_item_t *item)
{
return (char *) item + sizeof(vxge_queue_item_t);
}
/*
* __queue_consume - (Lockless) dequeue an item from the specified queue.
*
* @queue: Event queue.
* @data_max_size: Maximum size of the data
* @item: Queue item
* See vxge_queue_consume().
*/
static vxge_queue_status_e
__queue_consume(vxge_queue_t *queue,
u32 data_max_size,
vxge_queue_item_t *item)
{
int real_size;
vxge_queue_item_t *elem;
__hal_device_t *hldev;
vxge_assert(queue != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue(
"queue = 0x"VXGE_OS_STXFMT", size = %d, item = 0x"VXGE_OS_STXFMT,
(ptr_t) queue, data_max_size, (ptr_t) item);
if (vxge_list_is_empty(&queue->list_head)) {
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_IS_EMPTY);
return (VXGE_QUEUE_IS_EMPTY);
}
elem = (vxge_queue_item_t *) queue->list_head.next;
if (elem->data_size > data_max_size) {
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_NOT_ENOUGH_SPACE);
return (VXGE_QUEUE_NOT_ENOUGH_SPACE);
}
vxge_list_remove(&elem->item);
real_size = elem->data_size + sizeof(vxge_queue_item_t);
if (queue->head_ptr == elem) {
queue->head_ptr = (char *) queue->head_ptr + real_size;
vxge_hal_info_log_queue("event_type: %d \
removing from the head: "
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
":0x0x"VXGE_OS_STXFMT" elem 0x0x"VXGE_OS_STXFMT" length %d",
elem->event_type, (ptr_t) queue->start_ptr,
(ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
(ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
} else if ((char *) queue->tail_ptr - real_size == (char *) elem) {
queue->tail_ptr = (char *) queue->tail_ptr - real_size;
vxge_hal_info_log_queue("event_type: %d \
removing from the tail: "
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
elem->event_type, (ptr_t) queue->start_ptr,
(ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
(ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
} else {
vxge_hal_info_log_queue("event_type: %d \
removing from the list: "
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
elem->event_type, (ptr_t) queue->start_ptr,
(ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
(ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
}
vxge_assert(queue->tail_ptr >= queue->head_ptr);
vxge_assert(queue->tail_ptr >= queue->start_ptr &&
queue->tail_ptr <= queue->end_ptr);
vxge_assert(queue->head_ptr >= queue->start_ptr &&
queue->head_ptr < queue->end_ptr);
vxge_os_memcpy(item, elem, sizeof(vxge_queue_item_t));
vxge_os_memcpy(vxge_queue_item_data(item), vxge_queue_item_data(elem),
elem->data_size);
if (vxge_list_is_empty(&queue->list_head)) {
/* reset buffer pointers just to be clean */
queue->head_ptr = queue->tail_ptr = queue->start_ptr;
}
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_QUEUE_OK);
}
/*
* vxge_queue_produce - Enqueue an item (see vxge_queue_item_t {})
* into the specified queue.
* @queueh: Queue handle.
* @event_type: Event type. One of the enumerated event types
* that both consumer and producer "understand".
* For an example, please refer to vxge_hal_event_e.
* @context: Opaque (void *) "context", for instance event producer object.
* @is_critical: For critical event, e.g. ECC.
* @data_size: Size of the @data.
* @data: User data of variable @data_size that is _copied_ into
* the new queue item (see vxge_queue_item_t {}). Upon return
* from the call the @data memory can be re-used or released.
*
* Enqueue a new item.
*
* Returns: VXGE_QUEUE_OK - success.
* VXGE_QUEUE_IS_FULL - Queue is full.
* VXGE_QUEUE_OUT_OF_MEMORY - Memory allocation failed.
*
* See also: vxge_queue_item_t {}, vxge_queue_consume().
*/
vxge_queue_status_e
vxge_queue_produce(vxge_queue_h queueh,
u32 event_type,
void *context,
u32 is_critical,
const u32 data_size,
void *data)
{
vxge_queue_t *queue = (vxge_queue_t *) queueh;
int real_size = data_size + sizeof(vxge_queue_item_t);
__hal_device_t *hldev;
vxge_queue_item_t *elem;
unsigned long flags = 0;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue(
"queueh = 0x"VXGE_OS_STXFMT", event_type = %d, "
"context = 0x"VXGE_OS_STXFMT", is_critical = %d, "
"data_size = %d, data = 0x"VXGE_OS_STXFMT,
(ptr_t) queueh, event_type, (ptr_t) context,
is_critical, data_size, (ptr_t) data);
vxge_assert(real_size <= VXGE_QUEUE_BUF_SIZE);
vxge_os_spin_lock_irq(&queue->lock, flags);
if (is_critical && !queue->has_critical_event) {
unsigned char item_buf[sizeof(vxge_queue_item_t) +
VXGE_DEFAULT_EVENT_MAX_DATA_SIZE];
vxge_queue_item_t *item =
(vxge_queue_item_t *) (void *)item_buf;
while (__queue_consume(queue, VXGE_DEFAULT_EVENT_MAX_DATA_SIZE,
item) != VXGE_QUEUE_IS_EMPTY) {
} /* do nothing */
}
try_again:
if ((char *) queue->tail_ptr + real_size <= (char *) queue->end_ptr) {
elem = (vxge_queue_item_t *) queue->tail_ptr;
queue->tail_ptr = (void *)((char *) queue->tail_ptr + real_size);
vxge_hal_info_log_queue("event_type: %d adding to the tail: "
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
event_type, (ptr_t) queue->start_ptr,
(ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
(ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
} else if ((char *) queue->head_ptr - real_size >=
(char *) queue->start_ptr) {
elem = (vxge_queue_item_t *)
((void *)((char *) queue->head_ptr - real_size));
queue->head_ptr = elem;
vxge_hal_info_log_queue("event_type: %d adding to the head: "
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":"
"0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT" length %d",
event_type, (ptr_t) queue->start_ptr,
(ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
(ptr_t) queue->end_ptr, real_size);
} else {
vxge_queue_status_e status;
if (queue->pages_current >= queue->pages_max) {
vxge_os_spin_unlock_irq(&queue->lock, flags);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_IS_FULL);
return (VXGE_QUEUE_IS_FULL);
}
if (queue->has_critical_event) {
vxge_os_spin_unlock_irq(&queue->lock, flags);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_IS_FULL);
return (VXGE_QUEUE_IS_FULL);
}
/* grow */
status = vxge_io_queue_grow(queueh);
if (status != VXGE_QUEUE_OK) {
vxge_os_spin_unlock_irq(&queue->lock, flags);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
goto try_again;
}
vxge_assert(queue->tail_ptr >= queue->head_ptr);
vxge_assert(queue->tail_ptr >= queue->start_ptr &&
queue->tail_ptr <= queue->end_ptr);
vxge_assert(queue->head_ptr >= queue->start_ptr &&
queue->head_ptr < queue->end_ptr);
elem->data_size = data_size;
elem->event_type = (vxge_hal_event_e) event_type;
elem->is_critical = is_critical;
if (is_critical)
queue->has_critical_event = 1;
elem->context = context;
vxge_os_memcpy(vxge_queue_item_data(elem), data, data_size);
vxge_list_insert_before(&elem->item, &queue->list_head);
vxge_os_spin_unlock_irq(&queue->lock, flags);
/* no lock taken! */
queue->queued_func(queue->queued_data, event_type);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_QUEUE_OK);
}
/*
* vxge_queue_create - Create protected first-in-first-out queue.
* @devh: HAL device handle.
* @pages_initial: Number of pages to be initially allocated at the
* time of queue creation.
* @pages_max: Max number of pages that can be allocated in the queue.
* @queued_func: Optional callback function to be called each time a new item is
* added to the queue.
* @queued_data: Argument to the callback function.
*
* Create protected (fifo) queue.
*
* Returns: Pointer to vxge_queue_t structure,
* NULL - on failure.
*
* See also: vxge_queue_item_t {}, vxge_queue_destroy().
*/
vxge_queue_h
vxge_queue_create(vxge_hal_device_h devh,
u32 pages_initial,
u32 pages_max,
vxge_queued_f queued_func,
void *queued_data)
{
vxge_queue_t *queue;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue(
"devh = 0x"VXGE_OS_STXFMT", pages_initial = %d, "
"pages_max = %d, queued_func = 0x"VXGE_OS_STXFMT", "
"queued_data = 0x"VXGE_OS_STXFMT, (ptr_t) devh, pages_initial,
pages_max, (ptr_t) queued_func, (ptr_t) queued_data);
if ((queue = (vxge_queue_t *) vxge_os_malloc(hldev->header.pdev,
sizeof(vxge_queue_t))) == NULL) {
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
return (NULL);
}
queue->queued_func = queued_func;
queue->queued_data = queued_data;
queue->hldev = devh;
queue->pdev = hldev->header.pdev;
queue->irqh = hldev->header.irqh;
queue->pages_current = pages_initial;
queue->start_ptr = vxge_os_malloc(hldev->header.pdev,
queue->pages_current * VXGE_QUEUE_BUF_SIZE);
if (queue->start_ptr == NULL) {
vxge_os_free(hldev->header.pdev, queue, sizeof(vxge_queue_t));
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
return (NULL);
}
queue->head_ptr = queue->tail_ptr = queue->start_ptr;
queue->end_ptr = (char *) queue->start_ptr +
queue->pages_current * VXGE_QUEUE_BUF_SIZE;
vxge_os_spin_lock_init_irq(&queue->lock, queue->irqh);
queue->pages_initial = pages_initial;
queue->pages_max = pages_max;
vxge_list_init(&queue->list_head);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (queue);
}
/*
* vxge_queue_destroy - Destroy vxge_queue_t object.
* @queueh: Queue handle.
*
* Destroy the specified vxge_queue_t object.
*
* See also: vxge_queue_item_t {}, vxge_queue_create().
*/
void
vxge_queue_destroy(vxge_queue_h queueh)
{
vxge_queue_t *queue = (vxge_queue_t *) queueh;
__hal_device_t *hldev;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
(ptr_t) queueh);
vxge_os_spin_lock_destroy_irq(&queue->lock, queue->irqh);
if (!vxge_list_is_empty(&queue->list_head)) {
vxge_hal_trace_log_queue("destroying non-empty queue 0x"
VXGE_OS_STXFMT, (ptr_t) queue);
}
vxge_os_free(queue->pdev, queue->start_ptr, queue->pages_current *
VXGE_QUEUE_BUF_SIZE);
vxge_os_free(queue->pdev, queue, sizeof(vxge_queue_t));
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* vxge_io_queue_grow - Dynamically increases the size of the queue.
* @queueh: Queue handle.
*
* This function is called in the case of no slot avaialble in the queue
* to accomodate the newly received event.
* Note that queue cannot grow beyond the max size specified for the
* queue.
*
* Returns VXGE_QUEUE_OK: On success.
* VXGE_QUEUE_OUT_OF_MEMORY : No memory is available.
*/
vxge_queue_status_e
vxge_io_queue_grow(vxge_queue_h queueh)
{
vxge_queue_t *queue = (vxge_queue_t *) queueh;
__hal_device_t *hldev;
void *newbuf, *oldbuf;
vxge_list_t *item;
vxge_queue_item_t *elem;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
(ptr_t) queueh);
vxge_hal_info_log_queue("queue 0x"VXGE_OS_STXFMT":%d is growing",
(ptr_t) queue, queue->pages_current);
newbuf = vxge_os_malloc(queue->pdev,
(queue->pages_current + 1) * VXGE_QUEUE_BUF_SIZE);
if (newbuf == NULL) {
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
return (VXGE_QUEUE_OUT_OF_MEMORY);
}
vxge_os_memcpy(newbuf, queue->start_ptr,
queue->pages_current * VXGE_QUEUE_BUF_SIZE);
oldbuf = queue->start_ptr;
/* adjust queue sizes */
queue->start_ptr = newbuf;
queue->end_ptr = (char *) newbuf +
(queue->pages_current + 1) * VXGE_QUEUE_BUF_SIZE;
queue->tail_ptr = (char *) newbuf +
/* LINTED */
((char *) queue->tail_ptr - (char *) oldbuf);
queue->head_ptr = (char *) newbuf +
/* LINTED */
((char *) queue->head_ptr - (char *) oldbuf);
vxge_assert(!vxge_list_is_empty(&queue->list_head));
queue->list_head.next = (vxge_list_t *) (void *)((char *) newbuf +
/* LINTED */
((char *) queue->list_head.next - (char *) oldbuf));
queue->list_head.prev = (vxge_list_t *) (void *)((char *) newbuf +
/* LINTED */
((char *) queue->list_head.prev - (char *) oldbuf));
/* adjust queue list */
vxge_list_for_each(item, &queue->list_head) {
elem = vxge_container_of(item, vxge_queue_item_t, item);
if (elem->item.next != &queue->list_head) {
elem->item.next =
(vxge_list_t *) (void *)((char *) newbuf +
/* LINTED */
((char *) elem->item.next - (char *) oldbuf));
}
if (elem->item.prev != &queue->list_head) {
elem->item.prev =
(vxge_list_t *) (void *)((char *) newbuf +
/* LINTED */
((char *) elem->item.prev - (char *) oldbuf));
}
}
vxge_os_free(queue->pdev, oldbuf,
queue->pages_current * VXGE_QUEUE_BUF_SIZE);
queue->pages_current++;
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_QUEUE_OK);
}
/*
* vxge_queue_consume - Dequeue an item from the specified queue.
* @queueh: Queue handle.
* @data_max_size: Maximum expected size of the item.
* @item: Memory area into which the item is _copied_ upon return
* from the function.
*
* Dequeue an item from the queue. The caller is required to provide
* enough space for the item.
*
* Returns: VXGE_QUEUE_OK - success.
* VXGE_QUEUE_IS_EMPTY - Queue is empty.
* VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
* is too small to accomodate an item from the queue.
*
* See also: vxge_queue_item_t {}, vxge_queue_produce().
*/
vxge_queue_status_e
vxge_queue_consume(vxge_queue_h queueh,
u32 data_max_size,
vxge_queue_item_t *item)
{
vxge_queue_t *queue = (vxge_queue_t *) queueh;
__hal_device_t *hldev;
unsigned long flags = 0;
vxge_queue_status_e status;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue(
"queueh = 0x"VXGE_OS_STXFMT", data_max_size = %d, "
"item = 0x"VXGE_OS_STXFMT, (ptr_t) queueh,
data_max_size, (ptr_t) item);
vxge_os_spin_lock_irq(&queue->lock, flags);
status = __queue_consume(queue, data_max_size, item);
vxge_os_spin_unlock_irq(&queue->lock, flags);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* vxge_queue_flush - Flush, or empty, the queue.
* @queueh: Queue handle.
*
* Flush the queue, i.e. make it empty by consuming all events
* without invoking the event processing logic (callbacks, etc.)
*/
void
vxge_queue_flush(vxge_queue_h queueh)
{
unsigned char item_buf[sizeof(vxge_queue_item_t) +
VXGE_DEFAULT_EVENT_MAX_DATA_SIZE];
vxge_queue_item_t *item = (vxge_queue_item_t *) (void *)item_buf;
vxge_queue_t *queue = (vxge_queue_t *) queueh;
__hal_device_t *hldev;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
(ptr_t) queueh);
/* flush queue by consuming all enqueued items */
while (vxge_queue_consume(queueh, VXGE_DEFAULT_EVENT_MAX_DATA_SIZE,
item) != VXGE_QUEUE_IS_EMPTY) {
/* do nothing */
vxge_hal_trace_log_queue("item 0x"VXGE_OS_STXFMT"(%d) flushed",
(ptr_t) item, item->event_type);
}
(void) vxge_queue_get_reset_critical(queueh);
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* vxge_queue_get_reset_critical - Check for critical events in the queue,
* @queueh: Queue handle.
*
* Check for critical event(s) in the queue, and reset the
* "has-critical-event" flag upon return.
* Returns: 1 - if the queue contains atleast one critical event.
* 0 - If there are no critical events in the queue.
*/
u32
vxge_queue_get_reset_critical(vxge_queue_h queueh)
{
vxge_queue_t *queue = (vxge_queue_t *) queueh;
int c = queue->has_critical_event;
__hal_device_t *hldev;
vxge_assert(queueh != NULL);
hldev = (__hal_device_t *) queue->hldev;
vxge_hal_trace_log_queue("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
(ptr_t) queueh);
queue->has_critical_event = 0;
vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (c);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_BLOCKPOOL_H
#define VXGE_HAL_BLOCKPOOL_H
__EXTERN_BEGIN_DECLS
/*
* struct __hal_blockpool_entry_t - Block private data structure
* @item: List header used to link.
* @length: Length of the block
* @memblock: Virtual address block
* @dma_addr: DMA Address of the block.
* @dma_handle: DMA handle of the block.
* @acc_handle: DMA acc handle
*
* Block is allocated with a header to put the blocks into list.
*
*/
typedef struct __hal_blockpool_entry_t {
vxge_list_t item;
u32 length;
void *memblock;
dma_addr_t dma_addr;
pci_dma_h dma_handle;
pci_dma_acc_h acc_handle;
} __hal_blockpool_entry_t;
/*
* struct __hal_blockpool_t - Block Pool
* @hldev: HAL device
* @block_size: size of each block.
* @Pool_size: Number of blocks in the pool
* @pool_incr: Number of blocks to be requested/freed at a time from OS
* @pool_min: Minimum number of block below which to request additional blocks
* @pool_max: Maximum number of blocks above which to free additional blocks
* @req_out: Number of block requests with OS out standing
* @dma_flags: DMA flags
* @free_block_list: List of free blocks
* @pool_lock: Spin lock for the pool
*
* Block pool contains the DMA blocks preallocated.
*
*/
typedef struct __hal_blockpool_t {
vxge_hal_device_h hldev;
u32 block_size;
u32 pool_size;
u32 pool_incr;
u32 pool_min;
u32 pool_max;
u32 req_out;
u32 dma_flags;
vxge_list_t free_block_list;
vxge_list_t free_entry_list;
#if defined(VXGE_HAL_BP_POST) || defined(VXGE_HAL_BP_POST_IRQ)
spinlock_t pool_lock;
#endif
} __hal_blockpool_t;
vxge_hal_status_e
__hal_blockpool_create(vxge_hal_device_h hldev,
__hal_blockpool_t *blockpool,
u32 pool_size,
u32 pool_incr,
u32 pool_min,
u32 pool_max);
void
__hal_blockpool_destroy(__hal_blockpool_t *blockpool);
__hal_blockpool_entry_t *
__hal_blockpool_block_allocate(vxge_hal_device_h hldev,
u32 size);
void
__hal_blockpool_block_free(vxge_hal_device_h hldev,
__hal_blockpool_entry_t *entry);
void *
__hal_blockpool_malloc(vxge_hal_device_h hldev,
u32 size,
dma_addr_t *dma_addr,
pci_dma_h *dma_handle,
pci_dma_acc_h *acc_handle);
void
__hal_blockpool_free(vxge_hal_device_h hldev,
void *memblock,
u32 size,
dma_addr_t *dma_addr,
pci_dma_h *dma_handle,
pci_dma_acc_h *acc_handle);
vxge_hal_status_e
__hal_blockpool_list_allocate(vxge_hal_device_h hldev,
vxge_list_t *blocklist, u32 count);
void
__hal_blockpool_list_free(vxge_hal_device_h hldev,
vxge_list_t *blocklist);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_BLOCKPOOL_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* vxge_hal_channel_allocate - Allocate memory for channel
* @devh: Handle to the device object
* @vph: Handle to Virtual Path
* @type: Type of channel
* @length: Lengths of arrays
* @per_dtr_space: ULD requested per dtr space to be allocated in priv
* @userdata: User data to be passed back in the callback
*
* This function allocates required memory for the channel and various arrays
* in the channel
*/
__hal_channel_t *
vxge_hal_channel_allocate(
vxge_hal_device_h devh,
vxge_hal_vpath_h vph,
__hal_channel_type_e type,
u32 length,
u32 per_dtr_space,
void *userdata)
{
vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
__hal_channel_t *channel;
u32 i, size = 0;
vxge_assert((devh != NULL) && (vph != NULL));
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT", vph = "
"0x"VXGE_OS_STXFMT", type = %d, length = %d, "
"per_dtr_space = %d, userdata = 0x"VXGE_OS_STXFMT,
(ptr_t) devh, (ptr_t) vph, type, length, per_dtr_space,
(ptr_t) userdata);
switch (type) {
case VXGE_HAL_CHANNEL_TYPE_FIFO:
size = sizeof(__hal_fifo_t);
break;
case VXGE_HAL_CHANNEL_TYPE_RING:
size = sizeof(__hal_ring_t);
break;
default:
vxge_assert(size);
break;
}
channel = (__hal_channel_t *) vxge_os_malloc(hldev->pdev, size);
if (channel == NULL) {
vxge_hal_trace_log_channel("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(channel, size);
vxge_list_init(&channel->item);
channel->pdev = hldev->pdev;
channel->type = type;
channel->devh = devh;
channel->vph = vph;
channel->userdata = userdata;
channel->per_dtr_space = per_dtr_space;
channel->length = length;
channel->dtr_arr = (__hal_dtr_item_t *) vxge_os_malloc(hldev->pdev,
sizeof(__hal_dtr_item_t)*length);
if (channel->dtr_arr == NULL) {
vxge_hal_channel_free(channel);
vxge_hal_trace_log_channel("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(channel->dtr_arr, sizeof(__hal_dtr_item_t)*length);
channel->compl_index = 0;
channel->reserve_index = 0;
for (i = 0; i < length; i++)
channel->dtr_arr[i].state = VXGE_HAL_CHANNEL_DTR_FREE;
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (channel);
}
/*
* __hal_channel_free - Free memory allocated for channel
* @channel: channel to be freed
*
* This function deallocates memory from the channel and various arrays
* in the channel
*/
void
vxge_hal_channel_free(
__hal_channel_t *channel)
{
int size = 0;
vxge_hal_device_t *hldev;
vxge_assert(channel != NULL);
hldev = (vxge_hal_device_t *) channel->devh;
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
(ptr_t) channel);
vxge_assert(channel->pdev);
if (channel->dtr_arr) {
vxge_os_free(channel->pdev, channel->dtr_arr,
sizeof(__hal_dtr_item_t)*channel->length);
channel->dtr_arr = NULL;
}
switch (channel->type) {
case VXGE_HAL_CHANNEL_TYPE_FIFO:
size = sizeof(__hal_fifo_t);
break;
case VXGE_HAL_CHANNEL_TYPE_RING:
size = sizeof(__hal_ring_t);
break;
default:
break;
}
vxge_os_free(channel->pdev, channel, size);
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_channel_initialize - Initialize a channel
* @channel: channel to be initialized
*
* This function initializes a channel by properly
* setting the various references
*/
vxge_hal_status_e
vxge_hal_channel_initialize(
__hal_channel_t *channel)
{
vxge_hal_device_t *hldev;
__hal_virtualpath_t *vpath;
vxge_assert(channel != NULL);
hldev = (vxge_hal_device_t *) channel->devh;
vpath = (__hal_virtualpath_t *)
((__hal_vpath_handle_t *) channel->vph)->vpath;
vxge_assert(vpath != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
(ptr_t) channel);
switch (channel->type) {
case VXGE_HAL_CHANNEL_TYPE_FIFO:
vpath->fifoh = (vxge_hal_fifo_h) channel;
channel->stats =
&((__hal_fifo_t *) channel)->stats->common_stats;
break;
case VXGE_HAL_CHANNEL_TYPE_RING:
vpath->ringh = (vxge_hal_ring_h) channel;
channel->stats =
&((__hal_ring_t *) channel)->stats->common_stats;
break;
default:
break;
}
channel->is_initd = 1;
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* __hal_channel_reset - Resets a channel
* @channel: channel to be reset
*
* This function resets a channel by properly setting the various references
*/
vxge_hal_status_e
__hal_channel_reset(
__hal_channel_t *channel)
{
u32 i;
__hal_device_t *hldev;
vxge_assert(channel != NULL);
hldev = (__hal_device_t *) channel->devh;
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
(ptr_t) channel);
vxge_assert(channel->pdev);
channel->compl_index = 0;
channel->reserve_index = 0;
for (i = 0; i < channel->length; i++) {
channel->dtr_arr[i].state =
VXGE_HAL_CHANNEL_DTR_FREE;
}
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* vxge_hal_channel_terminate - Deinitializes a channel
* @channel: channel to be deinitialized
*
* This function deinitializes a channel by properly
* setting the various references
*/
void
vxge_hal_channel_terminate(
__hal_channel_t *channel)
{
__hal_device_t *hldev;
__hal_virtualpath_t *vpath;
vxge_assert(channel != NULL);
if (!channel || !channel->is_initd)
return;
hldev = (__hal_device_t *) channel->devh;
vpath = (__hal_virtualpath_t *)
((__hal_vpath_handle_t *) channel->vph)->vpath;
vxge_assert(vpath != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
(ptr_t) channel);
switch (channel->type) {
case VXGE_HAL_CHANNEL_TYPE_FIFO:
vpath->fifoh = 0;
break;
case VXGE_HAL_CHANNEL_TYPE_RING:
vpath->ringh = 0;
break;
case VXGE_HAL_CHANNEL_TYPE_SEND_QUEUE:
vxge_list_remove(&channel->item);
vpath->sw_stats->obj_counts.no_sqs--;
break;
case VXGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE:
vxge_list_remove(&channel->item);
vpath->sw_stats->obj_counts.no_srqs--;
break;
case VXGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE:
vxge_list_remove(&channel->item);
vpath->sw_stats->obj_counts.no_cqrqs--;
break;
default:
break;
}
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
void
__hal_channel_init_pending_list(
vxge_hal_device_h devh)
{
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
vxge_list_init(&hldev->pending_channel_list);
#if defined(VXGE_HAL_VP_CHANNELS)
vxge_os_spin_lock_init(&hldev->pending_channel_lock, hldev->pdev);
#elif defined(VXGE_HAL_VP_CHANNELS_IRQ)
vxge_os_spin_lock_init_irq(&hldev->pending_channel_lock, hldev->irqh);
#endif
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
void
__hal_channel_insert_pending_list(
__hal_channel_t * channel)
{
__hal_device_t *hldev = (__hal_device_t *) channel->devh;
vxge_assert(channel != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
(ptr_t) channel);
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_lock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_lock_irq(&hldev->pending_channel_lock, flags);
#endif
vxge_list_insert_before(&channel->item, &hldev->pending_channel_list);
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_unlock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_unlock_irq(&hldev->pending_channel_lock, flags);
#endif
__hal_channel_process_pending_list(channel->devh);
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
void
__hal_channel_process_pending_list(
vxge_hal_device_h devh)
{
vxge_hal_status_e status;
__hal_channel_t *channel;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
for (;;) {
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_lock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_lock_irq(&hldev->pending_channel_lock, flags);
#endif
channel = (__hal_channel_t *)
vxge_list_first_get(&hldev->pending_channel_list);
if (channel != NULL)
vxge_list_remove(&channel->item);
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_unlock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_unlock_irq(&hldev->pending_channel_lock, flags);
#endif
if (channel == NULL) {
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return;
}
switch (channel->type) {
default:
status = VXGE_HAL_OK;
break;
}
if (status == VXGE_HAL_ERR_OUT_OF_MEMORY) {
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_lock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_lock_irq(&hldev->pending_channel_lock,
flags);
#endif
vxge_list_insert(&channel->item,
&hldev->pending_channel_list);
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_unlock(&hldev->pending_channel_lock);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_unlock_irq(&hldev->pending_channel_lock,
flags);
#endif
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return;
}
}
}
void
__hal_channel_destroy_pending_list(
vxge_hal_device_h devh)
{
vxge_list_t *p, *n;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_channel("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
vxge_list_for_each_safe(p, n, &hldev->pending_channel_list) {
vxge_list_remove(p);
switch (((__hal_channel_t *) p)->type) {
default:
break;
}
}
#if defined(VXGE_HAL_PENDING_CHANNELS)
vxge_os_spin_lock_destroy(&hldev->pending_channel_lock,
hldev->header.pdev);
#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
vxge_os_spin_lock_destroy_irq(&hldev->pending_channel_lock,
hldev->header.pdev);
#endif
vxge_hal_trace_log_channel("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_CHANNEL_H
#define VXGE_HAL_CHANNEL_H
__EXTERN_BEGIN_DECLS
/*
* __hal_dtr_h - Handle to the desriptor object used for nonoffload
* send or receive. Generic handle which can be with txd or rxd
*/
typedef void *__hal_dtr_h;
/*
* enum __hal_channel_type_e - Enumerated channel types.
* @VXGE_HAL_CHANNEL_TYPE_UNKNOWN: Unknown channel.
* @VXGE_HAL_CHANNEL_TYPE_FIFO: fifo.
* @VXGE_HAL_CHANNEL_TYPE_RING: ring.
* @VXGE_HAL_CHANNEL_TYPE_SQ: Send Queue
* @VXGE_HAL_CHANNEL_TYPE_SRQ: Receive Queue
* @VXGE_HAL_CHANNEL_TYPE_CQRQ: Receive queue completion queue
* @VXGE_HAL_CHANNEL_TYPE_UMQ: Up message queue
* @VXGE_HAL_CHANNEL_TYPE_DMQ: Down message queue
* @VXGE_HAL_CHANNEL_TYPE_MAX: Maximum number of HAL-supported
* (and recognized) channel types. Currently: 7.
*
* Enumerated channel types. Currently there are only two link-layer
* channels - X3100 fifo and X3100 ring. In the future the list will grow.
*/
typedef enum __hal_channel_type_e {
VXGE_HAL_CHANNEL_TYPE_UNKNOWN = 0,
VXGE_HAL_CHANNEL_TYPE_FIFO = 1,
VXGE_HAL_CHANNEL_TYPE_RING = 2,
VXGE_HAL_CHANNEL_TYPE_SEND_QUEUE = 3,
VXGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE = 4,
VXGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE = 5,
VXGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE = 6,
VXGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE = 7,
VXGE_HAL_CHANNEL_TYPE_MAX = 8
} __hal_channel_type_e;
/*
* __hal_dtr_item_t
* @dtr: Pointer to the descriptors that contains the dma data
* to/from the device.
* @hal_priv: HAL Private data related to the dtr.
* @uld_priv: ULD Private data related to the dtr.
*/
typedef struct __hal_dtr_item_t {
void *dtr;
void *hal_priv;
void *uld_priv;
u32 state;
#define VXGE_HAL_CHANNEL_DTR_FREE 0
#define VXGE_HAL_CHANNEL_DTR_RESERVED 1
#define VXGE_HAL_CHANNEL_DTR_POSTED 2
#define VXGE_HAL_CHANNEL_DTR_COMPLETED 3
} __hal_dtr_item_t;
/*
* __hal_channel_t
* @item: List item; used to maintain a list of open channels.
* @type: Channel type. See vxge_hal_channel_type_e {}.
* @devh: Device handle. HAL device object that contains _this_ channel.
* @pdev: PCI Device object
* @vph: Virtual path handle. Virtual Path Object that contains _this_ channel.
* @length: Channel length. Currently allocated number of descriptors.
* The channel length "grows" when more descriptors get allocated.
* See _hal_mempool_grow.
* @dtr_arr: Dtr array. Contains descriptors posted to the channel and their
* private data.
* Note that at any point in time @dtr_arr contains 3 types of
* descriptors:
* 1) posted but not yet consumed by X3100 device;
* 2) consumed but not yet completed;
* 3) completed.
* @post_index: Post index. At any point in time points on the
* position in the channel, which'll contain next to-be-posted
* descriptor.
* @compl_index: Completion index. At any point in time points on the
* position in the channel, which will contain next
* to-be-completed descriptor.
* @reserve_index: Reserve index. At any point in time points on the
* position in the channel, which will contain next
* to-be-reserved descriptor.
* @free_dtr_count: Number of dtrs free.
* @posted_dtr_count: Number of dtrs posted
* @post_lock: Lock to serialize multiple concurrent "posters" of descriptors
* on the given channel.
* @poll_bytes: Poll bytes.
* @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
* to store per-operation control information.
* @stats: Pointer to common statistics
* @userdata: Per-channel opaque (void *) user-defined context, which may be
* upper-layer driver object, ULP connection, etc.
* Once channel is open, @userdata is passed back to user via
* vxge_hal_channel_callback_f.
*
* HAL channel object.
*
* See also: vxge_hal_channel_type_e {}, vxge_hal_channel_flag_e
*/
typedef struct __hal_channel_t {
vxge_list_t item;
__hal_channel_type_e type;
vxge_hal_device_h devh;
pci_dev_h pdev;
vxge_hal_vpath_h vph;
u32 length;
u32 is_initd;
__hal_dtr_item_t *dtr_arr;
u32 compl_index __vxge_os_attr_cacheline_aligned;
u32 reserve_index __vxge_os_attr_cacheline_aligned;
spinlock_t post_lock;
u32 poll_bytes;
u32 per_dtr_space;
vxge_hal_vpath_stats_sw_common_info_t *stats;
void *userdata;
} __hal_channel_t __vxge_os_attr_cacheline_aligned;
#define __hal_channel_is_posted_dtr(channel, index) \
((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED)
#define __hal_channel_for_each_posted_dtr(channel, dtrh, index) \
for (index = (channel)->compl_index,\
dtrh = (channel)->dtr_arr[index].dtr; \
(index < (channel)->reserve_index) && \
((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED); \
index = (++index == (channel)->length)? 0 : index, \
dtrh = (channel)->dtr_arr[index].dtr)
#define __hal_channel_for_each_dtr(channel, dtrh, index) \
for (index = 0, dtrh = (channel)->dtr_arr[index].dtr; \
index < (channel)->length; \
dtrh = ((++index == (channel)->length)? 0 : \
(channel)->dtr_arr[index].dtr))
#define __hal_channel_free_dtr_count(channel) \
(((channel)->reserve_index < (channel)->compl_index) ? \
((channel)->compl_index - (channel)->reserve_index) : \
(((channel)->length - (channel)->reserve_index) + \
(channel)->reserve_index))
/* ========================== CHANNEL PRIVATE API ========================= */
__hal_channel_t *
vxge_hal_channel_allocate(
vxge_hal_device_h devh,
vxge_hal_vpath_h vph,
__hal_channel_type_e type,
u32 length,
u32 per_dtr_space,
void *userdata);
void
vxge_hal_channel_free(
__hal_channel_t *channel);
vxge_hal_status_e
vxge_hal_channel_initialize(
__hal_channel_t *channel);
vxge_hal_status_e
__hal_channel_reset(
__hal_channel_t *channel);
void
vxge_hal_channel_terminate(
__hal_channel_t *channel);
void
__hal_channel_init_pending_list(
vxge_hal_device_h devh);
void
__hal_channel_insert_pending_list(
__hal_channel_t * channel);
void
__hal_channel_process_pending_list(
vxge_hal_device_h devhv);
void
__hal_channel_destroy_pending_list(
vxge_hal_device_h devh);
#if defined(VXGE_DEBUG_FP) && (VXGE_DEBUG_FP & VXGE_DEBUG_FP_CHANNEL)
#define __HAL_STATIC_CHANNEL
#define __HAL_INLINE_CHANNEL
#else /* VXGE_FASTPATH_EXTERN */
#define __HAL_STATIC_CHANNEL static
#define __HAL_INLINE_CHANNEL inline
#endif /* VXGE_FASTPATH_INLINE */
/* ========================== CHANNEL Fast Path API ========================= */
/*
* __hal_channel_dtr_reserve- Reserve a dtr from the channel
* @channelh: Channel
* @dtrh: Buffer to return the DTR pointer
*
* Reserve a dtr from the reserve array.
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL vxge_hal_status_e
/* LINTED */
__hal_channel_dtr_reserve(__hal_channel_t *channel, __hal_dtr_h *dtrh)
{
vxge_hal_status_e status = VXGE_HAL_INF_OUT_OF_DESCRIPTORS;
*dtrh = NULL;
if (channel->dtr_arr[channel->reserve_index].state ==
VXGE_HAL_CHANNEL_DTR_FREE) {
*dtrh = channel->dtr_arr[channel->reserve_index].dtr;
channel->dtr_arr[channel->reserve_index].state =
VXGE_HAL_CHANNEL_DTR_RESERVED;
if (++channel->reserve_index == channel->length)
channel->reserve_index = 0;
status = VXGE_HAL_OK;
} else {
#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
__hal_device_t *hldev = (__hal_device_t *) channel->devh;
vxge_hal_info_log_channel("channel %d is full!", channel->type);
#endif
channel->stats->full_cnt++;
}
return (status);
}
/*
* __hal_channel_dtr_restore - Restores a dtr to the channel
* @channelh: Channel
* @dtr: DTR pointer
*
* Returns a dtr back to reserve array.
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
/* LINTED */
__hal_channel_dtr_restore(__hal_channel_t *channel, __hal_dtr_h dtrh)
{
u32 dtr_index;
/*
* restore a previously allocated dtrh at current offset and update
* the available reserve length accordingly. If dtrh is null just
* update the reserve length, only
*/
if (channel->reserve_index == 0)
dtr_index = channel->length;
else
dtr_index = channel->reserve_index - 1;
if ((channel->dtr_arr[dtr_index].dtr == dtrh)) {
channel->reserve_index = dtr_index;
channel->dtr_arr[dtr_index].state = VXGE_HAL_CHANNEL_DTR_FREE;
#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
__hal_device_t *hldev = (__hal_device_t *) channel->devh;
vxge_hal_info_log_channel("dtrh 0x"VXGE_OS_STXFMT" \
restored for " "channel %d at reserve index %d, ",
(ptr_t) dtrh, channel->type,
channel->reserve_index);
#endif
}
}
/*
* __hal_channel_dtr_post - Post a dtr to the channel
* @channelh: Channel
* @dtr: DTR pointer
*
* Posts a dtr to work array.
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
/* LINTED */
__hal_channel_dtr_post(__hal_channel_t *channel, u32 dtr_index)
{
channel->dtr_arr[dtr_index].state =
VXGE_HAL_CHANNEL_DTR_POSTED;
}
/*
* __hal_channel_dtr_try_complete - Returns next completed dtr
* @channelh: Channel
* @dtr: Buffer to return the next completed DTR pointer
*
* Returns the next completed dtr with out removing it from work array
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
/* LINTED */
__hal_channel_dtr_try_complete(__hal_channel_t *channel, __hal_dtr_h *dtrh)
{
vxge_assert(channel->dtr_arr);
vxge_assert(channel->compl_index < channel->length);
if (channel->dtr_arr[channel->compl_index].state ==
VXGE_HAL_CHANNEL_DTR_POSTED)
*dtrh = channel->dtr_arr[channel->compl_index].dtr;
else
*dtrh = NULL;
}
/*
* __hal_channel_dtr_complete - Removes next completed dtr from the work array
* @channelh: Channel
*
* Removes the next completed dtr from work array
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
/* LINTED */
__hal_channel_dtr_complete(__hal_channel_t *channel)
{
channel->dtr_arr[channel->compl_index].state =
VXGE_HAL_CHANNEL_DTR_COMPLETED;
if (++channel->compl_index == channel->length)
channel->compl_index = 0;
channel->stats->total_compl_cnt++;
}
/*
* __hal_channel_dtr_free - Frees a dtr
* @channelh: Channel
* @index: Index of DTR
*
* Returns the dtr to free array
*
*/
__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
/* LINTED */
__hal_channel_dtr_free(__hal_channel_t *channel, u32 dtr_index)
{
channel->dtr_arr[dtr_index].state =
VXGE_HAL_CHANNEL_DTR_FREE;
}
__EXTERN_END_DECLS
#endif /* VXGE_HAL_CHANNEL_H */

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sys/dev/vxge/vxgehal/vxgehal-common-reg.h Normal file
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@ -0,0 +1,256 @@
/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_COMMON_REGS_H
#define VXGE_HAL_COMMON_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_common_reg_t {
u8 unused00a00[0x00a00];
/* 0x00a00 */ u64 prc_status1;
#define VXGE_HAL_PRC_STATUS1_PRC_VP_QUIESCENT(n) mBIT(n)
/* 0x00a08 */ u64 rxdcm_reset_in_progress;
#define VXGE_HAL_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n)
/* 0x00a10 */ u64 replicq_flush_in_progress;
#define VXGE_HAL_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) mBIT(n)
/* 0x00a18 */ u64 rxpe_cmds_reset_in_progress;
#define VXGE_HAL_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
/* 0x00a20 */ u64 mxp_cmds_reset_in_progress;
#define VXGE_HAL_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
/* 0x00a28 */ u64 noffload_reset_in_progress;
#define VXGE_HAL_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n)
/* 0x00a30 */ u64 rd_req_in_progress;
#define VXGE_HAL_RD_REQ_IN_PROGRESS_VP(n) mBIT(n)
/* 0x00a38 */ u64 rd_req_outstanding;
#define VXGE_HAL_RD_REQ_OUTSTANDING_VP(n) mBIT(n)
/* 0x00a40 */ u64 kdfc_reset_in_progress;
#define VXGE_HAL_KDFC_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
u8 unused00b00[0x00b00 - 0x00a48];
/* 0x00b00 */ u64 one_cfg_vp;
#define VXGE_HAL_ONE_CFG_VP_RDY(n) mBIT(n)
/* 0x00b08 */ u64 one_common;
#define VXGE_HAL_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n) mBIT(n)
u8 unused00b80[0x00b80 - 0x00b10];
/* 0x00b80 */ u64 tim_int_en;
#define VXGE_HAL_TIM_INT_EN_TIM_VP(n) mBIT(n)
/* 0x00b88 */ u64 tim_set_int_en;
#define VXGE_HAL_TIM_SET_INT_EN_VP(n) mBIT(n)
/* 0x00b90 */ u64 tim_clr_int_en;
#define VXGE_HAL_TIM_CLR_INT_EN_VP(n) mBIT(n)
/* 0x00b98 */ u64 tim_mask_int_during_reset;
#define VXGE_HAL_TIM_MASK_INT_DURING_RESET_VPATH(n) mBIT(n)
/* 0x00ba0 */ u64 tim_reset_in_progress;
#define VXGE_HAL_TIM_RESET_IN_PROGRESS_TIM_VPATH(n) mBIT(n)
/* 0x00ba8 */ u64 tim_outstanding_bmap;
#define VXGE_HAL_TIM_OUTSTANDING_BMAP_TIM_VPATH(n) mBIT(n)
u8 unused00c00[0x00c00 - 0x00bb0];
/* 0x00c00 */ u64 msg_reset_in_progress;
#define VXGE_HAL_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vBIT(val, 0, 17)
/* 0x00c08 */ u64 msg_mxp_mr_ready;
#define VXGE_HAL_MSG_MXP_MR_READY_MP_BOOTED(n) mBIT(n)
/* 0x00c10 */ u64 msg_uxp_mr_ready;
#define VXGE_HAL_MSG_UXP_MR_READY_UP_BOOTED(n) mBIT(n)
/* 0x00c18 */ u64 msg_dmq_noni_rtl_prefetch;
#define VXGE_HAL_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n) mBIT(n)
/* 0x00c20 */ u64 msg_umq_rtl_bwr;
#define VXGE_HAL_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n) mBIT(n)
u8 unused00d00[0x00d00 - 0x00c28];
/* 0x00d00 */ u64 cmn_rsthdlr_cfg0;
#define VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vBIT(val, 0, 17)
/* 0x00d08 */ u64 cmn_rsthdlr_cfg1;
#define VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vBIT(val, 0, 17)
/* 0x00d10 */ u64 cmn_rsthdlr_cfg2;
#define VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vBIT(val, 0, 17)
/* 0x00d18 */ u64 cmn_rsthdlr_cfg3;
#define VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vBIT(val, 0, 17)
/* 0x00d20 */ u64 cmn_rsthdlr_cfg4;
#define VXGE_HAL_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vBIT(val, 0, 17)
u8 unused00d40[0x00d40 - 0x00d28];
/* 0x00d40 */ u64 cmn_rsthdlr_cfg8;
#define VXGE_HAL_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vBIT(val, 0, 17)
/* 0x00d48 */ u64 stats_cfg0;
#define VXGE_HAL_STATS_CFG0_STATS_ENABLE(val) vBIT(val, 0, 17)
u8 unused00da8[0x00da8 - 0x00d50];
/* 0x00da8 */ u64 clear_msix_mask_vect[4];
#define VXGE_HAL_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) vBIT(val, 0, 17)
/* 0x00dc8 */ u64 set_msix_mask_vect[4];
#define VXGE_HAL_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vBIT(val, 0, 17)
/* 0x00de8 */ u64 clear_msix_mask_all_vect;
#define VXGE_HAL_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val)\
vBIT(val, 0, 17)
/* 0x00df0 */ u64 set_msix_mask_all_vect;
#define VXGE_HAL_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val)\
vBIT(val, 0, 17)
/* 0x00df8 */ u64 mask_vector[4];
#define VXGE_HAL_MASK_VECTOR_MASK_VECTOR(val) vBIT(val, 0, 17)
/* 0x00e18 */ u64 msix_pending_vector[4];
#define VXGE_HAL_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) vBIT(val, 0, 17)
/* 0x00e38 */ u64 clr_msix_one_shot_vec[4];
#define VXGE_HAL_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val)\
vBIT(val, 0, 17)
/* 0x00e58 */ u64 titan_asic_id;
#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vBIT(val, 0, 16)
#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vBIT(val, 48, 8)
#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vBIT(val, 56, 8)
/* 0x00e60 */ u64 titan_general_int_status;
#define VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT mBIT(0)
#define VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT mBIT(1)
#define VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT mBIT(2)
#define VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val)\
vBIT(val, 3, 17)
u8 unused00e70[0x00e70 - 0x00e68];
/* 0x00e70 */ u64 titan_mask_all_int;
#define VXGE_HAL_TITAN_MASK_ALL_INT_ALARM mBIT(7)
#define VXGE_HAL_TITAN_MASK_ALL_INT_TRAFFIC mBIT(15)
u8 unused00e80[0x00e80 - 0x00e78];
/* 0x00e80 */ u64 tim_int_status0;
#define VXGE_HAL_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vBIT(val, 0, 64)
/* 0x00e88 */ u64 tim_int_mask0;
#define VXGE_HAL_TIM_INT_MASK0_TIM_INT_MASK0(val) vBIT(val, 0, 64)
/* 0x00e90 */ u64 tim_int_status1;
#define VXGE_HAL_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vBIT(val, 0, 4)
/* 0x00e98 */ u64 tim_int_mask1;
#define VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(val) vBIT(val, 0, 4)
/* 0x00ea0 */ u64 rti_int_status;
#define VXGE_HAL_RTI_INT_STATUS_RTI_INT_STATUS(val) vBIT(val, 0, 17)
/* 0x00ea8 */ u64 rti_int_mask;
#define VXGE_HAL_RTI_INT_MASK_RTI_INT_MASK(val) vBIT(val, 0, 17)
/* 0x00eb0 */ u64 adapter_status;
#define VXGE_HAL_ADAPTER_STATUS_RTDMA_RTDMA_READY mBIT(0)
#define VXGE_HAL_ADAPTER_STATUS_WRDMA_WRDMA_READY mBIT(1)
#define VXGE_HAL_ADAPTER_STATUS_KDFC_KDFC_READY mBIT(2)
#define VXGE_HAL_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY mBIT(3)
#define VXGE_HAL_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT mBIT(4)
#define VXGE_HAL_ADAPTER_STATUS_XGMAC_NETWORK_FAULT mBIT(5)
#define VXGE_HAL_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT mBIT(6)
#define VXGE_HAL_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY mBIT(7)
#define VXGE_HAL_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY mBIT(8)
#define VXGE_HAL_ADAPTER_STATUS_RIC_RIC_RUNNING mBIT(9)
#define VXGE_HAL_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK mBIT(10)
#define VXGE_HAL_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK mBIT(11)
#define VXGE_HAL_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK mBIT(12)
#define VXGE_HAL_ADAPTER_STATUS_PCC_PCC_IDLE(val) vBIT(val, 24, 8)
#define VXGE_HAL_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vBIT(val, 44, 8)
/* 0x00eb8 */ u64 gen_ctrl;
#define VXGE_HAL_GEN_CTRL_SPI_MRPCIM_WR_DIS mBIT(0)
#define VXGE_HAL_GEN_CTRL_SPI_MRPCIM_RD_DIS mBIT(1)
#define VXGE_HAL_GEN_CTRL_SPI_SRPCIM_WR_DIS mBIT(2)
#define VXGE_HAL_GEN_CTRL_SPI_SRPCIM_RD_DIS mBIT(3)
#define VXGE_HAL_GEN_CTRL_SPI_DEBUG_DIS mBIT(4)
#define VXGE_HAL_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS mBIT(5)
#define VXGE_HAL_GEN_CTRL_SPI_NOT_USED(val) vBIT(val, 6, 4)
u8 unused00ed0[0x00ed0 - 0x00ec0];
/* 0x00ed0 */ u64 adapter_ready;
#define VXGE_HAL_ADAPTER_READY_ADAPTER_READY mBIT(63)
/* 0x00ed8 */ u64 outstanding_read;
#define VXGE_HAL_OUTSTANDING_READ_OUTSTANDING_READ(val) vBIT(val, 0, 17)
/* 0x00ee0 */ u64 vpath_rst_in_prog;
#define VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vBIT(val, 0, 17)
/* 0x00ee8 */ u64 vpath_reg_modified;
#define VXGE_HAL_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vBIT(val, 0, 17)
u8 unused00f40[0x00f40 - 0x00ef0];
/* 0x00f40 */ u64 qcc_reset_in_progress;
#define VXGE_HAL_QCC_RESET_IN_PROGRESS_QCC_VPATH(n) mBIT(n)
u8 unused00fc0[0x00fc0 - 0x00f48];
/* 0x00fc0 */ u64 cp_reset_in_progress;
#define VXGE_HAL_CP_RESET_IN_PROGRESS_CP_VPATH(n) mBIT(n)
u8 unused01000[0x01000 - 0x00fc8];
/* 0x01000 */ u64 h2l_reset_in_progress;
#define VXGE_HAL_H2L_RESET_IN_PROGRESS_H2L_VPATH(n) mBIT(n)
u8 unused01080[0x01080 - 0x01008];
/* 0x01080 */ u64 xgmac_ready;
#define VXGE_HAL_XGMAC_READY_XMACJ_READY(val) vBIT(val, 0, 17)
u8 unused010c0[0x010c0 - 0x01088];
/* 0x010c0 */ u64 fbif_ready;
#define VXGE_HAL_FBIF_READY_FAU_READY(val) vBIT(val, 0, 17)
u8 unused01100[0x01100 - 0x010c8];
/* 0x01100 */ u64 vplane_assignments;
#define VXGE_HAL_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vBIT(val, 3, 5)
/* 0x01108 */ u64 vpath_assignments;
#define VXGE_HAL_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vBIT(val, 0, 17)
/* 0x01110 */ u64 resource_assignments;
#define VXGE_HAL_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) vBIT(val, 0, 17)
/* 0x01118 */ u64 host_type_assignments;
#define VXGE_HAL_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val)\
vBIT(val, 5, 3)
/* 0x01120 */ u64 debug_assignments;
#define VXGE_HAL_DEBUG_ASSIGNMENTS_VHLABEL(val) vBIT(val, 3, 5)
#define VXGE_HAL_DEBUG_ASSIGNMENTS_VPLANE(val) vBIT(val, 11, 5)
#define VXGE_HAL_DEBUG_ASSIGNMENTS_FUNC(val) vBIT(val, 19, 5)
/* 0x01128 */ u64 max_resource_assignments;
#define VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) vBIT(val, 3, 5)
#define VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) vBIT(val, 11, 5)
/* 0x01130 */ u64 pf_vpath_assignments;
#define VXGE_HAL_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) vBIT(val, 0, 17)
u8 unused01200[0x01200 - 0x01138];
/* 0x01200 */ u64 rts_access_icmp;
#define VXGE_HAL_RTS_ACCESS_ICMP_EN(val) vBIT(val, 0, 17)
/* 0x01208 */ u64 rts_access_tcpsyn;
#define VXGE_HAL_RTS_ACCESS_TCPSYN_EN(val) vBIT(val, 0, 17)
/* 0x01210 */ u64 rts_access_zl4pyld;
#define VXGE_HAL_RTS_ACCESS_ZL4PYLD_EN(val) vBIT(val, 0, 17)
/* 0x01218 */ u64 rts_access_l4prtcl_tcp;
#define VXGE_HAL_RTS_ACCESS_L4PRTCL_TCP_EN(val) vBIT(val, 0, 17)
/* 0x01220 */ u64 rts_access_l4prtcl_udp;
#define VXGE_HAL_RTS_ACCESS_L4PRTCL_UDP_EN(val) vBIT(val, 0, 17)
/* 0x01228 */ u64 rts_access_l4prtcl_flex;
#define VXGE_HAL_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vBIT(val, 0, 17)
/* 0x01230 */ u64 rts_access_ipfrag;
#define VXGE_HAL_RTS_ACCESS_IPFRAG_EN(val) vBIT(val, 0, 17)
u8 unused01238[0x01248 - 0x01238];
} vxge_hal_common_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_COMMON_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef XGEHAL_CONFIG_PRIV_H
#define XGEHAL_CONFIG_PRIV_H
__EXTERN_BEGIN_DECLS
vxge_hal_status_e
vxge_hal_driver_config_check(vxge_hal_driver_config_t *config);
vxge_hal_status_e
__hal_device_mac_config_check(vxge_hal_mac_config_t *mac_config);
vxge_hal_status_e
__hal_vpath_qos_config_check(vxge_hal_vpath_qos_config_t *config);
vxge_hal_status_e
__hal_mrpcim_config_check(vxge_hal_mrpcim_config_t *config);
vxge_hal_status_e
__hal_device_ring_config_check(vxge_hal_ring_config_t *ring_config);
vxge_hal_status_e
__hal_device_fifo_config_check(vxge_hal_fifo_config_t *fifo_config);
vxge_hal_status_e
__hal_device_lag_config_check(vxge_hal_lag_config_t *lag_config);
vxge_hal_status_e
__hal_device_lag_port_config_check(vxge_hal_lag_port_config_t *port_config);
vxge_hal_status_e
__hal_device_lag_aggr_config_check(vxge_hal_lag_aggr_config_t *aggr_config);
vxge_hal_status_e
__hal_device_lag_la_config_check(vxge_hal_lag_la_config_t *la_config);
vxge_hal_status_e
__hal_device_lag_ap_config_check(vxge_hal_lag_ap_config_t *ap_config);
vxge_hal_status_e
__hal_device_lag_sl_config_check(vxge_hal_lag_sl_config_t *sl_config);
vxge_hal_status_e
__hal_device_lag_lacp_config_check(vxge_hal_lag_lacp_config_t *lacp_config);
vxge_hal_status_e
__hal_device_wire_port_config_check(vxge_hal_wire_port_config_t *port_config);
vxge_hal_status_e
__hal_device_switch_port_config_check(
vxge_hal_switch_port_config_t *port_config);
vxge_hal_status_e
__hal_device_tim_intr_config_check(vxge_hal_tim_intr_config_t *tim_intr_config);
vxge_hal_status_e
__hal_device_vpath_config_check(vxge_hal_vp_config_t *vp_config);
vxge_hal_status_e
__hal_device_config_check(vxge_hal_device_config_t *new_config);
__EXTERN_END_DECLS
#endif /* XGEHAL_CONFIG_PRIV_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_DEBUG_H
#define VXGE_HAL_DEBUG_H
__EXTERN_BEGIN_DECLS
#define D_ERR_MASK ((__hal_device_t *)hldev)->d_err_mask
#define D_INFO_MASK ((__hal_device_t *)hldev)->d_info_mask
#define D_TRACE_MASK ((__hal_device_t *)hldev)->d_trace_mask
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
#define vxge_hal_debug_printf vxge_os_vasprintf
#else
#define vxge_hal_debug_printf vxge_os_vaprintf
#endif
#ifndef VXGE_DEBUG_INLINE_FUNCTIONS
#define vxge_hal_debug_noop(fmt, ...)
#else
static inline void
vxge_hal_debug_noop(
char *fmt, ...)
{
}
#endif
#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_driver \
if (g_debug_level & VXGE_ERR) vxge_hal_debug_printf
#define vxge_hal_info_log_driver \
if (g_debug_level & VXGE_INFO) vxge_hal_debug_printf
#define vxge_hal_trace_log_driver \
if (g_debug_level & VXGE_TRACE) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_driver vxge_hal_debug_noop
#define vxge_hal_info_log_driver vxge_hal_debug_noop
#define vxge_hal_trace_log_driver vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_DEVICE & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_device \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
#define vxge_hal_info_log_device \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
#define vxge_hal_trace_log_device \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_device vxge_hal_debug_noop
#define vxge_hal_info_log_device vxge_hal_debug_noop
#define vxge_hal_trace_log_device vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_DEVICE_IRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_device_irq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_device_irq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_device_irq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_device_irq vxge_hal_debug_noop
#define vxge_hal_info_log_device_irq vxge_hal_debug_noop
#define vxge_hal_trace_log_device_irq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_VPATH & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_vpath \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
#define vxge_hal_info_log_vpath \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
#define vxge_hal_trace_log_vpath \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_vpath vxge_hal_debug_noop
#define vxge_hal_info_log_vpath vxge_hal_debug_noop
#define vxge_hal_trace_log_vpath vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_VPATH_IRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_vpath_irq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_vpath_irq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_vpath_irq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_vpath_irq vxge_hal_debug_noop
#define vxge_hal_info_log_vpath_irq vxge_hal_debug_noop
#define vxge_hal_trace_log_vpath_irq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_CONFIG & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_config \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
#define vxge_hal_info_log_config \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
#define vxge_hal_trace_log_config \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_config vxge_hal_debug_noop
#define vxge_hal_info_log_config vxge_hal_debug_noop
#define vxge_hal_trace_log_config vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_MM & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_mm \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
#define vxge_hal_info_log_mm \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
#define vxge_hal_trace_log_mm \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_mm vxge_hal_debug_noop
#define vxge_hal_info_log_mm vxge_hal_debug_noop
#define vxge_hal_trace_log_mm vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_pool \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
#define vxge_hal_info_log_pool \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
#define vxge_hal_trace_log_pool \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_pool vxge_hal_debug_noop
#define vxge_hal_info_log_pool vxge_hal_debug_noop
#define vxge_hal_trace_log_pool vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_QUEUE & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_queue \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
#define vxge_hal_info_log_queue \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
#define vxge_hal_trace_log_queue \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_queue vxge_hal_debug_noop
#define vxge_hal_info_log_queue vxge_hal_debug_noop
#define vxge_hal_trace_log_queue vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_BITMAP & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_bitmap \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
#define vxge_hal_info_log_bitmap \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
#define vxge_hal_trace_log_bitmap \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_bitmap vxge_hal_debug_noop
#define vxge_hal_info_log_bitmap vxge_hal_debug_noop
#define vxge_hal_trace_log_bitmap vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_channel \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
#define vxge_hal_info_log_channel \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
#define vxge_hal_trace_log_channel \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_channel vxge_hal_debug_noop
#define vxge_hal_info_log_channel vxge_hal_debug_noop
#define vxge_hal_trace_log_channel vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_FIFO & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_fifo \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
#define vxge_hal_info_log_fifo \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
#define vxge_hal_trace_log_fifo \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_fifo vxge_hal_debug_noop
#define vxge_hal_info_log_fifo vxge_hal_debug_noop
#define vxge_hal_trace_log_fifo vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_RING & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_ring \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
#define vxge_hal_info_log_ring \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
#define vxge_hal_trace_log_ring \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_ring vxge_hal_debug_noop
#define vxge_hal_info_log_ring vxge_hal_debug_noop
#define vxge_hal_trace_log_ring vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_DMQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_dmq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
#define vxge_hal_info_log_dmq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_dmq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_dmq vxge_hal_debug_noop
#define vxge_hal_info_log_dmq vxge_hal_debug_noop
#define vxge_hal_trace_log_dmq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_UMQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_umq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
#define vxge_hal_info_log_umq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_umq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_umq vxge_hal_debug_noop
#define vxge_hal_info_log_umq vxge_hal_debug_noop
#define vxge_hal_trace_log_umq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_sq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
#define vxge_hal_info_log_sq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_sq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_sq vxge_hal_debug_noop
#define vxge_hal_info_log_sq vxge_hal_debug_noop
#define vxge_hal_trace_log_sq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_srq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_srq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_srq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_srq vxge_hal_debug_noop
#define vxge_hal_info_log_srq vxge_hal_debug_noop
#define vxge_hal_trace_log_srq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_CQRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_cqrq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_cqrq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_cqrq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_cqrq vxge_hal_debug_noop
#define vxge_hal_info_log_cqrq vxge_hal_debug_noop
#define vxge_hal_trace_log_cqrq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_NCE & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_nce \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
#define vxge_hal_info_log_nce \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
#define vxge_hal_trace_log_nce \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_nce vxge_hal_debug_noop
#define vxge_hal_info_log_nce vxge_hal_debug_noop
#define vxge_hal_trace_log_nce vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_STAG & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_stag \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
#define vxge_hal_info_log_stag \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
#define vxge_hal_trace_log_stag \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_stag vxge_hal_debug_noop
#define vxge_hal_info_log_stag vxge_hal_debug_noop
#define vxge_hal_trace_log_stag vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_TCP & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_tcp \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
#define vxge_hal_info_log_tcp \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
#define vxge_hal_trace_log_tcp \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_tcp vxge_hal_debug_noop
#define vxge_hal_info_log_tcp vxge_hal_debug_noop
#define vxge_hal_trace_log_tcp vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_LRO & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_lro \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
#define vxge_hal_info_log_lro \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
#define vxge_hal_trace_log_lro \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_lro vxge_hal_debug_noop
#define vxge_hal_info_log_lro vxge_hal_debug_noop
#define vxge_hal_trace_log_lro vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SPDM & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_spdm \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
#define vxge_hal_info_log_spdm \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
#define vxge_hal_trace_log_spdm \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_spdm vxge_hal_debug_noop
#define vxge_hal_info_log_spdm vxge_hal_debug_noop
#define vxge_hal_trace_log_spdm vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SESSION & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_session \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
#define vxge_hal_info_log_session \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
#define vxge_hal_trace_log_session \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_session vxge_hal_debug_noop
#define vxge_hal_info_log_session vxge_hal_debug_noop
#define vxge_hal_trace_log_session vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_STATS & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_stats \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
#define vxge_hal_info_log_stats \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
#define vxge_hal_trace_log_stats \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_stats vxge_hal_debug_noop
#define vxge_hal_info_log_stats vxge_hal_debug_noop
#define vxge_hal_trace_log_stats vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_MRPCIM & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_mrpcim \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
#define vxge_hal_info_log_mrpcim \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
#define vxge_hal_trace_log_mrpcim \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_mrpcim vxge_hal_debug_noop
#define vxge_hal_info_log_mrpcim vxge_hal_debug_noop
#define vxge_hal_trace_log_mrpcim vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_MRPCIM_IRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_mrpcim_irq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_mrpcim_irq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_mrpcim_irq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_mrpcim_irq vxge_hal_debug_noop
#define vxge_hal_info_log_mrpcim_irq vxge_hal_debug_noop
#define vxge_hal_trace_log_mrpcim_irq vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SRPCIM & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_srpcim \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
#define vxge_hal_info_log_srpcim \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
#define vxge_hal_trace_log_srpcim \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_srpcim vxge_hal_debug_noop
#define vxge_hal_info_log_srpcim vxge_hal_debug_noop
#define vxge_hal_trace_log_srpcim vxge_hal_debug_noop
#endif
#if (VXGE_COMPONENT_HAL_SRPCIM_IRQ & VXGE_DEBUG_MODULE_MASK)
#define vxge_hal_err_log_srpcim_irq \
if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
#define vxge_hal_info_log_srpcim_irq \
if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
#define vxge_hal_trace_log_srpcim_irq \
if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
#else
#define vxge_hal_err_log_srpcim_irq vxge_hal_debug_noop
#define vxge_hal_info_log_srpcim_irq vxge_hal_debug_noop
#define vxge_hal_trace_log_srpcim_irq vxge_hal_debug_noop
#endif
__EXTERN_END_DECLS
#endif /* VXGE_HAL_DEBUG_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_DEVICE_H
#define VXGE_HAL_DEVICE_H
__EXTERN_BEGIN_DECLS
struct __hal_mrpcim_t;
struct __hal_srpcim_t;
/*
* vxge_hal_vpd_data_t
*
* Represents vpd capabilty structure
*/
typedef struct vxge_hal_vpd_data_t {
u8 product_name[VXGE_HAL_VPD_LEN];
u8 serial_num[VXGE_HAL_VPD_LEN];
} vxge_hal_vpd_data_t;
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
/*
* __hal_tracebuf_t
*
* HAL trace buffer object.
*/
typedef struct __hal_tracebuf_t {
u8 *data;
u64 wrapped_count;
volatile u32 offset;
u32 size;
} __hal_tracebuf_t;
#endif
/*
* __hal_msix_map_t
*
* HAL msix to vpath map.
*/
typedef struct __hal_msix_map_t {
u32 vp_id;
u32 int_num;
} __hal_msix_map_t;
/*
* __hal_device_t
*
* HAL device object. Represents X3100.
*/
typedef struct __hal_device_t {
vxge_hal_device_t header;
u32 host_type;
u32 vh_id;
u32 func_id;
u32 srpcim_id;
u32 access_rights;
#define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1
#define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
#define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
u32 ifmsg_seqno;
u32 manager_up;
vxge_hal_pci_config_t pci_config_space;
vxge_hal_pci_config_t pci_config_space_bios;
vxge_hal_pci_caps_offset_t pci_caps;
vxge_hal_pci_e_caps_offset_t pci_e_caps;
vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps;
vxge_hal_legacy_reg_t *legacy_reg;
vxge_hal_toc_reg_t *toc_reg;
vxge_hal_common_reg_t *common_reg;
vxge_hal_memrepair_reg_t *memrepair_reg;
vxge_hal_pcicfgmgmt_reg_t
*pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES];
vxge_hal_mrpcim_reg_t *mrpcim_reg;
vxge_hal_srpcim_reg_t
*srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES];
vxge_hal_vpmgmt_reg_t
*vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES];
vxge_hal_vpath_reg_t
*vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES];
u8 *kdfc;
u8 *usdc;
__hal_virtualpath_t
virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS];
u64 vpath_assignments;
u64 vpaths_deployed;
u32 first_vp_id;
u64 tim_int_mask0[4];
u32 tim_int_mask1[4];
__hal_msix_map_t
msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX];
struct __hal_srpcim_t *srpcim;
struct __hal_mrpcim_t *mrpcim;
__hal_blockpool_t block_pool;
vxge_list_t pending_channel_list;
spinlock_t pending_channel_lock;
vxge_hal_device_stats_t stats;
volatile u32 msix_enabled;
volatile u32 hw_is_initialized;
volatile int device_resetting;
volatile int is_promisc;
int tti_enabled;
spinlock_t titan_post_lock;
u32 mtu_first_time_set;
char *dump_buf;
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
__hal_tracebuf_t trace_buf;
#endif
volatile u32 in_poll;
u32 d_err_mask;
u32 d_info_mask;
u32 d_trace_mask;
} __hal_device_t;
/*
* I2C device id. Used in I2C control register for accessing EEPROM device
* memory.
*/
#define VXGE_DEV_ID 5
#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \
((__hal_device_t *)hldev)->manager_up = \
__hal_ifmsg_is_manager_up(wmsg); \
}
#define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \
((vxge_hal_device_t *)hldev)->link_state = ls; \
}
#define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \
((vxge_hal_device_t *)hldev)->data_rate = dr; \
}
#define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \
if (i < 16) { \
((__hal_device_t *)hldev)->tim_int_mask0[0] |= \
vBIT(0x8, (i*4), 4); \
((__hal_device_t *)hldev)->tim_int_mask0[1] |= \
vBIT(0x4, (i*4), 4); \
((__hal_device_t *)hldev)->tim_int_mask0[3] |= \
vBIT(0x1, (i*4), 4); \
} else { \
((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \
((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \
((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \
} \
}
#define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \
if (i < 16) { \
((__hal_device_t *)hldev)->tim_int_mask0[0] &= \
~vBIT(0x8, (i*4), 4); \
((__hal_device_t *)hldev)->tim_int_mask0[1] &= \
~vBIT(0x4, (i*4), 4); \
((__hal_device_t *)hldev)->tim_int_mask0[3] &= \
~vBIT(0x1, (i*4), 4); \
} else { \
((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \
((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \
((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \
} \
}
/* ========================== PRIVATE API ================================= */
void
vxge_hal_pio_mem_write32_upper(pci_dev_h pdev,
pci_reg_h regh,
u32 val,
void *addr);
void
vxge_hal_pio_mem_write32_lower(pci_dev_h pdev,
pci_reg_h regh,
u32 val,
void *addr);
void
__hal_device_event_queued(void *data,
u32 event_type);
void
__hal_device_pci_caps_list_process(__hal_device_t *hldev);
void
__hal_device_pci_e_init(__hal_device_t *hldev);
vxge_hal_status_e
vxge_hal_device_register_poll(pci_dev_h pdev,
pci_reg_h regh,
u64 *reg,
u32 op,
u64 mask,
u32 max_millis);
vxge_hal_status_e
__hal_device_register_stall(pci_dev_h pdev,
pci_reg_h regh,
u64 *reg,
u32 op,
u64 mask,
u32 max_millis);
vxge_hal_status_e
__hal_device_reg_addr_get(__hal_device_t *hldev);
void
__hal_device_id_get(__hal_device_t *hldev);
u32
__hal_device_access_rights_get(u32 host_type, u32 func_id);
void
__hal_device_host_info_get(__hal_device_t *hldev);
vxge_hal_status_e
__hal_device_hw_initialize(__hal_device_t *hldev);
vxge_hal_status_e
__hal_device_reset(__hal_device_t *hldev);
vxge_hal_status_e
__hal_device_handle_link_up_ind(__hal_device_t *hldev);
vxge_hal_status_e
__hal_device_handle_link_down_ind(__hal_device_t *hldev);
void
__hal_device_handle_error(
__hal_device_t *hldev,
u32 vp_id,
vxge_hal_event_e type);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_DEVICE_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* __hal_non_offload_db_post - Post non offload doorbell
*
* @vpath_handle: vpath handle
* @txdl_ptr: The starting location of the TxDL in host memory
* @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
* @no_snoop: No snoop flags
*
* This function posts a non-offload doorbell to doorbell FIFO
*
*/
void
__hal_non_offload_db_post(vxge_hal_vpath_h vpath_handle,
u64 txdl_ptr,
u32 num_txds,
u32 no_snoop)
{
u64 *db_ptr;
__hal_device_t *hldev;
__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
vxge_assert((vpath_handle != NULL) && (txdl_ptr != 0));
hldev = (__hal_device_t *) vp->vpath->hldev;
vxge_hal_trace_log_fifo("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_fifo(
"vpath_handle = 0x"VXGE_OS_STXFMT", txdl_ptr = 0x"VXGE_OS_STXFMT
", num_txds = %d, no_snoop = %d", (ptr_t) vpath_handle,
(ptr_t) txdl_ptr, num_txds, no_snoop);
db_ptr = &vp->vpath->nofl_db->control_0;
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_NODBW_TYPE(VXGE_HAL_NODBW_TYPE_NODBW) |
VXGE_HAL_NODBW_LAST_TXD_NUMBER(num_txds) |
VXGE_HAL_NODBW_GET_NO_SNOOP(no_snoop),
db_ptr++);
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
txdl_ptr,
db_ptr);
vxge_hal_trace_log_fifo("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_non_offload_db_reset - Reset non offload doorbell fifo
*
* @vpath_handle: vpath handle
*
* This function resets non-offload doorbell FIFO
*
*/
vxge_hal_status_e
__hal_non_offload_db_reset(vxge_hal_vpath_h vpath_handle)
{
vxge_hal_status_e status;
__hal_device_t *hldev;
__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
vxge_assert(vpath_handle != NULL);
hldev = (__hal_device_t *) vp->vpath->hldev;
vxge_hal_trace_log_fifo("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_fifo(
"vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(
1 << (16 - vp->vpath->vp_id)),
&vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg2);
vxge_os_wmb();
status = vxge_hal_device_register_poll(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
&vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg2, 0,
(u64) VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(
1 << (16 - vp->vpath->vp_id)),
VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
vxge_hal_trace_log_fifo("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (status);
}
/*
* __hal_rxd_db_post - Post rxd doorbell
*
* @vpath_handle: vpath handle
* @num_bytes: The number of bytes
*
* This function posts a rxd doorbell
*
*/
void
__hal_rxd_db_post(vxge_hal_vpath_h vpath_handle,
u32 num_bytes)
{
__hal_device_t *hldev;
__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
vxge_assert(vpath_handle != NULL);
hldev = (__hal_device_t *) vp->vpath->hldev;
vxge_hal_trace_log_ring("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_fifo(
"vpath_handle = 0x"VXGE_OS_STXFMT", num_bytes = %d",
(ptr_t) vpath_handle, num_bytes);
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT((num_bytes >> 3)),
&vp->vpath->vp_reg->prc_rxd_doorbell);
vxge_hal_trace_log_ring("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_message_db_post - Post message doorbell
*
* @vpath_handle: VPATH handle
* @num_msg_bytes: The number of new message bytes made available
* by this doorbell entry.
* @immed_msg: Immediate message to be sent
* @immed_msg_len: Immediate message length
*
* This function posts a message doorbell to doorbell FIFO
*
*/
void
__hal_message_db_post(vxge_hal_vpath_h vpath_handle,
u32 num_msg_bytes,
u8 *immed_msg,
u32 immed_msg_len)
{
u32 i;
u64 *db_ptr;
__hal_device_t *hldev;
__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
vxge_assert((vpath_handle != NULL) && (num_msg_bytes != 0));
hldev = (__hal_device_t *) vp->vpath->hldev;
vxge_hal_trace_log_dmq("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_dmq("vpath_handle = 0x"VXGE_OS_STXFMT", "
"num_msg_bytes = %d, immed_msg = 0x"VXGE_OS_STXFMT", "
"immed_msg_len = %d", (ptr_t) vpath_handle, num_msg_bytes,
(ptr_t) immed_msg, immed_msg_len);
db_ptr = &vp->vpath->msg_db->control_0;
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_MDBW_TYPE(VXGE_HAL_MDBW_TYPE_MDBW) |
VXGE_HAL_MDBW_MESSAGE_BYTE_COUNT(num_msg_bytes),
db_ptr++);
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_MDBW_IMMEDIATE_BYTE_COUNT(immed_msg_len),
db_ptr++);
for (i = 0; i < immed_msg_len / 8; i++) {
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
*((u64 *) ((void *)&immed_msg[i * 8])),
db_ptr++);
}
vxge_hal_trace_log_dmq("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_message_db_reset - Reset message doorbell fifo
*
* @vpath_handle: vpath handle
*
* This function resets message doorbell FIFO
*
*/
vxge_hal_status_e
__hal_message_db_reset(vxge_hal_vpath_h vpath_handle)
{
vxge_hal_status_e status;
__hal_device_t *hldev;
__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
vxge_assert(vpath_handle != NULL);
hldev = (__hal_device_t *) vp->vpath->hldev;
vxge_hal_trace_log_dmq("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_dmq("vpath_handle = 0x"VXGE_OS_STXFMT,
(ptr_t) vpath_handle);
vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(
1 << (16 - vp->vpath->vp_id)),
&vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg3);
vxge_os_wmb();
status = vxge_hal_device_register_poll(vp->vpath->hldev->header.pdev,
vp->vpath->hldev->header.regh0,
&vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg3, 0,
(u64) VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(
1 << (16 - vp->vpath->vp_id)),
VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
vxge_hal_trace_log_dmq("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (status);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_DOOR_BELLS_H
#define VXGE_HAL_DOOR_BELLS_H
__EXTERN_BEGIN_DECLS
/*
* struct __hal_non_offload_db_wrapper_t - Non-offload Doorbell Wrapper
* @control_0: Bits 0 to 7 - Doorbell type.
* Bits 8 to 31 - Reserved.
* Bits 32 to 39 - The highest TxD in this TxDL.
* Bits 40 to 47 - Reserved.
* Bits 48 to 55 - Reserved.
* Bits 56 to 63 - No snoop flags.
* @txdl_ptr: The starting location of the TxDL in host memory.
*
* Created by the host and written to the adapter via PIO to a Kernel Doorbell
* FIFO. All non-offload doorbell wrapper fields must be written by the host as
* part of a doorbell write. Consumed by the adapter but is not written by the
* adapter.
*/
typedef __vxge_os_attr_cacheline_aligned struct __hal_non_offload_db_wrapper_t {
u64 control_0;
#define VXGE_HAL_NODBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0)
#define VXGE_HAL_NODBW_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_NODBW_TYPE_NODBW 0
#define VXGE_HAL_NODBW_GET_LAST_TXD_NUMBER(ctrl0) bVAL8(ctrl0, 32)
#define VXGE_HAL_NODBW_LAST_TXD_NUMBER(val) vBIT(val, 32, 8)
#define VXGE_HAL_NODBW_GET_NO_SNOOP(ctrl0) bVAL8(ctrl0, 56)
#define VXGE_HAL_NODBW_LIST_NO_SNOOP(val) vBIT(val, 56, 8)
#define VXGE_HAL_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2
#define VXGE_HAL_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1
u64 txdl_ptr;
} __hal_non_offload_db_wrapper_t;
/*
* struct __hal_offload_db_wrapper_t - Tx-Offload Doorbell Wrapper
* @control_0: Bits 0 to 7 - Doorbell type.
* Bits 8 to 31 - Identifies the session to which this Tx
* offload doorbell applies.
* Bits 32 to 40 - Identifies the incarnation of this Session
* Number. The adapter assigns a Session Instance
* Number of 0 to a session when that Session Number
* is first used. Each subsequent assignment of that
* Session Number from the free pool causes this
* number to be incremented, with wrap eventually
* occurring from 255 back to 0.
* Bits 40 to 63 - Identifies the end of the TOWI list for
* this session to the adapter.
* @control_1: Bits 0 to 7 - Identifies what is included in this doorbell
* Bits 8 to 15 - The number of Immediate data bytes included in
* this doorbell.
* Bits 16 to 63 - Reserved.
*
* Created by the host and written to the adapter via PIO to a Kernel Doorbell
* FIFO. All Tx Offload doorbell wrapper fields must be written by the host as
* part of a doorbell write. Consumed by the adapter but is never written by the
* adapter.
*/
typedef __vxge_os_attr_cacheline_aligned struct __hal_offload_db_wrapper_t {
u64 control_0;
#define VXGE_HAL_ODBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0)
#define VXGE_HAL_ODBW_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_ODBW_TYPE_ODBW 1
#define VXGE_HAL_ODBW_GET_SESSION_NUMBER(ctrl0) bVAL24(ctrl0, 8)
#define VXGE_HAL_ODBW_SESSION_NUMBER(val) vBIT(val, 8, 24)
#define VXGE_HAL_ODBW_GET_SESSION_INST_NUMBER(ctrl0) bVAL8(ctrl0, 32)
#define VXGE_HAL_ODBW_SESSION_INST_NUMBER(val) vBIT(val, 32, 8)
#define VXGE_HAL_ODBW_GET_HIGH_TOWI_NUMBER(ctrl0) bVAL24(ctrl0, 40)
#define VXGE_HAL_ODBW_HIGH_TOWI_NUMBER(val) vBIT(val, 40, 24)
u64 control_1;
#define VXGE_HAL_ODBW_GET_ENTRY_TYPE(ctrl1) bVAL8(ctrl1, 0)
#define VXGE_HAL_ODBW_ENTRY_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_ONLY 0x0
#define VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_TOWI 0x1
#define VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_TOWI_DATA 0x2
#define VXGE_HAL_ODBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1) bVAL8(ctrl1, 8)
#define VXGE_HAL_ODBW_IMMEDIATE_BYTE_COUNT(val) vBIT(val, 8, 8)
} __hal_offload_db_wrapper_t;
/*
* struct __hal_offload_atomic_db_wrapper_t - Atomic Tx-Offload Doorbell
* Wrapper
* @control_0: Bits 0 to 7 - Doorbell type.
* Bits 8 to 31 - Identifies the session to which this Tx
* offload doorbell applies.
* Bits 32 to 40 - Identifies the incarnation of this Session
* Number. The adapter assigns a Session Instance
* Number of 0 to a session when that Session Number
* is first used. Each subsequent assignment of that
* Session Number from the free pool causes this
* number to be incremented, with wrap eventually
* occurring from 255 back to 0.
* Bits 40 to 63 - Identifies the end of the TOWI list for
* this session to the adapter.
*
* Created by the host and written to the adapter via PIO to a Kernel Doorbell
* FIFO. All Tx Offload doorbell wrapper fields must be written by the host as
* part of a doorbell write. Consumed by the adapter but is never written by the
* adapter.
*/
typedef __vxge_os_attr_cacheline_aligned
struct __hal_offload_atomic_db_wrapper_t {
u64 control_0;
#define VXGE_HAL_ODBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0)
#define VXGE_HAL_ODBW_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_ODBW_TYPE_ATOMIC 2
#define VXGE_HAL_ODBW_GET_SESSION_NUMBER(ctrl0) bVAL24(ctrl0, 8)
#define VXGE_HAL_ODBW_SESSION_NUMBER(val) vBIT(val, 8, 24)
#define VXGE_HAL_ODBW_GET_SESSION_INST_NUMBER(ctrl0) bVAL8(ctrl0, 32)
#define VXGE_HAL_ODBW_SESSION_INST_NUMBER(val) vBIT(val, 32, 8)
#define VXGE_HAL_ODBW_GET_HIGH_TOWI_NUMBER(ctrl0) bVAL24(ctrl0, 40)
#define VXGE_HAL_ODBW_HIGH_TOWI_NUMBER(val) vBIT(val, 40, 24)
} __hal_offload_atomic_db_wrapper_t;
/*
* struct __hal_messaging_db_wrapper_t - Messaging Doorbell Wrapper
* @control_0: Bits 0 to 7 - Doorbell type.
* Bits 8 to 31 - Reserved.
* Bits 32 to 63 - The number of new message bytes made available
* by this doorbell entry.
* @control_1: Bits 0 to 7 - Reserved.
* Bits 8 to 15 - The number of Immediate messaging bytes included
* in this doorbell.
* Bits 16 to 63 - Reserved.
*
* Created by the host and written to the adapter via PIO to a Kernel Doorbell
* FIFO. All message doorbell wrapper fields must be written by the host as
* part of a doorbell write. Consumed by the adapter but not written by adapter.
*/
typedef __vxge_os_attr_cacheline_aligned struct __hal_messaging_db_wrapper_t {
u64 control_0;
#define VXGE_HAL_MDBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0)
#define VXGE_HAL_MDBW_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_MDBW_TYPE_MDBW 3
#define VXGE_HAL_MDBW_GET_MESSAGE_BYTE_COUNT(ctrl0) bVAL32(ctrl0, 32)
#define VXGE_HAL_MDBW_MESSAGE_BYTE_COUNT(val) vBIT(val, 32, 32)
u64 control_1;
#define VXGE_HAL_MDBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1) bVAL8(ctrl1, 8)
#define VXGE_HAL_MDBW_IMMEDIATE_BYTE_COUNT(val) vBIT(val, 8, 8)
} __hal_messaging_db_wrapper_t;
void
__hal_non_offload_db_post(vxge_hal_vpath_h vpath_handle,
u64 txdl_ptr,
u32 num_txds,
u32 no_snoop);
void
__hal_rxd_db_post(vxge_hal_vpath_h vpath_handle,
u32 num_bytes);
vxge_hal_status_e
__hal_non_offload_db_reset(vxge_hal_vpath_h vpath_handle);
void
__hal_message_db_post(vxge_hal_vpath_h vpath_handle,
u32 num_msg_bytes,
u8 *immed_msg,
u32 immed_msg_len);
vxge_hal_status_e
__hal_message_db_reset(vxge_hal_vpath_h vpath_handle);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_DOOR_BELLS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
static __hal_driver_t g_driver;
__hal_driver_t *g_vxge_hal_driver;
#if defined(VXGE_OS_MEMORY_CHECK)
vxge_os_malloc_t g_malloc_arr[VXGE_OS_MALLOC_CNT_MAX];
u32 g_malloc_cnt;
#endif
/*
* Runtime tracing support
*/
u32 g_debug_level;
/*
* vxge_hal_driver_initialize - Initialize HAL.
* @config: HAL configuration, see vxge_hal_driver_config_t {}.
* @uld_callbacks: Upper-layer driver callbacks, e.g. link-up.
*
* HAL initialization entry point. Not to confuse with device initialization
* (note that HAL "contains" zero or more X3100 devices).
*
* Returns: VXGE_HAL_OK - success;
* VXGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid.
*
* See also: vxge_hal_device_initialize(), vxge_hal_status_e {},
* vxge_hal_uld_cbs_t {}.
*/
vxge_hal_status_e
vxge_hal_driver_initialize(
vxge_hal_driver_config_t *config,
vxge_hal_uld_cbs_t *uld_callbacks)
{
vxge_hal_status_e status;
g_vxge_hal_driver = &g_driver;
if ((status = vxge_hal_driver_config_check(config)) != VXGE_HAL_OK)
return (status);
vxge_os_memzero(g_vxge_hal_driver, sizeof(__hal_driver_t));
/* apply config */
vxge_os_memcpy(&g_vxge_hal_driver->config, config,
sizeof(vxge_hal_driver_config_t));
/* apply ULD callbacks */
vxge_os_memcpy(&g_vxge_hal_driver->uld_callbacks, uld_callbacks,
sizeof(vxge_hal_uld_cbs_t));
vxge_hal_driver_debug_set(config->level);
g_vxge_hal_driver->is_initialized = 1;
return (VXGE_HAL_OK);
}
/*
* vxge_hal_driver_terminate - Terminate HAL.
*
* HAL termination entry point.
*
* See also: vxge_hal_device_terminate().
*/
void
vxge_hal_driver_terminate(void)
{
g_vxge_hal_driver->is_initialized = 0;
g_vxge_hal_driver = NULL;
#if defined(VXGE_OS_MEMORY_CHECK)
if (TRUE) {
u32 i, leaks = 0;
vxge_os_printf("OSPAL: max g_malloc_cnt %d\n", g_malloc_cnt);
for (i = 0; i < g_malloc_cnt; i++) {
if (g_malloc_arr[i].ptr != NULL) {
vxge_os_printf("OSPAL: memory leak detected at "
"%s:%lu:"VXGE_OS_LLXFMT":%lu\n",
g_malloc_arr[i].file,
g_malloc_arr[i].line,
(u64) (ptr_t) g_malloc_arr[i].ptr,
g_malloc_arr[i].size);
leaks++;
}
}
if (leaks) {
vxge_os_printf("OSPAL: %d memory leaks detected\n",
leaks);
} else {
vxge_os_println("OSPAL: no memory leaks detected\n");
}
}
#endif
}
/*
* vxge_hal_driver_debug_set - Set the debug module, level and timestamp
* @level: Debug level as defined in enum vxge_debug_level_e
*
* This routine is used to dynamically change the debug output
*/
void
vxge_hal_driver_debug_set(
vxge_debug_level_e level)
{
g_vxge_hal_driver->debug_level = level;
g_debug_level = 0;
switch (level) {
/* FALLTHRU */
case VXGE_TRACE:
g_debug_level |= VXGE_TRACE;
/* FALLTHRU */
case VXGE_INFO:
g_debug_level |= VXGE_INFO;
/* FALLTHRU */
case VXGE_ERR:
g_debug_level |= VXGE_ERR;
/* FALLTHRU */
default:
break;
}
}
/*
* vxge_hal_driver_debug_get - Get the debug level
*
* This routine returns the current debug level set
*/
u32
vxge_hal_driver_debug_get(void)
{
return (g_vxge_hal_driver->debug_level);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_DRIVER_H
#define VXGE_HAL_DRIVER_H
__EXTERN_BEGIN_DECLS
/* maximum number of events consumed in a syncle poll() cycle */
#define VXGE_HAL_DRIVER_QUEUE_CONSUME_MAX 5
/*
* struct __hal_driver_t - Represents HAL object for driver.
* @config: HAL configuration.
* @devices: List of all PCI-enumerated X3100 devices in the system.
* A single vxge_hal_driver_t instance contains zero or more
* X3100 devices.
* @devices_lock: Lock to protect %devices when inserting/removing.
* @is_initialized: True if HAL is initialized; false otherwise.
* @uld_callbacks: Upper-layer driver callbacks. See vxge_hal_uld_cbs_t {}.
* @debug_module_mask: 32bit mask that defines which components of the
* driver are to be traced. The trace-able components are listed in
* xgehal_debug.h:
* @debug_level: See vxge_debug_level_e {}.
*
* HAL (driver) object. There is a single instance of this structure per HAL.
*/
typedef struct __hal_driver_t {
vxge_hal_driver_config_t config;
int is_initialized;
vxge_hal_uld_cbs_t uld_callbacks;
u32 debug_level;
} __hal_driver_t;
extern __hal_driver_t *g_vxge_hal_driver;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_DRIVER_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_FIFO_H
#define VXGE_HAL_FIFO_H
__EXTERN_BEGIN_DECLS
/*
* struct __hal_fifo_t - Fifo.
* @channel: Channel "base" of this fifo, the common part of all HAL
* channels.
* @mempool: Memory pool, from which descriptors get allocated.
* @config: Fifo configuration, part of device configuration
* (see vxge_hal_device_config_t {}).
* @interrupt_type: Interrupt type to be used
* @no_snoop_bits: See vxge_hal_fifo_config_t {}.
* @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
* bytes. Setting @memblock_size to page size ensures
* by-page allocation of descriptors. 128K bytes is the
* maximum supported block size.
* @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
* on TxDL please refer to X3100 UG.
* @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
* per-TxDL HAL private space (__hal_fifo_txdl_priv_t).
* @txdl_priv_size: Per-TxDL space reserved for HAL and ULD
* @per_txdl_space: Per txdl private space for the ULD
* @txdlblock_priv_size: Total private space per TXDL memory block
* @align_size: Cache alignment size
* @callback: Fifo completion callback. HAL invokes the callback when there
* are new completions on that fifo. In many implementations
* the @callback executes in the hw interrupt context.
* @txdl_init: Fifo's descriptor-initialize callback.
* See vxge_hal_fifo_txdl_init_f {}.
* If not NULL, HAL invokes the callback when opening
* the fifo via vxge_hal_vpath_open().
* @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
* HAL invokes the callback when closing the corresponding fifo.
* See also vxge_hal_fifo_txdl_term_f {}.
* @stats: Statistics of this fifo
*
* Fifo channel.
* Note: The structure is cache line aligned.
*/
typedef struct __hal_fifo_t {
__hal_channel_t channel;
vxge_hal_mempool_t *mempool;
vxge_hal_fifo_config_t *config;
u64 interrupt_type;
u32 no_snoop_bits;
u32 memblock_size;
u32 txdl_per_memblock;
u32 txdl_size;
u32 txdl_priv_size;
u32 per_txdl_space;
u32 txdlblock_priv_size;
u32 align_size;
vxge_hal_fifo_callback_f callback;
vxge_hal_fifo_txdl_init_f txdl_init;
vxge_hal_fifo_txdl_term_f txdl_term;
vxge_hal_vpath_stats_sw_fifo_info_t *stats;
} __vxge_os_attr_cacheline_aligned __hal_fifo_t;
/*
* struct __hal_fifo_txdl_priv_t - Transmit descriptor HAL-private data.
* @dma_addr: DMA (mapped) address of _this_ descriptor.
* @dma_handle: DMA handle used to map the descriptor onto device.
* @dma_offset: Descriptor's offset in the memory block. HAL allocates
* descriptors in memory blocks (see vxge_hal_fifo_config_t {})
* Each memblock is a contiguous block of DMA-able memory.
* @frags: Total number of fragments (that is, contiguous data buffers)
* carried by this TxDL.
* @align_vaddr_start: Aligned virtual address start
* @align_vaddr: Virtual address of the per-TxDL area in memory used for
* alignement. Used to place one or more mis-aligned fragments
* (the maximum defined by configration variable
* @max_aligned_frags).
* @align_dma_addr: DMA address translated from the @align_vaddr.
* @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
* @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
* @align_dma_offset: The current offset into the @align_vaddr area.
* Grows while filling the descriptor, gets reset.
* @align_used_frags: Number of fragments used.
* @alloc_frags: Total number of fragments allocated.
* @dang_frags: Number of fragments kept from release until this TxDL is freed.
* @bytes_sent:
* @unused:
* @dang_txdl:
* @next_txdl_priv:
* @first_txdp:
* @dang_txdlh: Pointer to TxDL (list) kept from release until this TxDL
* is freed.
* @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
* TxDL list.
* @txdlh: Corresponding txdlh to this TxDL.
* @memblock: Pointer to the TxDL memory block or memory page.
* on the next send operation.
* @dma_object: DMA address and handle of the memory block that contains
* the descriptor. This member is used only in the "checked"
* version of the HAL (to enforce certain assertions);
* otherwise it gets compiled out.
* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
*
* Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
* information associated with the descriptor. Note that ULD can ask HAL
* to allocate additional per-descriptor space for its own (ULD-specific)
* purposes.
*
* See also: vxge_hal_ring_rxd_priv_t {}.
*/
typedef struct __hal_fifo_txdl_priv_t {
dma_addr_t dma_addr;
pci_dma_h dma_handle;
ptrdiff_t dma_offset;
u32 frags;
u8 *align_vaddr_start;
u8 *align_vaddr;
dma_addr_t align_dma_addr;
pci_dma_h align_dma_handle;
pci_dma_acc_h align_dma_acch;
ptrdiff_t align_dma_offset;
u32 align_used_frags;
u32 alloc_frags;
u32 dang_frags;
u32 bytes_sent;
u32 unused;
vxge_hal_fifo_txd_t *dang_txdl;
struct __hal_fifo_txdl_priv_t *next_txdl_priv;
vxge_hal_fifo_txd_t *first_txdp;
void *memblock;
#if defined(VXGE_DEBUG_ASSERT)
vxge_hal_mempool_dma_t *dma_object;
#endif
#if defined(VXGE_OS_MEMORY_CHECK)
u32 allocated;
#endif
} __hal_fifo_txdl_priv_t;
#define VXGE_HAL_FIFO_ULD_PRIV(fifo, txdh) \
fifo->channel.dtr_arr[ \
((vxge_hal_fifo_txd_t *)(txdh))->host_control].uld_priv
#define VXGE_HAL_FIFO_HAL_PRIV(fifo, txdh) \
((__hal_fifo_txdl_priv_t *)(fifo->channel.dtr_arr[ \
((vxge_hal_fifo_txd_t *)(txdh))->host_control].hal_priv))
#define VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags
#define VXGE_HAL_FIFO_TXDL_INDEX(txdp) \
(u32)((vxge_hal_fifo_txd_t *)txdp)->host_control
/* ========================= FIFO PRIVATE API ============================= */
vxge_hal_status_e
__hal_fifo_create(
vxge_hal_vpath_h vpath_handle,
vxge_hal_fifo_attr_t *attr);
void
__hal_fifo_abort(
vxge_hal_fifo_h fifoh,
vxge_hal_reopen_e reopen);
vxge_hal_status_e
__hal_fifo_reset(
vxge_hal_fifo_h ringh);
void
__hal_fifo_delete(
vxge_hal_vpath_h vpath_handle);
void
__hal_fifo_txdl_free_many(
__hal_fifo_t *fifo,
vxge_hal_fifo_txd_t *txdp,
u32 list_size,
u32 frags);
#if defined(VXGE_HAL_ALIGN_XMIT)
void
__hal_fifo_txdl_align_free_unmap(
__hal_fifo_t *fifo,
vxge_hal_fifo_txd_t *txdp);
vxge_hal_status_e
__hal_fifo_txdl_align_alloc_map(
__hal_fifo_t *fifo,
vxge_hal_fifo_txd_t *txdp);
#endif
__EXTERN_END_DECLS
#endif /* VXGE_HAL_FIFO_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* __hal_ifmsg_wmsg_process - Process the srpcim to vpath wmsg
* @vpath: vpath
* @wmsg: wsmsg
*
* Processes the wmsg and invokes appropriate action
*/
void
__hal_ifmsg_wmsg_process(
__hal_virtualpath_t *vpath,
u64 wmsg)
{
u32 msg_type;
__hal_device_t *hldev = vpath->hldev;
vxge_assert(vpath);
vxge_hal_trace_log_vpath("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT
",wmsg = 0x"VXGE_OS_LLXFMT"", (ptr_t) vpath, wmsg);
if ((vpath->vp_id != vpath->hldev->first_vp_id) ||
(vpath->hldev->vpath_assignments &
mBIT((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(wmsg)))) {
vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return;
}
msg_type = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg);
switch (msg_type) {
default:
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_UNKNOWN:
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN:
__hal_device_handle_error(hldev,
vpath->vp_id,
VXGE_HAL_EVENT_DEVICE_RESET_START);
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END:
vpath->hldev->manager_up = TRUE;
__hal_device_handle_error(hldev,
vpath->vp_id,
VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE);
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN:
__hal_device_handle_error(hldev,
vpath->vp_id,
VXGE_HAL_EVENT_VPATH_RESET_START);
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END:
vpath->hldev->manager_up = TRUE;
__hal_device_handle_error(hldev,
vpath->vp_id,
VXGE_HAL_EVENT_VPATH_RESET_COMPLETE);
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP:
vpath->hldev->manager_up = TRUE;
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN:
vpath->hldev->manager_up = FALSE;
break;
case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_ACK:
break;
}
vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_ifmsg_device_reset_end_poll - Polls for the
* srpcim to vpath reset end
* @hldev: HAL Device
* @vp_id: Vpath id
*
* Polls for the srpcim to vpath reset end
*/
vxge_hal_status_e
__hal_ifmsg_device_reset_end_poll(
__hal_device_t *hldev,
u32 vp_id)
{
vxge_hal_status_e status;
vxge_assert(hldev);
vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
(ptr_t) hldev, vp_id);
status = vxge_hal_device_register_poll(
hldev->header.pdev,
hldev->header.regh0,
&hldev->vpmgmt_reg[vp_id]->srpcim_to_vpath_wmsg, 0,
~((u64) VXGE_HAL_IFMSG_DEVICE_RESET_END_MSG),
WAIT_FACTOR * hldev->header.config.device_poll_millis);
vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (status);
}
/*
* __hal_ifmsg_wmsg_post - Posts the srpcim to vpath req
* @hldev: Hal device
* @src_vp_id: Source vpath id
* @dest_vp_id: Vpath id, VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_MRPCIM, or
* VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST
* @msg_type: wsmsg type
* @msg_data: wsmsg data
*
* Posts the req
*/
vxge_hal_status_e
__hal_ifmsg_wmsg_post(
__hal_device_t *hldev,
u32 src_vp_id,
u32 dest_vp_id,
u32 msg_type,
u32 msg_data)
{
u64 val64;
vxge_hal_vpath_reg_t *vp_reg;
vxge_hal_status_e status;
vxge_assert(hldev);
vp_reg = hldev->vpath_reg[src_vp_id];
vxge_hal_trace_log_vpath("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim(
"hldev = 0x"VXGE_OS_STXFMT", src_vp_id = %d, dest_vp_id = %d, "
"msg_type = %d, msg_data = %d", (ptr_t) hldev, src_vp_id,
dest_vp_id, msg_type, msg_data);
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
0,
&vp_reg->rts_access_steer_ctrl);
vxge_os_wmb();
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_RTS_ACCESS_STEER_DATA0_IGNORE_IN_SVC_CHECK |
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(msg_type) |
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(dest_vp_id) |
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(src_vp_id) |
VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(++hldev->ifmsg_seqno) |
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(msg_data),
&vp_reg->rts_access_steer_data0);
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
0,
&vp_reg->rts_access_steer_data1);
vxge_os_wmb();
val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG) |
VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(val64, 32),
&vp_reg->rts_access_steer_ctrl);
vxge_os_wmb();
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(val64, 0),
&vp_reg->rts_access_steer_ctrl);
vxge_os_wmb();
status = vxge_hal_device_register_poll(hldev->header.pdev,
hldev->header.regh0,
&vp_reg->rts_access_steer_ctrl, 0,
VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
WAIT_FACTOR * hldev->header.config.device_poll_millis);
if (status != VXGE_HAL_OK) {
vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&vp_reg->rts_access_steer_ctrl);
if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&vp_reg->rts_access_steer_data0);
status = VXGE_HAL_OK;
} else {
status = VXGE_HAL_FAIL;
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_IFMSG_H
#define VXGE_HAL_IFMSG_H
__EXTERN_BEGIN_DECLS
#define VXGE_HAL_IFMSG_PRIV_DRIVER_UP_MSG \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(VXGE_HAL_IFMSG_MSV_OPCODE_UP)
#define VXGE_HAL_IFMSG_PRIV_DRIVER_DOWN_MSG \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(VXGE_HAL_IFMSG_MSV_OPCODE_DOWN)
#define VXGE_HAL_IFMSG_DEVICE_RESET_BEGIN_MSG \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE( \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN)
#define VXGE_HAL_IFMSG_DEVICE_RESET_END_MSG \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE( \
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END)
static inline u32
/* LINTED */
__hal_ifmsg_is_manager_up(u64 wmsg)
{
return (((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg) ==
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP) ||
((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg) ==
VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END));
}
vxge_hal_status_e
__hal_ifmsg_device_reset_end_poll(
__hal_device_t *hldev,
u32 vp_id);
void
__hal_ifmsg_wmsg_process(
__hal_virtualpath_t *vpath,
u64 wmsg);
vxge_hal_status_e
__hal_ifmsg_wmsg_post(
__hal_device_t *hldev,
u32 src_vp_id,
u32 dest_vp_id,
u32 msg_type,
u32 msg_data);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_IFMSG_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_LEGACY_REGS_H
#define VXGE_HAL_LEGACY_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_legacy_reg_t {
u8 unused00010[0x00010];
/* 0x00010 */ u64 toc_swapper_fb;
#define VXGE_HAL_TOC_SWAPPER_FB_INITIAL_VAL(val) vBIT(val, 0, 64)
/* 0x00018 */ u64 pifm_rd_swap_en;
#define VXGE_HAL_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vBIT(val, 0, 64)
/* 0x00020 */ u64 pifm_rd_flip_en;
#define VXGE_HAL_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vBIT(val, 0, 64)
/* 0x00028 */ u64 pifm_wr_swap_en;
#define VXGE_HAL_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vBIT(val, 0, 64)
/* 0x00030 */ u64 pifm_wr_flip_en;
#define VXGE_HAL_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vBIT(val, 0, 64)
/* 0x00038 */ u64 toc_first_pointer;
#define VXGE_HAL_TOC_FIRST_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
/* 0x00040 */ u64 host_access_en;
#define VXGE_HAL_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vBIT(val, 0, 64)
} vxge_hal_legacy_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_LEGACY_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_MEMREPAIR_REGS_H
#define VXGE_HAL_MEMREPAIR_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_memrepair_reg_t {
u64 unused1;
u64 unused2;
} vxge_hal_memrepair_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_MEMREPAIR_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* __hal_mempool_grow
*
* Will resize mempool up to %num_allocate value.
*/
static vxge_hal_status_e
__hal_mempool_grow(
vxge_hal_mempool_t *mempool,
u32 num_allocate,
u32 *num_allocated)
{
u32 i, j, k, item_index, is_last;
u32 first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
u32 n_items = mempool->items_per_memblock;
u32 start_block_idx = mempool->memblocks_allocated;
u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
__hal_device_t *hldev;
vxge_assert(mempool != NULL);
hldev = (__hal_device_t *) mempool->devh;
vxge_hal_trace_log_mm("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_mm(
"mempool = 0x"VXGE_OS_STXFMT", num_allocate = %d, "
"num_allocated = 0x"VXGE_OS_STXFMT, (ptr_t) mempool,
num_allocate, (ptr_t) num_allocated);
*num_allocated = 0;
if (end_block_idx > mempool->memblocks_max) {
vxge_hal_err_log_mm("%s",
"__hal_mempool_grow: can grow anymore");
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (VXGE_HAL_ERR_OUT_OF_MEMORY);
}
for (i = start_block_idx; i < end_block_idx; i++) {
void *the_memblock;
vxge_hal_mempool_dma_t *dma_object;
is_last = ((end_block_idx - 1) == i);
dma_object = mempool->memblocks_dma_arr + i;
/*
* allocate memblock's private part. Each DMA memblock
* has a space allocated for item's private usage upon
* mempool's user request. Each time mempool grows, it will
* allocate new memblock and its private part at once.
* This helps to minimize memory usage a lot.
*/
mempool->memblocks_priv_arr[i] = vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
mempool->items_priv_size * n_items);
if (mempool->memblocks_priv_arr[i] == NULL) {
vxge_hal_err_log_mm("memblock_priv[%d]: \
out of virtual memory, "
"requested %d(%d:%d) bytes", i,
mempool->items_priv_size * n_items,
mempool->items_priv_size, n_items);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_OUT_OF_MEMORY);
return (VXGE_HAL_ERR_OUT_OF_MEMORY);
}
vxge_os_memzero(mempool->memblocks_priv_arr[i],
mempool->items_priv_size * n_items);
/* allocate DMA-capable memblock */
mempool->memblocks_arr[i] =
__hal_blockpool_malloc(mempool->devh,
mempool->memblock_size,
&dma_object->addr,
&dma_object->handle,
&dma_object->acc_handle);
if (mempool->memblocks_arr[i] == NULL) {
vxge_os_free(
((__hal_device_t *) mempool->devh)->header.pdev,
mempool->memblocks_priv_arr[i],
mempool->items_priv_size * n_items);
vxge_hal_err_log_mm("memblock[%d]: \
out of DMA memory", i);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_OUT_OF_MEMORY);
return (VXGE_HAL_ERR_OUT_OF_MEMORY);
}
(*num_allocated)++;
mempool->memblocks_allocated++;
vxge_os_memzero(mempool->memblocks_arr[i],
mempool->memblock_size);
the_memblock = mempool->memblocks_arr[i];
/* fill the items hash array */
for (j = 0; j < n_items; j++) {
item_index = i * n_items + j;
if (first_time && (item_index >= mempool->items_initial))
break;
mempool->items_arr[item_index] =
((char *) the_memblock + j *mempool->item_size);
/* let caller to do more job on each item */
if (mempool->item_func_alloc != NULL) {
vxge_hal_status_e status;
if ((status = mempool->item_func_alloc(
mempool,
the_memblock,
i,
dma_object,
mempool->items_arr[item_index],
item_index,
is_last,
mempool->userdata)) != VXGE_HAL_OK) {
if (mempool->item_func_free != NULL) {
for (k = 0; k < j; k++) {
item_index = i * n_items + k;
(void) mempool->item_func_free(
mempool,
the_memblock,
i, dma_object,
mempool->items_arr[item_index],
item_index, is_last,
mempool->userdata);
}
}
vxge_os_free(((__hal_device_t *)
mempool->devh)->header.pdev,
mempool->memblocks_priv_arr[i],
mempool->items_priv_size *
n_items);
__hal_blockpool_free(mempool->devh,
the_memblock,
mempool->memblock_size,
&dma_object->addr,
&dma_object->handle,
&dma_object->acc_handle);
(*num_allocated)--;
mempool->memblocks_allocated--;
return (status);
}
}
mempool->items_current = item_index + 1;
}
vxge_hal_info_log_mm(
"memblock%d: allocated %dk, vaddr 0x"VXGE_OS_STXFMT", "
"dma_addr 0x"VXGE_OS_STXFMT,
i, mempool->memblock_size / 1024,
(ptr_t) mempool->memblocks_arr[i], dma_object->addr);
if (first_time && mempool->items_current ==
mempool->items_initial) {
break;
}
}
vxge_hal_trace_log_mm("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* vxge_hal_mempool_create
* @memblock_size:
* @items_initial:
* @items_max:
* @item_size:
* @item_func:
*
* This function will create memory pool object. Pool may grow but will
* never shrink. Pool consists of number of dynamically allocated blocks
* with size enough to hold %items_initial number of items. Memory is
* DMA-able but client must map/unmap before interoperating with the device.
* See also: vxge_os_dma_map(), vxge_hal_dma_unmap(), vxge_hal_status_e {}.
*/
vxge_hal_mempool_t *
vxge_hal_mempool_create(
vxge_hal_device_h devh,
u32 memblock_size,
u32 item_size,
u32 items_priv_size,
u32 items_initial,
u32 items_max,
vxge_hal_mempool_item_f item_func_alloc,
vxge_hal_mempool_item_f item_func_free,
void *userdata)
{
vxge_hal_status_e status;
u32 memblocks_to_allocate;
vxge_hal_mempool_t *mempool;
__hal_device_t *hldev;
u32 allocated;
vxge_assert(devh != NULL);
hldev = (__hal_device_t *) devh;
vxge_hal_trace_log_mm("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_mm(
"devh = 0x"VXGE_OS_STXFMT", memblock_size = %d, item_size = %d, "
"items_priv_size = %d, items_initial = %d, items_max = %d, "
"item_func_alloc = 0x"VXGE_OS_STXFMT", "
"item_func_free = 0x"VXGE_OS_STXFMT", "
"userdata = 0x"VXGE_OS_STXFMT, (ptr_t) devh,
memblock_size, item_size, items_priv_size,
items_initial, items_max, (ptr_t) item_func_alloc,
(ptr_t) item_func_free, (ptr_t) userdata);
if (memblock_size < item_size) {
vxge_hal_err_log_mm(
"memblock_size %d < item_size %d: misconfiguration",
memblock_size, item_size);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
return (NULL);
}
mempool = (vxge_hal_mempool_t *) vxge_os_malloc(
((__hal_device_t *) devh)->header.pdev, sizeof(vxge_hal_mempool_t));
if (mempool == NULL) {
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool, sizeof(vxge_hal_mempool_t));
mempool->devh = devh;
mempool->memblock_size = memblock_size;
mempool->items_max = items_max;
mempool->items_initial = items_initial;
mempool->item_size = item_size;
mempool->items_priv_size = items_priv_size;
mempool->item_func_alloc = item_func_alloc;
mempool->item_func_free = item_func_free;
mempool->userdata = userdata;
mempool->memblocks_allocated = 0;
if (memblock_size != VXGE_OS_HOST_PAGE_SIZE)
mempool->dma_flags = VXGE_OS_DMA_CACHELINE_ALIGNED;
#if defined(VXGE_HAL_DMA_CONSISTENT)
mempool->dma_flags |= VXGE_OS_DMA_CONSISTENT;
#else
mempool->dma_flags |= VXGE_OS_DMA_STREAMING;
#endif
mempool->items_per_memblock = memblock_size / item_size;
mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
mempool->items_per_memblock;
/* allocate array of memblocks */
mempool->memblocks_arr = (void **)vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
sizeof(void *) * mempool->memblocks_max);
if (mempool->memblocks_arr == NULL) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool->memblocks_arr,
sizeof(void *) * mempool->memblocks_max);
/* allocate array of private parts of items per memblocks */
mempool->memblocks_priv_arr = (void **)vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
sizeof(void *) * mempool->memblocks_max);
if (mempool->memblocks_priv_arr == NULL) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool->memblocks_priv_arr,
sizeof(void *) * mempool->memblocks_max);
/* allocate array of memblocks DMA objects */
mempool->memblocks_dma_arr =
(vxge_hal_mempool_dma_t *) vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
sizeof(vxge_hal_mempool_dma_t) * mempool->memblocks_max);
if (mempool->memblocks_dma_arr == NULL) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool->memblocks_dma_arr,
sizeof(vxge_hal_mempool_dma_t) * mempool->memblocks_max);
/* allocate hash array of items */
mempool->items_arr = (void **)vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
sizeof(void *) * mempool->items_max);
if (mempool->items_arr == NULL) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool->items_arr,
sizeof(void *) * mempool->items_max);
mempool->shadow_items_arr = (void **)vxge_os_malloc(
((__hal_device_t *) mempool->devh)->header.pdev,
sizeof(void *) * mempool->items_max);
if (mempool->shadow_items_arr == NULL) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_os_memzero(mempool->shadow_items_arr,
sizeof(void *) * mempool->items_max);
/* calculate initial number of memblocks */
memblocks_to_allocate = (mempool->items_initial +
mempool->items_per_memblock - 1) /
mempool->items_per_memblock;
vxge_hal_info_log_mm("allocating %d memblocks, "
"%d items per memblock", memblocks_to_allocate,
mempool->items_per_memblock);
/* pre-allocate the mempool */
status = __hal_mempool_grow(mempool, memblocks_to_allocate, &allocated);
vxge_os_memcpy(mempool->shadow_items_arr, mempool->items_arr,
sizeof(void *) * mempool->items_max);
if (status != VXGE_HAL_OK) {
vxge_hal_mempool_destroy(mempool);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (NULL);
}
vxge_hal_info_log_mm(
"total: allocated %dk of DMA-capable memory",
mempool->memblock_size * allocated / 1024);
vxge_hal_trace_log_mm("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (mempool);
}
/*
* vxge_hal_mempool_destroy
*/
void
vxge_hal_mempool_destroy(
vxge_hal_mempool_t *mempool)
{
u32 i, j, item_index;
__hal_device_t *hldev;
vxge_assert(mempool != NULL);
hldev = (__hal_device_t *) mempool->devh;
vxge_hal_trace_log_mm("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_mm("mempool = 0x"VXGE_OS_STXFMT,
(ptr_t) mempool);
for (i = 0; i < mempool->memblocks_allocated; i++) {
vxge_hal_mempool_dma_t *dma_object;
vxge_assert(mempool->memblocks_arr[i]);
vxge_assert(mempool->memblocks_dma_arr + i);
dma_object = mempool->memblocks_dma_arr + i;
for (j = 0; j < mempool->items_per_memblock; j++) {
item_index = i * mempool->items_per_memblock + j;
/* to skip last partially filled(if any) memblock */
if (item_index >= mempool->items_current)
break;
/* let caller to do more job on each item */
if (mempool->item_func_free != NULL) {
mempool->item_func_free(mempool,
mempool->memblocks_arr[i],
i, dma_object,
mempool->shadow_items_arr[item_index],
item_index, /* unused */ -1,
mempool->userdata);
}
}
vxge_os_free(hldev->header.pdev,
mempool->memblocks_priv_arr[i],
mempool->items_priv_size * mempool->items_per_memblock);
__hal_blockpool_free(hldev,
mempool->memblocks_arr[i],
mempool->memblock_size,
&dma_object->addr,
&dma_object->handle,
&dma_object->acc_handle);
}
if (mempool->items_arr) {
vxge_os_free(hldev->header.pdev,
mempool->items_arr, sizeof(void *) * mempool->items_max);
}
if (mempool->shadow_items_arr) {
vxge_os_free(hldev->header.pdev,
mempool->shadow_items_arr,
sizeof(void *) * mempool->items_max);
}
if (mempool->memblocks_dma_arr) {
vxge_os_free(hldev->header.pdev,
mempool->memblocks_dma_arr,
sizeof(vxge_hal_mempool_dma_t) *
mempool->memblocks_max);
}
if (mempool->memblocks_priv_arr) {
vxge_os_free(hldev->header.pdev,
mempool->memblocks_priv_arr,
sizeof(void *) * mempool->memblocks_max);
}
if (mempool->memblocks_arr) {
vxge_os_free(hldev->header.pdev,
mempool->memblocks_arr,
sizeof(void *) * mempool->memblocks_max);
}
vxge_os_free(hldev->header.pdev,
mempool, sizeof(vxge_hal_mempool_t));
vxge_hal_trace_log_mm("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
}
/*
* vxge_hal_check_alignment - Check buffer alignment and calculate the
* "misaligned" portion.
* @dma_pointer: DMA address of the buffer.
* @size: Buffer size, in bytes.
* @alignment: Alignment "granularity" (see below), in bytes.
* @copy_size: Maximum number of bytes to "extract" from the buffer
* (in order to spost it as a separate scatter-gather entry). See below.
*
* Check buffer alignment and calculate "misaligned" portion, if exists.
* The buffer is considered aligned if its address is multiple of
* the specified @alignment. If this is the case,
* vxge_hal_check_alignment() returns zero.
* Otherwise, vxge_hal_check_alignment() uses the last argument,
* @copy_size,
* to calculate the size to "extract" from the buffer. The @copy_size
* may or may not be equal @alignment. The difference between these two
* arguments is that the @alignment is used to make the decision: aligned
* or not aligned. While the @copy_size is used to calculate the portion
* of the buffer to "extract", i.e. to post as a separate entry in the
* transmit descriptor. For example, the combination
* @alignment = 8 and @copy_size = 64 will work okay on AMD Opteron boxes.
*
* Note: @copy_size should be a multiple of @alignment. In many practical
* cases @copy_size and @alignment will probably be equal.
*
* See also: vxge_hal_fifo_txdl_buffer_set_aligned().
*/
u32
vxge_hal_check_alignment(
dma_addr_t dma_pointer,
u32 size,
u32 alignment,
u32 copy_size)
{
u32 misaligned_size;
misaligned_size = (int)(dma_pointer & (alignment - 1));
if (!misaligned_size) {
return (0);
}
if (size > copy_size) {
misaligned_size = (int)(dma_pointer & (copy_size - 1));
misaligned_size = copy_size - misaligned_size;
} else {
misaligned_size = size;
}
return (misaligned_size);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_MM_H
#define VXGE_HAL_MM_H
__EXTERN_BEGIN_DECLS
typedef void *vxge_hal_mempool_h;
/*
* struct vxge_hal_mempool_dma_t - Represents DMA objects passed to the
* caller.
*/
typedef struct vxge_hal_mempool_dma_t {
dma_addr_t addr;
pci_dma_h handle;
pci_dma_acc_h acc_handle;
} vxge_hal_mempool_dma_t;
/*
* vxge_hal_mempool_item_f - Mempool item alloc/free callback
* @mempoolh: Memory pool handle.
* @memblock: Address of memory block
* @memblock_index: Index of memory block
* @item: Item that gets allocated or freed.
* @index: Item's index in the memory pool.
* @is_last: True, if this item is the last one in the pool; false - otherwise.
* userdata: Per-pool user context.
*
* Memory pool allocation/deallocation callback.
*/
typedef vxge_hal_status_e (*vxge_hal_mempool_item_f) (
vxge_hal_mempool_h mempoolh,
void *memblock,
u32 memblock_index,
vxge_hal_mempool_dma_t *dma_object,
void *item,
u32 index,
u32 is_last,
void *userdata);
/*
* struct vxge_hal_mempool_t - Memory pool.
*/
typedef struct vxge_hal_mempool_t {
vxge_hal_mempool_item_f item_func_alloc;
vxge_hal_mempool_item_f item_func_free;
void *userdata;
void **memblocks_arr;
void **memblocks_priv_arr;
vxge_hal_mempool_dma_t *memblocks_dma_arr;
vxge_hal_device_h devh;
u32 memblock_size;
u32 memblocks_max;
u32 memblocks_allocated;
u32 item_size;
u32 items_max;
u32 items_initial;
u32 items_current;
u32 items_per_memblock;
u32 dma_flags;
void **items_arr;
void **shadow_items_arr;
u32 items_priv_size;
} vxge_hal_mempool_t;
/*
* __hal_mempool_item_count - Returns number of items in the mempool
*/
static inline u32
/* LINTED */
__hal_mempool_item_count(
vxge_hal_mempool_t *mempool)
{
return (mempool->items_current);
}
/*
* __hal_mempool_item - Returns pointer to the item in the mempool
* items array.
*/
static inline void *
/* LINTED */
__hal_mempool_item(
vxge_hal_mempool_t *mempool,
u32 items_index)
{
return (mempool->items_arr[items_index]);
}
/*
* __hal_mempool_item_priv - will return pointer on per item private space
*/
static inline void*
/* LINTED */
__hal_mempool_item_priv(
vxge_hal_mempool_t *mempool,
u32 memblock_idx,
void *item,
u32 *memblock_item_idx)
{
ptrdiff_t offset;
void *memblock = mempool->memblocks_arr[memblock_idx];
vxge_assert(memblock);
/* LINTED */
offset = (u32) ((u8 *) item - (u8 *) memblock);
vxge_assert(offset >= 0 && (u32) offset < mempool->memblock_size);
(*memblock_item_idx) = (u32) offset / mempool->item_size;
vxge_assert((*memblock_item_idx) < mempool->items_per_memblock);
return ((u8 *) mempool->memblocks_priv_arr[memblock_idx] +
(*memblock_item_idx) * mempool->items_priv_size);
}
/*
* __hal_mempool_items_arr - will return pointer to the items array in the
* mempool.
*/
static inline void *
/* LINTED */
__hal_mempool_items_arr(
vxge_hal_mempool_t *mempool)
{
return (mempool->items_arr);
}
/*
* __hal_mempool_memblock - will return pointer to the memblock in the
* mempool memblocks array.
*/
static inline void *
/* LINTED */
__hal_mempool_memblock(
vxge_hal_mempool_t *mempool,
u32 memblock_idx)
{
vxge_assert(mempool->memblocks_arr[memblock_idx]);
return (mempool->memblocks_arr[memblock_idx]);
}
/*
* __hal_mempool_memblock_dma - will return pointer to the dma block
* corresponds to the memblock(identified by memblock_idx) in the mempool.
*/
static inline vxge_hal_mempool_dma_t *
/* LINTED */
__hal_mempool_memblock_dma(
vxge_hal_mempool_t *mempool,
u32 memblock_idx)
{
return (mempool->memblocks_dma_arr + memblock_idx);
}
vxge_hal_mempool_t *
vxge_hal_mempool_create(
vxge_hal_device_h devh,
u32 memblock_size,
u32 item_size,
u32 private_size,
u32 items_initial,
u32 items_max,
vxge_hal_mempool_item_f item_func_alloc,
vxge_hal_mempool_item_f item_func_free,
void *userdata);
void
vxge_hal_mempool_destroy(
vxge_hal_mempool_t *mempool);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_MM_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_MRPCIM_H
#define VXGE_HAL_MRPCIM_H
__EXTERN_BEGIN_DECLS
/*
* __hal_mrpcim_t
*
* HAL mrpcim object. Represents privileged mode device.
*/
typedef struct __hal_mrpcim_t {
u32 mdio_phy_prtad0;
u32 mdio_phy_prtad1;
u32 mdio_dte_prtad0;
u32 mdio_dte_prtad1;
vxge_hal_vpd_data_t vpd_data;
__hal_blockpool_entry_t *mrpcim_stats_block;
vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats;
vxge_hal_mrpcim_stats_hw_info_t mrpcim_stats_sav;
vxge_hal_mrpcim_xpak_stats_t xpak_stats[VXGE_HAL_MAC_MAX_WIRE_PORTS];
} __hal_mrpcim_t;
#define VXGE_HAL_MRPCIM_STATS_PIO_READ(loc, offset) { \
status = vxge_hal_mrpcim_stats_access(devh, \
VXGE_HAL_STATS_OP_READ, \
loc, \
offset, \
&val64); \
\
if (status != VXGE_HAL_OK) { \
vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", \
__FILE__, __func__, __LINE__, status); \
return (status); \
} \
}
#define VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(reg) \
vxge_os_pio_mem_write64( \
hldev->header.pdev, \
hldev->header.regh0, \
VXGE_HAL_INTR_MASK_ALL, \
(reg));
#define VXGE_HAL_MRPCIM_ERROR_REG_MASK(reg) \
vxge_os_pio_mem_write64( \
hldev->header.pdev, \
hldev->header.regh0, \
VXGE_HAL_INTR_MASK_ALL, \
(reg));
#define VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(mask, reg) \
vxge_os_pio_mem_write64( \
hldev->header.pdev, \
hldev->header.regh0, \
~mask, \
(reg));
vxge_hal_status_e
__hal_mrpcim_mdio_access(
vxge_hal_device_h devh,
u32 port,
u32 operation,
u32 device,
u16 addr,
u16 *data);
vxge_hal_status_e
__hal_mrpcim_rts_table_access(
vxge_hal_device_h devh,
u32 action,
u32 rts_table,
u32 offset,
u64 *data1,
u64 *data2,
u64 *vpath_vector);
vxge_hal_status_e
__hal_mrpcim_initialize(__hal_device_t *hldev);
vxge_hal_status_e
__hal_mrpcim_terminate(__hal_device_t *hldev);
void
__hal_mrpcim_get_vpd_data(__hal_device_t *hldev);
void
__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev,
u32 port, u32 type, u32 value);
vxge_hal_status_e
__hal_mrpcim_stats_get(
__hal_device_t *hldev,
vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats);
vxge_hal_status_e
__hal_mrpcim_mac_configure(__hal_device_t *hldev);
vxge_hal_status_e
__hal_mrpcim_lag_configure(__hal_device_t *hldev);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_MRPCIM_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_PCICFGMGMT_REGS_H
#define VXGE_HAL_PCICFGMGMT_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_pcicfgmgmt_reg_t {
/* 0x00000 */ u64 resource_no;
#define VXGE_HAL_RESOURCE_NO_PFN_OR_VF BIT(3)
/* 0x00008 */ u64 bargrp_pf_or_vf_bar0_mask;
#define VXGE_HAL_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val)\
vBIT(val, 2, 6)
/* 0x00010 */ u64 bargrp_pf_or_vf_bar1_mask;
#define VXGE_HAL_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val)\
vBIT(val, 2, 6)
/* 0x00018 */ u64 bargrp_pf_or_vf_bar2_mask;
#define VXGE_HAL_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val)\
vBIT(val, 2, 6)
/* 0x00020 */ u64 msixgrp_no;
#define VXGE_HAL_MSIXGRP_NO_TABLE_SIZE(val) vBIT(val, 5, 11)
} vxge_hal_pcicfgmgmt_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_PCICFGMGMT_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_REGDEFS_H
#define VXGE_HAL_REGDEFS_H
__EXTERN_BEGIN_DECLS
#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) bVAL16(bits, 0)
#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) bVAL8(bits, 48)
#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) bVAL8(bits, 56)
#define VXGE_HAL_VPD_LEN 80
#define VXGE_HAL_CARD_TITAN_VPD_ADDR 0x80
#define VPD_READ_COMPLETE 0x80
#define VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(bits) bVAL5(bits, 3)
#define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VHLABEL(bits) bVAL5(bits, 3)
#define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VPLANE(bits) bVAL5(bits, 11)
#define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_FUNC(bits) bVAL5(bits, 19)
#define VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)\
bVAL3(bits, 5)
#define VXGE_HAL_VPLANE_ASSIGNMENTS_GET_VPLANE_ASSIGNMENTS(bits) \
bVAL5(bits, 3)
#define VXGE_HAL_PF_SW_RESET_COMMAND 0xA5
#define VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES 17
#define VXGE_HAL_TITAN_SRPCIM_REG_SPACES 17
#define VXGE_HAL_TITAN_VPMGMT_REG_SPACES 17
#define VXGE_HAL_TITAN_VPATH_REG_SPACES 17
#define VXGE_HAL_PRIV_VPATH_ACTION 5
#define VXGE_HAL_BW_CONTROL 12
#define VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_NON_PRIV_BANDWIDTH_CTRL 32
#define VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF 17
#define VXGE_HAL_API_FUNC_MODE_COMMIT 21
#define VXGE_HAL_ASIC_MODE_RESERVED 0
#define VXGE_HAL_ASIC_MODE_NO_IOV 1
#define VXGE_HAL_ASIC_MODE_SR_IOV 2
#define VXGE_HAL_ASIC_MODE_MR_IOV 3
#define VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN mBIT(3)
#define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE mBIT(19)
#define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH mBIT(23)
#define VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS mBIT(31)
#define VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) bVAL1(bits, 3)
#define VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) bVAL32(bits, 0)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)\
bVAL14(bits, 50)
#define VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) bVAL17(bits, 0)
#define VXGE_HAL_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)\
bVAL5(bits, 3)
#define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)\
bVAL15(bits, 17)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE 0
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY 1
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE 2
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY 0
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE 1
#define VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val)\
(val&~VXGE_HAL_TOC_KDFC_INITIAL_BIR(7))
#define VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val) bVAL3(val, 61)
#define VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val)\
(val&~VXGE_HAL_TOC_USDC_INITIAL_BIR(7))
#define VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val) bVAL3(val, 61)
#define VXGE_HAL_LAG_CFG_GET_MODE(bits) bVAL2(bits, 6)
#define VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(bits) bVAL2(bits, 6)
#define VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits
#define VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) bVAL15(bits, 1)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) bVAL15(bits, 17)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) bVAL15(bits, 33)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vBIT(val, 42, 5)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vBIT(val, 47, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15)
#define VXGE_HAL_PRC_CFG4_RING_MODE_ONE_BUFFER 0
#define VXGE_HAL_PRC_CFG4_RING_MODE_THREE_BUFFER 1
#define VXGE_HAL_PRC_CFG4_RING_MODE_FIVE_BUFFER 2
#define VXGE_HAL_PRC_CFG7_SCATTER_MODE_A 0
#define VXGE_HAL_PRC_CFG7_SCATTER_MODE_B 2
#define VXGE_HAL_PRC_CFG7_SCATTER_MODE_C 1
#define VXGE_HAL_RTDMA_BW_CTRL_GET_DESIRED_BW(bits) bVAL18(bits, 46)
#define VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ 0
#define VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE 1
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA 0
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID 1
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN 3
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN 4
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS 10
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS 11
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13
#define VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
#define VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) bVAL48(bits, 0)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vBIT(val, 0, 48)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
bVAL5(bits, 55)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) vBIT(val, 55, 5)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
bVAL2(bits, 62)
#define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vBIT(val, 62, 2)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY 0
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY 1
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY 2
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY 3
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY 0
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY 1
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_CLEAR_TABLE 2
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_VERSION 0
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO 3
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL 4
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_VPATH_MAP 5
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PCI_CONFIG 6
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_UDP_RTH 10
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FUNC_MODE 11
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG 15
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE 16
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL 17
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_INFO 18
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_COMMIT 21
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_COUNT 24
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE 29
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR 172
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA 0
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID 1
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13
#define VXGE_HAL_MSG_SEND_TO_VPATH_MASK 0xFFFFFFFFUL
#define VXGE_HAL_MSG_SEND_RETRY 100
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_MODE 2
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_DATA 3
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_COMMIT 4
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP mBIT(63)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(bits) \
bVAL8(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_OK 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_DONE 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_ERROR 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_SKIP 3
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_CODE(bits) \
bVAL8(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_SUB_CODE(bits) \
bVAL8(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(bits) \
bVAL32(bits, 24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_TOTAL_STEPS(bits) \
bVAL32(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_COMPL_STEPS(bits) \
bVAL32(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) bVAL11(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vBIT(val, 0, 12)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) bVAL11(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(val) vBIT(val, 0, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(val) vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(val) vBIT(val, 8, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(val) vBIT(val, 16, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(val) vBIT(val, 32, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) bVAL1(bits, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL mBIT(3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) bVAL1(bits, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL mBIT(7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) bVAL16(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vBIT(val, 8, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) bVAL1(bits, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN mBIT(3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits)\
bVAL4(bits, 4)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) vBIT(val, 4, 4)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits)\
bVAL2(bits, 10)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) vBIT(val, 10, 2)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits)\
bVAL1(bits, 15)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN mBIT(15)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits)\
bVAL1(bits, 19)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN mBIT(19)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits)\
bVAL1(bits, 23)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN mBIT(23)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits)\
bVAL1(bits, 27)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN mBIT(27)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits)\
bVAL1(bits, 31)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN mBIT(31)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits)\
bVAL1(bits, 35)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN mBIT(35)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits)\
bVAL1(bits, 39)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE mBIT(39)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits)\
bVAL1(bits, 43)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN mBIT(43)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits)\
bVAL1(bits, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN mBIT(3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits)\
bVAL7(bits, 9)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val)\
vBIT(val, 9, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val)\
vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits)\
bVAL1(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN mBIT(8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits)\
bVAL7(bits, 9)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val)\
vBIT(val, 9, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits)\
bVAL8(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val)\
vBIT(val, 16, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits)\
bVAL1(bits, 24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN mBIT(24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits)\
bVAL7(bits, 25)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val)\
vBIT(val, 25, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val)\
vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits)\
bVAL1(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN mBIT(8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits)\
bVAL7(bits, 9)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val)\
vBIT(val, 9, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits)\
bVAL8(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val)\
vBIT(val, 16, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits)\
bVAL1(bits, 24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN mBIT(24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits)\
bVAL7(bits, 25)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val)\
vBIT(val, 25, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits)\
bVAL32(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val)\
vBIT(val, 0, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val)\
vBIT(val, 32, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits)\
bVAL16(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val)\
vBIT(val, 0, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits)\
bVAL16(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val)\
vBIT(val, 16, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits)\
bVAL4(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val)\
vBIT(val, 32, 4)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits)\
bVAL4(bits, 36)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val)\
vBIT(val, 36, 4)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits)\
bVAL2(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) vBIT(val, 40, 2)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits)\
bVAL2(bits, 42)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) vBIT(val, 42, 2)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) bVAL64(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vBIT(val, 0, 64)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) bVAL1(bits, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN mBIT(3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) bVAL1(bits, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN mBIT(3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)\
bVAL48(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) vBIT(val, 0, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
bVAL5(bits, 55)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)\
vBIT(val, 55, 5)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
bVAL2(bits, 62)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) vBIT(val, 62, 2)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val)\
vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits)\
bVAL1(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN mBIT(8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits)\
bVAL7(bits, 9)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val)\
vBIT(val, 9, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits)\
bVAL8(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val)\
vBIT(val, 16, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits)\
bVAL1(bits, 24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN mBIT(24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits)\
bVAL7(bits, 25)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val)\
vBIT(val, 25, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits)\
bVAL8(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val)\
vBIT(val, 32, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits)\
bVAL1(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN mBIT(40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits)\
bVAL7(bits, 41)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val)\
vBIT(val, 41, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits)\
bVAL8(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val)\
vBIT(val, 48, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits)\
bVAL1(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN mBIT(56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits)\
bVAL7(bits, 57)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val)\
vBIT(val, 57, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FW_VERSION 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FLASH_VERSION 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE 3
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0 4
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1 5
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2 6
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3 7
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS 8
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE 10
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR 11
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO 13
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO 14
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE 20
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR 21
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO 23
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO 24
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_LAG_MODE 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_ACTIVE_PORT 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(bits) \
bVAL8(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS(val) \
vBIT(val, 56, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_SUCCESS 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_FAIL 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(bits) \
bVAL3(bits, 61)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_LAG_MODE(val) \
vBIT(val, 61, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_PREFFERRED_PORT mBIT(62)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_ACTIVE_PORT mBIT(63)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_ADDR(bits) bVAL16(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_ADDR(val) vBIT(val, 16, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_READ 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_WRITE mBIT(39)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_BYTE_COUNT(bits) bVAL8(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_BYTE_COUNT(val) vBIT(val, 40, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VH(bits) bVAL8(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(val) vBIT(val, 48, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNCTION(bits) bVAL8(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(val) vBIT(val, 56, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_DATA(bits) bVAL32(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_DATA(val) vBIT(val, 32, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_PCI_DATA(bits) bVAL32(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_PCI_DATA(val) vBIT(val, 32, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_IS_VPATH_ASSIGNED(vpid) mBIT((63-vpid))
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_IGNORE_IN_SVC_CHECK mBIT(0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(bits) bVAL7(bits, 1)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(val) vBIT(val, 1, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_UNKNOWN 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN 3
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END 4
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP 5
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN 6
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_ACK 127
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DEST(bits) bVAL8(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(val) vBIT(val, 8, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_MRPCIM 0xfe
#define VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST 0xff
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(bits) bVAL8(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(val) vBIT(val, 16, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_SEQ_NUM(bits) bVAL32(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(val) vBIT(val, 32, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DATA(bits) bVAL16(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(val) vBIT(val, 48, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_PENDING 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_NOT_IN_SVC 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_UDP_RTH_ENABLE mBIT(63)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(val) vBIT(val, 48, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(val) vBIT(val, 56, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits) bVAL3(bits, 45)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits) bVAL8(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits) bVAL8(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val) vBIT(val, 45, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val) vBIT(val, 48, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val) vBIT(val, 56, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val) vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits) bVAL3(bits, 21)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits) bVAL8(bits, 24)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits) bVAL8(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val) vBIT(val, 21, 3)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val) vBIT(val, 24, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val) vBIT(val, 32, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(bits) bVAL8(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(bits) bVAL8(bits, 56)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(val) vBIT(val, 56, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17 0
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2 1
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1 2
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1 3
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2 4
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1 5
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2 6
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4 7
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8 8
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4 9
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4 10
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2 11
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)\
bVAL8(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vBIT(val, 8, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) bVAL16(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) vBIT(val, 16, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)\
bVAL8(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vBIT(val, 32, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)\
bVAL8(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vBIT(val, 40, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)\
bVAL16(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vBIT(val, 48, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_DAY(val) vBIT(val, 0, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(bits)\
bVAL8(bits, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MONTH(val) vBIT(val, 8, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(bits)\
bVAL16(bits, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_YEAR(val) vBIT(val, 16, 16)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(bits)\
bVAL8(bits, 32)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MAJOR vBIT(val, 32, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(bits)\
bVAL8(bits, 40)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MINOR vBIT(val, 40, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(bits)\
bVAL16(bits, 48)
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_BUILD vBIT(val, 48, 16)
/* Netork port control API related */
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val) vBIT(val, 0, 8)
/* Bandwidth & priority related MACROS */
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits) \
vxge_bVALn(bits, 0, 8)
#define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_SHOW_PORT_INFO(bits)\
bVAL1(bits, 55)
#define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_PORT_NUM(bits) bVAL1(bits, 63)
#define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM(bits) bVAL17(bits, 0)
#define VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) bVAL16(bits, 48)
#define VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(bits) bVAL16(bits, 48)
#define VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(bits) bVAL16(bits, 48)
#define VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(bits) bVAL9(bits, 36)
#define VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) bVAL32(bits, 0)
#define VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) bVAL32(bits, 0)
#define VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) bVAL32(bits, 0)
#define VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits)
#define VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits)
#define VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) bVAL32(bits, 32)
#define VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) bVAL32(bits, 32)
#define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits)\
bVAL32(bits, 0)
#define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits)\
bVAL32(bits, 0)
#define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits)\
bVAL32(bits, 0)
#define VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits)\
bVAL32(bits, 32)
#define \
VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits)\
bVAL16(bits, 48)
#define VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) bVAL16(bits, 0)
#define VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) bVAL16(bits, 16)
#define VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) bVAL16(bits, 32)
#define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) bVAL16(bits, 0)
#define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits)\
bVAL16(bits, 16)
#define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) bVAL16(bits, 32)
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR 0x0
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_WRITE 0x1
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR 0x2
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ 0x3
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_RESERVED 0x4
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE 0x5
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR 0x6
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ 0x7
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1 0x0000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK 0x01
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL 0x8000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_1_BYTE 0x02
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_256_BYTES 0x03
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_COMPLETE 0x04
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_PROGRESS 0x08
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_FAILED 0x0C
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK 0x0C
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_READ 0x00
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_WRITE 0x20
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_ADDR(val) (val<<8)
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_1 0x8067
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_2 0x8068
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_DATA(val)\
(val&0xff)
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG 0xA070
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW 0x01
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH 0x02
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW 0x04
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH 0x08
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW 0x40
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH 0x80
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG 0xA074
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW 0x01
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH 0x02
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW 0x04
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH 0x08
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW 0x40
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH 0x80
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT 0xA100
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SINGLE_UPDATE 0x0000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SLOW_PER_UPDATE 0x0001
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_INT_PER_UPDATE 0x0002
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_FAST_PER_UPDATE 0x0003
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_IDLE 0x0000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_COMPLETE 0x0004
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_PROGRESS 0x0008
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_FAILED 0x000C
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_UPLOAD_EN 0x0010
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_256_BYTES 0x0000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_1_BYTES 0x0100
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_IDLE 0x0000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_COMPLETE 0x1000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_PROGRESS 0x2000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_FAILED 0x3000
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_TX_LED 0xD006
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_RX_LED 0xD007
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_LINK_LED 0xD008
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD 1
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PCS 3
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PHY_XS 4
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS 5
#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_AN 7
#define VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(bits) bVAL5(bits, 19)
#define VXGE_HAL_MDIO_GEN_CFG_PORT_MDIO_PHY_PRTAD(val) vBIT(val, 19, 5)
#define VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(bits) bVAL5(bits, 7)
#define VXGE_HAL_XGXS_STATIC_CFG_PORT_MDIO_DTE_PRTAD(val) vBIT(val, 7, 5)
#define VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(bits) bVAL16(bits, 32)
#define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) bVAL32(bits, 0)
#define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) bVAL32(bits, 32)
#define \
VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits)\
bVAL32(bits, 32)
#define \
VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits)\
bVAL32(bits, 32)
#define \
VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) bVAL32(bits, 0)
#define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) bVAL32(bits, 32)
#define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) bVAL32(bits, 0)
#define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) bVAL32(bits, 32)
#define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) bVAL32(bits, 0)
#define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) bVAL32(bits, 32)
#define VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) bVAL32(bits, 32)
#define VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) bVAL32(bits, 32)
#define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(bits) bVAL32(bits, 0)
#define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(bits) bVAL32(bits, 32)
#define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) bVAL32(bits, 0)
#define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) bVAL32(bits, 32)
#define VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) bVAL32(bits, 0)
#define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) bVAL16(bits, 0)
#define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) bVAL16(bits, 16)
#define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) bVAL16(bits, 32)
#define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) bVAL16(bits, 0)
#define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL16(bits, 16)
#define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) bVAL16(bits, 32)
#define VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(bits) (bits)
#define VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(bits) (bits)
#define VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(bits) (bits)
#define VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits)\
bVAL32(bits, 32)
#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits)\
bVAL8(bits, 8)
#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits)\
bVAL8(bits, 16)
#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits)\
bVAL8(bits, 0)
#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits)\
bVAL8(bits, 8)
#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits)\
bVAL8(bits, 16)
__EXTERN_END_DECLS
#endif /* VXGE_HAL_REGDEFS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_RING_H
#define VXGE_HAL_RING_H
__EXTERN_BEGIN_DECLS
typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE];
#define VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8)
#define VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET (VXGE_OS_HOST_PAGE_SIZE-16)
/*
* struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
* @dma_addr: DMA (mapped) address of _this_ descriptor.
* @dma_handle: DMA handle used to map the descriptor onto device.
* @dma_offset: Descriptor's offset in the memory block. HAL allocates
* descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE
* bytes. Each memblock is contiguous DMA-able memory. Each
* memblock contains 1 or more 4KB RxD blocks visible to the
* X3100 hardware.
* @dma_object: DMA address and handle of the memory block that contains
* the descriptor. This member is used only in the "checked"
* version of the HAL (to enforce certain assertions);
* otherwise it gets compiled out.
* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
* @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes
* next RxD block pointers
*
* Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
* information associated with the descriptor. Note that ULD can ask HAL
* to allocate additional per-descriptor space for its own (ULD-specific)
* purposes.
*/
typedef struct __hal_ring_rxd_priv_t {
dma_addr_t dma_addr;
pci_dma_h dma_handle;
ptrdiff_t dma_offset;
#if defined(VXGE_DEBUG_ASSERT)
vxge_hal_mempool_dma_t *dma_object;
#endif
#if defined(VXGE_OS_MEMORY_CHECK)
u32 allocated;
#endif
u32 db_bytes;
} __hal_ring_rxd_priv_t;
/*
* struct __hal_ring_t - Ring channel.
* @channel: Channel "base" of this ring, the common part of all HAL
* channels.
* @mempool: Memory pool, the pool from which descriptors get allocated.
* (See vxge_hal_mm.h).
* @config: Ring configuration, part of device configuration
* (see vxge_hal_device_config_t {}).
* @ring_length: Length of the ring
* @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
* as per X3100 User Guide.
* @indicate_max_pkts: Maximum number of packets processed within a single
* interrupt. Can be used to limit the time spent inside hw interrupt.
* @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec,
* 1-buffer mode descriptor is 32 byte long, etc.
* @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
* data (e.g., DMA handle for Solaris)
* @per_rxd_space: Per rxd space requested by ULD
* @rxds_per_block: Number of descriptors per hardware-defined RxD
* block. Depends on the (1-, 3-, 5-) buffer mode.
* @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
* usage. Not to confuse with @rxd_priv_size.
* @rxd_mem_avail: Available RxD memory
* @db_byte_count: Number of doorbell bytes to be posted
* @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
* Used in conjunction with @indicate_max_pkts.
* @active_sw_lros: List of Software LRO sessions in progess
* @active_sw_lro_count: Number of Software LRO sessions in progess
* @free_sw_lros: List of Software LRO sessions free
* @free_sw_lro_count: Number of Software LRO sessions free
* @sw_lro_lock: LRO session lists' lock
* @callback: Channel completion callback. HAL invokes the callback when there
* are new completions on that channel. In many implementations
* the @callback executes in the hw interrupt context.
* @rxd_init: Channel's descriptor-initialize callback.
* See vxge_hal_ring_rxd_init_f {}.
* If not NULL, HAL invokes the callback when opening the ring.
* @rxd_term: Channel's descriptor-terminate callback. If not NULL,
* HAL invokes the callback when closing the corresponding channel.
* See also vxge_hal_channel_rxd_term_f {}.
* @stats: Statistics for ring
* Ring channel.
*
* Note: The structure is cache line aligned to better utilize
* CPU cache performance.
*/
typedef struct __hal_ring_t {
__hal_channel_t channel;
vxge_hal_mempool_t *mempool;
vxge_hal_ring_config_t *config;
u32 ring_length;
u32 buffer_mode;
u32 indicate_max_pkts;
u32 rxd_size;
u32 rxd_priv_size;
u32 per_rxd_space;
u32 rxds_per_block;
u32 rxdblock_priv_size;
u32 rxd_mem_avail;
u32 db_byte_count;
u32 cmpl_cnt;
vxge_hal_ring_callback_f callback;
vxge_hal_ring_rxd_init_f rxd_init;
vxge_hal_ring_rxd_term_f rxd_term;
vxge_hal_vpath_stats_sw_ring_info_t *stats;
} __vxge_os_attr_cacheline_aligned __hal_ring_t;
#define VXGE_HAL_RING_ULD_PRIV(ring, rxdh) \
ring->channel.dtr_arr[ \
((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv
#define VXGE_HAL_RING_HAL_PRIV(ring, rxdh) \
((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[ \
((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv))
#define VXGE_HAL_RING_POST_DOORBELL(vph, ringh) \
{ \
if (((__hal_ring_t *)(ringh))->config->post_mode == \
VXGE_HAL_RING_POST_MODE_DOORBELL) { \
vxge_hal_ring_rxd_post_post_db(vph); \
} \
}
#define VXGE_HAL_RING_RXD_INDEX(rxdp) \
(u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control
/* ========================== RING PRIVATE API ============================ */
u64
__hal_ring_first_block_address_get(
vxge_hal_ring_h ringh);
vxge_hal_status_e
__hal_ring_create(
vxge_hal_vpath_h vpath_handle,
vxge_hal_ring_attr_t *attr);
void
__hal_ring_abort(
vxge_hal_ring_h ringh,
vxge_hal_reopen_e reopen);
vxge_hal_status_e
__hal_ring_reset(
vxge_hal_ring_h ringh);
void
__hal_ring_delete(
vxge_hal_vpath_h vpath_handle);
vxge_hal_status_e
vxge_hal_ring_initial_replenish(
__hal_ring_t *ring,
vxge_hal_reopen_e reopen);
vxge_hal_status_e
__hal_ring_frame_length_set(
__hal_virtualpath_t *vpath,
u32 new_frmlen);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_RING_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_SRPCIM_REGS_H
#define VXGE_HAL_SRPCIM_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_srpcim_reg_t {
/* 0x00000 */ u64 tim_mr2sr_resource_assignment_vh;
#define VXGE_HAL_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)\
vBIT(val, 0, 32)
u8 unused00100[0x00100 - 0x00008];
/* 0x00100 */ u64 srpcim_pcipif_int_status;
#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3)
#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7)
#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT\
mBIT(11)
/* 0x00108 */ u64 srpcim_pcipif_int_mask;
/* 0x00110 */ u64 mrpcim_msg_reg;
#define VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT mBIT(3)
/* 0x00118 */ u64 mrpcim_msg_mask;
/* 0x00120 */ u64 mrpcim_msg_alarm;
/* 0x00128 */ u64 vpath_msg_reg;
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT mBIT(0)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT mBIT(1)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT mBIT(2)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT mBIT(3)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT mBIT(4)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT mBIT(5)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT mBIT(6)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT mBIT(7)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT mBIT(8)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT mBIT(9)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT mBIT(10)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT mBIT(11)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT mBIT(12)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT mBIT(13)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT mBIT(14)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT mBIT(15)
#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT mBIT(16)
/* 0x00130 */ u64 vpath_msg_mask;
/* 0x00138 */ u64 vpath_msg_alarm;
u8 unused00158[0x00158 - 0x00140];
/* 0x00158 */ u64 vf_bargrp_no;
#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR0(val) vBIT(val, 11, 5)
#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR1(val) vBIT(val, 19, 5)
#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR2(val) vBIT(val, 26, 6)
#define VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val) vBIT(val, 32, 4)
#define VXGE_HAL_VF_BARGRP_NO_MASK(val) vBIT(val, 36, 4)
/* 0x00160 */ u64 srpcim_to_mrpcim_wmsg;
#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val)\
vBIT(val, 0, 64)
/* 0x00168 */ u64 srpcim_to_mrpcim_wmsg_trig;
#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG mBIT(0)
/* 0x00170 */ u64 mrpcim_to_srpcim_rmsg;
#define VXGE_HAL_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val)\
vBIT(val, 0, 64)
/* 0x00178 */ u64 vpath_to_srpcim_rmsg_sel;
#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val) vBIT(val, 0, 5)
/* 0x00180 */ u64 vpath_to_srpcim_rmsg;
#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val)\
vBIT(val, 0, 64)
u8 unused00200[0x00200 - 0x00188];
/* 0x00200 */ u64 srpcim_general_int_status;
#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0)
#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(3)
#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(7)
u8 unused00210[0x00210 - 0x00208];
/* 0x00210 */ u64 srpcim_general_int_mask;
#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0)
#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(3)
#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(7)
u8 unused00220[0x00220 - 0x00218];
/* 0x00220 */ u64 srpcim_ppif_int_status;
#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT\
mBIT(3)
#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM mBIT(7)
#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_VPATH_TO_SRPCIM_ALARM_INT mBIT(11)
/* 0x00228 */ u64 srpcim_ppif_int_mask;
/* 0x00230 */ u64 srpcim_gen_errors_reg;
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR mBIT(3)
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR mBIT(7)
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR mBIT(11)
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT mBIT(15)
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET mBIT(19)
#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS mBIT(23)
/* 0x00238 */ u64 srpcim_gen_errors_mask;
/* 0x00240 */ u64 srpcim_gen_errors_alarm;
/* 0x00248 */ u64 mrpcim_to_srpcim_alarm_reg;
#define VXGE_HAL_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM mBIT(3)
/* 0x00250 */ u64 mrpcim_to_srpcim_alarm_mask;
/* 0x00258 */ u64 mrpcim_to_srpcim_alarm_alarm;
/* 0x00260 */ u64 vpath_to_srpcim_alarm_reg;
#define VXGE_HAL_VPATH_TO_SRPCIM_ALARM_REG_PPIF_VPATH_TO_SRPCIM_ALARM(val)\
vBIT(val, 0, 17)
/* 0x00268 */ u64 vpath_to_srpcim_alarm_mask;
/* 0x00270 */ u64 vpath_to_srpcim_alarm_alarm;
u8 unused00280[0x00280 - 0x00278];
/* 0x00280 */ u64 pf_sw_reset;
#define VXGE_HAL_PF_SW_RESET_PF_SW_RESET(val) vBIT(val, 0, 8)
/* 0x00288 */ u64 srpcim_general_cfg1;
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN mBIT(19)
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN mBIT(23)
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(27)
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(31)
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(35)
#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(39)
/* 0x00290 */ u64 srpcim_interrupt_cfg1;
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7)
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vBIT(val, 9, 3)
/* 0x00298 */ u64 srpcim_interrupt_cfg2;
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_MSIX_FOR_SCHED_INT(val)\
vBIT(val, 1, 7)
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_ONE_SHOT mBIT(11)
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_TIMER_EN mBIT(15)
#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_INT_PERIOD(val) vBIT(val, 32, 32)
u8 unused002a8[0x002a8 - 0x002a0];
/* 0x002a8 */ u64 srpcim_clear_msix_mask;
#define VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK mBIT(0)
/* 0x002b0 */ u64 srpcim_set_msix_mask;
#define VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK mBIT(0)
/* 0x002b8 */ u64 srpcim_clr_msix_one_shot;
#define VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT mBIT(0)
/* 0x002c0 */ u64 srpcim_rst_in_prog;
#define VXGE_HAL_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG mBIT(7)
/* 0x002c8 */ u64 srpcim_reg_modified;
#define VXGE_HAL_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED mBIT(7)
/* 0x002d0 */ u64 tgt_pf_illegal_access;
#define VXGE_HAL_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7)
/* 0x002d8 */ u64 srpcim_msix_status;
#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK mBIT(3)
#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR mBIT(7)
u8 unused00318[0x00318 - 0x002e0];
/* 0x00318 */ u64 usdc_vpl;
#define VXGE_HAL_USDC_VPL_SGRP_OWN(val) vBIT(val, 0, 32)
u8 unused00600[0x00600 - 0x00320];
/* 0x00600 */ u64 one_cfg_sr_copy;
#define VXGE_HAL_ONE_CFG_SR_COPY_ONE_CFG_RDY mBIT(7)
/* 0x00608 */ u64 sgrp_allocated;
#define VXGE_HAL_SGRP_ALLOCATED_SGRP_ALLOC(val) vBIT(val, 0, 64)
/* 0x00610 */ u64 sgrp_iwarp_lro_allocated;
#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_ENABLE_IWARP mBIT(7)
#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_LAST_IWARP_SGRP(val) vBIT(val, 11, 5)
u8 unused00880[0x00880 - 0x00618];
/* 0x00880 */ u64 xgmac_sr_int_status;
#define VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT mBIT(3)
/* 0x00888 */ u64 xgmac_sr_int_mask;
/* 0x00890 */ u64 asic_ntwk_sr_err_reg;
#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT mBIT(3)
#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK mBIT(7)
#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED\
mBIT(11)
#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED mBIT(15)
/* 0x00898 */ u64 asic_ntwk_sr_err_mask;
/* 0x008a0 */ u64 asic_ntwk_sr_err_alarm;
u8 unused008c0[0x008c0 - 0x008a8];
/* 0x008c0 */ u64 xmac_vsport_choices_sr_clone;
#define VXGE_HAL_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val)\
vBIT(val, 0, 17)
u8 unused00900[0x00900 - 0x008c8];
/* 0x00900 */ u64 mr_rqa_top_prty_for_vh;
#define VXGE_HAL_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)\
vBIT(val, 59, 5)
/* 0x00908 */ u64 umq_vh_data_list_empty;
#define VXGE_HAL_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY mBIT(0)
/* 0x00910 */ u64 wde_cfg;
#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_START mBIT(0)
#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_END mBIT(1)
#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_START mBIT(2)
#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_END mBIT(3)
#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_START mBIT(4)
#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_END mBIT(5)
#define VXGE_HAL_WDE_CFG_NS0_MWB_OPT_EN mBIT(6)
#define VXGE_HAL_WDE_CFG_NS0_QB_OPT_EN mBIT(7)
#define VXGE_HAL_WDE_CFG_NS0_MPSB_OPT_EN mBIT(8)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_START mBIT(9)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_END mBIT(10)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_START mBIT(11)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_END mBIT(12)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_START mBIT(13)
#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_END mBIT(14)
#define VXGE_HAL_WDE_CFG_NS1_MWB_OPT_EN mBIT(15)
#define VXGE_HAL_WDE_CFG_NS1_QB_OPT_EN mBIT(16)
#define VXGE_HAL_WDE_CFG_NS1_MPSB_OPT_EN mBIT(17)
#define VXGE_HAL_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR mBIT(19)
#define VXGE_HAL_WDE_CFG_ALIGNMENT_PREFERENCE(val) vBIT(val, 30, 2)
#define VXGE_HAL_WDE_CFG_MEM_WORD_SIZE(val) vBIT(val, 46, 2)
} vxge_hal_srpcim_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_SRPCIM_REGS_H */

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sys/dev/vxge/vxgehal/vxgehal-srpcim.c Normal file
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@ -0,0 +1,787 @@
/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* __hal_srpcim_alarm_process - Process Alarms.
* @hldev: HAL Device
* @srpcim_id: srpcim index
* @skip_alarms: Flag to indicate if not to clear the alarms
*
* Process srpcim alarms.
*
*/
vxge_hal_status_e
__hal_srpcim_alarm_process(
__hal_device_t * hldev,
u32 srpcim_id,
u32 skip_alarms)
{
u64 val64;
u64 alarm_status;
u64 pic_status;
u64 xgmac_status;
vxge_hal_srpcim_reg_t *srpcim_reg;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim_irq("hldev = 0x"VXGE_OS_STXFMT,
(ptr_t) hldev);
srpcim_reg = hldev->srpcim_reg[srpcim_id];
alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->srpcim_general_int_status);
vxge_hal_info_log_srpcim_irq("alarm_status = 0x"VXGE_OS_STXFMT,
(ptr_t) alarm_status);
if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT) {
xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->xgmac_sr_int_status);
vxge_hal_info_log_srpcim_irq("xgmac_status = 0x"VXGE_OS_STXFMT,
(ptr_t) xgmac_status);
if (xgmac_status &
VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT) {
val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->asic_ntwk_sr_err_reg);
vxge_hal_info_log_srpcim_irq("asic_ntwk_sr_err_reg = \
0x"VXGE_OS_STXFMT, (ptr_t) val64);
if (!skip_alarms)
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->asic_ntwk_sr_err_reg);
}
}
if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT) {
pic_status = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->srpcim_ppif_int_status);
vxge_hal_info_log_srpcim_irq("pic_status = 0x"VXGE_OS_STXFMT,
(ptr_t) pic_status);
if (pic_status &
VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT) {
val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->srpcim_gen_errors_reg);
vxge_hal_info_log_srpcim_irq("srpcim_gen_errors_reg = \
0x"VXGE_OS_STXFMT, (ptr_t) val64);
if (!skip_alarms)
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_gen_errors_reg);
}
if (pic_status &
VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM) {
val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->mrpcim_to_srpcim_alarm_reg);
vxge_hal_info_log_srpcim_irq("mrpcim_to_srpcim_alarm_reg = \
0x"VXGE_OS_STXFMT, (ptr_t) val64);
if (!skip_alarms)
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->mrpcim_to_srpcim_alarm_reg);
}
}
if (alarm_status & ~(
VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT |
VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT)) {
vxge_hal_trace_log_srpcim_irq("%s:%s:%d Unknown Alarm",
__FILE__, __func__, __LINE__);
}
vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* vxge_hal_srpcim_alarm_process - Process srpcim Alarms.
* @devh: Device Handle.
* @skip_alarms: Flag to indicate if not to clear the alarms
*
* Process srpcim alarms.
*
*/
vxge_hal_status_e
vxge_hal_srpcim_alarm_process(
vxge_hal_device_h devh,
u32 skip_alarms)
{
u32 i;
u64 val64;
vxge_hal_status_e status = VXGE_HAL_OK;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim_irq("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
vxge_hal_trace_log_srpcim_irq("srpcim_to_mrpcim_alarm_reg = \
0x"VXGE_OS_STXFMT, (ptr_t) val64);
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
if (val64 & mBIT(i)) {
status = __hal_srpcim_alarm_process(hldev,
i, skip_alarms);
}
}
if (!skip_alarms)
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_INTR_MASK_ALL,
&hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
} else {
status = __hal_srpcim_alarm_process(hldev,
hldev->srpcim_id, skip_alarms);
}
vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* __hal_srpcim_intr_enable - Enable srpcim interrupts.
* @hldev: Hal Device.
* @srpcim_id: SRPCIM Id
*
* Enable srpcim interrupts.
*
* See also: __hal_srpcim_intr_disable()
*/
vxge_hal_status_e
__hal_srpcim_intr_enable(
__hal_device_t * hldev,
u32 srpcim_id)
{
vxge_hal_srpcim_reg_t *srpcim_reg;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
(ptr_t) hldev);
srpcim_reg = hldev->srpcim_reg[srpcim_id];
vxge_os_pio_mem_write64(hldev->header.pdev,
hldev->header.regh0,
VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_gen_errors_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->mrpcim_to_srpcim_alarm_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->vpath_to_srpcim_alarm_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_ppif_int_status);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->mrpcim_msg_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->vpath_msg_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_pcipif_int_status);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->asic_ntwk_sr_err_reg);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->xgmac_sr_int_status);
vxge_os_pio_mem_read64(hldev->header.pdev,
hldev->header.regh0,
&srpcim_reg->srpcim_general_int_status);
/* Unmask the individual interrupts. */
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
0,
&srpcim_reg->vpath_msg_mask);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
0,
&srpcim_reg->srpcim_pcipif_int_mask);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(~VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT, 0),
&srpcim_reg->srpcim_general_int_mask);
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* vxge_hal_srpcim_intr_enable - Enable srpcim interrupts.
* @devh: Hal Device.
*
* Enable srpcim interrupts.
*
* See also: vxge_hal_srpcim_intr_disable()
*/
vxge_hal_status_e
vxge_hal_srpcim_intr_enable(
vxge_hal_device_h devh)
{
u32 i;
vxge_hal_status_e status;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
status = __hal_srpcim_intr_enable(hldev, i);
}
} else {
status = __hal_srpcim_intr_enable(hldev, hldev->srpcim_id);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* __hal_srpcim_intr_disable - Disable srpcim interrupts.
* @hldev: Hal Device.
* @srpcim_id: SRPCIM Id
*
* Disable srpcim interrupts.
*
* See also: __hal_srpcim_intr_enable()
*/
vxge_hal_status_e
__hal_srpcim_intr_disable(
__hal_device_t * hldev,
u32 srpcim_id)
{
vxge_hal_srpcim_reg_t *srpcim_reg;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
(ptr_t) hldev);
srpcim_reg = hldev->srpcim_reg[srpcim_id];
/* Mask the individual interrupts. */
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->vpath_msg_mask);
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_pcipif_int_mask);
vxge_hal_pio_mem_write32_upper(
hldev->header.pdev,
hldev->header.regh0,
(u32) VXGE_HAL_INTR_MASK_ALL,
&srpcim_reg->srpcim_general_int_mask);
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* vxge_hal_srpcim_intr_disable - Disable srpcim interrupts.
* @devh: Hal Device.
*
* Disable srpcim interrupts.
*
* See also: vxge_hal_srpcim_intr_enable()
*/
vxge_hal_status_e
vxge_hal_srpcim_intr_disable(
vxge_hal_device_h devh)
{
u32 i;
vxge_hal_status_e status;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
status = __hal_srpcim_intr_disable(hldev, i);
}
} else {
status = __hal_srpcim_intr_disable(hldev, hldev->srpcim_id);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm
* @hldev: HAL device.
* @alarm_msix_id: MSIX vector for alarm.
*
* This API will associate a given MSIX vector numbers with srpcim alarm
*/
vxge_hal_status_e
vxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id)
{
u32 i;
vxge_hal_status_e status = VXGE_HAL_OK;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
alarm_msix_id),
0),
&hldev->srpcim_reg[i]->srpcim_interrupt_cfg1);
}
} else {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
alarm_msix_id),
0),
&hldev->srpcim_reg[hldev->srpcim_id]->
srpcim_interrupt_cfg1);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* vxge_hal_srpcim_msix_mask - Mask MSIX Vector.
* @hldev: HAL device.
*
* The function masks the srpcim msix interrupt
*
*/
void
vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh)
{
u32 i;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return;
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
0),
&hldev->srpcim_reg[i]->srpcim_set_msix_mask);
}
} else {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
0),
&hldev->srpcim_reg[hldev->srpcim_id]->srpcim_set_msix_mask);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* vxge_hal_srpcim_msix_clear - Clear MSIX Vector.
* @hldev: HAL device.
*
* The function clears the srpcim msix interrupt
*
*/
void
vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh)
{
u32 i;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return;
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
0),
&hldev->srpcim_reg[i]->srpcim_clear_msix_mask);
}
} else {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
0),
&hldev->srpcim_reg[hldev->srpcim_id]->
srpcim_clear_msix_mask);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector.
* @hldev: HAL device.
*
* The function unmasks the srpcim msix interrupt
*
*/
void
vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh)
{
u32 i;
__hal_device_t *hldev = (__hal_device_t *) devh;
vxge_assert(devh != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
(ptr_t) devh);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return;
}
if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
0),
&hldev->srpcim_reg[i]->srpcim_clr_msix_one_shot);
}
} else {
vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
hldev->header.regh0,
(u32) bVAL32(
VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
0),
&hldev->srpcim_reg[hldev->srpcim_id]->
srpcim_clr_msix_one_shot);
}
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
}
/*
* __hal_srpcim_initialize - Initialize srpcim.
* @hldev: HAL Device
*
* Initialize srpcim.
*
*/
vxge_hal_status_e
__hal_srpcim_initialize(
__hal_device_t * hldev)
{
vxge_assert(hldev != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
(ptr_t) hldev);
if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__,
VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
}
hldev->srpcim = (__hal_srpcim_t *)
vxge_os_malloc(hldev->header.pdev, sizeof(__hal_srpcim_t));
if (hldev->srpcim == NULL) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
return (VXGE_HAL_ERR_OUT_OF_MEMORY);
}
vxge_os_memzero(hldev->srpcim, sizeof(__hal_srpcim_t));
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}
/*
* __hal_srpcim_terminate - Terminate srpcim.
* @hldev: HAL Device
*
* Terminate srpcim.
*
*/
vxge_hal_status_e
__hal_srpcim_terminate(
__hal_device_t * hldev)
{
vxge_hal_status_e status = VXGE_HAL_OK;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_srpcim("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
(ptr_t) hldev);
if (hldev->srpcim == NULL) {
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
vxge_os_free(hldev->header.pdev,
hldev->srpcim, sizeof(__hal_srpcim_t));
hldev->srpcim = NULL;
vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}

84
sys/dev/vxge/vxgehal/vxgehal-srpcim.h Normal file
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@ -0,0 +1,84 @@
/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_SRPCIM_H
#define VXGE_HAL_SRPCIM_H
__EXTERN_BEGIN_DECLS
/*
* __hal_srpcim_vpath_t
*
* HAL srpcim vpath messaging state.
*/
typedef struct __hal_srpcim_vpath_t {
u32 registered;
u32 srpcim_id;
} __hal_srpcim_vpath_t;
/*
* __hal_srpcim_t
*
* HAL srpcim object. Represents privileged mode srpcim device.
*/
typedef struct __hal_srpcim_t {
__hal_srpcim_vpath_t vpath_state[VXGE_HAL_MAX_VIRTUAL_PATHS];
} __hal_srpcim_t;
vxge_hal_status_e
__hal_srpcim_alarm_process(
__hal_device_t *hldev,
u32 srpcim_id,
u32 skip_alarms);
vxge_hal_status_e
__hal_srpcim_intr_enable(
__hal_device_t *hldev,
u32 srpcim_id);
vxge_hal_status_e
__hal_srpcim_intr_disable(
__hal_device_t *hldev,
u32 srpcim_id);
vxge_hal_status_e
__hal_srpcim_initialize(
__hal_device_t *hldev);
vxge_hal_status_e
__hal_srpcim_terminate(
__hal_device_t *hldev);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_SRPCIM_H */

243
sys/dev/vxge/vxgehal/vxgehal-swapper.c Normal file
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@ -0,0 +1,243 @@
/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#include <dev/vxge/vxgehal/vxgehal.h>
/*
* _hal_legacy_swapper_set - Set the swapper bits for the legacy secion.
* @pdev: PCI device object.
* @regh: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
* (Linux and the rest.)
* @legacy_reg: Address of the legacy register space.
*
* Set the swapper bits appropriately for the lagacy section.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_SWAPPER_CTRL - failed.
*
* See also: vxge_hal_status_e {}.
*/
vxge_hal_status_e
__hal_legacy_swapper_set(
pci_dev_h pdev,
pci_reg_h regh,
vxge_hal_legacy_reg_t *legacy_reg)
{
u64 val64;
vxge_hal_status_e status;
vxge_assert(legacy_reg != NULL);
vxge_hal_trace_log_driver("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_driver(
"pdev = 0x"VXGE_OS_STXFMT", regh = 0x"VXGE_OS_STXFMT", "
"legacy_reg = 0x"VXGE_OS_STXFMT, (ptr_t) pdev, (ptr_t) regh,
(ptr_t) legacy_reg);
val64 = vxge_os_pio_mem_read64(pdev, regh, &legacy_reg->toc_swapper_fb);
vxge_hal_info_log_driver("TOC Swapper Fb: 0x"VXGE_OS_LLXFMT, val64);
vxge_os_wmb();
switch (val64) {
case VXGE_HAL_SWAPPER_INITIAL_VALUE:
return (VXGE_HAL_OK);
case VXGE_HAL_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE,
&legacy_reg->pifm_rd_swap_en);
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE,
&legacy_reg->pifm_rd_flip_en);
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
&legacy_reg->pifm_wr_swap_en);
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE,
&legacy_reg->pifm_wr_flip_en);
break;
case VXGE_HAL_SWAPPER_BYTE_SWAPPED:
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE,
&legacy_reg->pifm_rd_swap_en);
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
&legacy_reg->pifm_wr_swap_en);
break;
case VXGE_HAL_SWAPPER_BIT_FLIPPED:
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE,
&legacy_reg->pifm_rd_flip_en);
vxge_os_pio_mem_write64(pdev, regh,
VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE,
&legacy_reg->pifm_wr_flip_en);
break;
}
vxge_os_wmb();
val64 = vxge_os_pio_mem_read64(pdev, regh, &legacy_reg->toc_swapper_fb);
if (val64 == VXGE_HAL_SWAPPER_INITIAL_VALUE) {
status = VXGE_HAL_OK;
} else {
vxge_hal_err_log_driver("%s:TOC Swapper setting failed",
__func__);
status = VXGE_HAL_ERR_SWAPPER_CTRL;
}
vxge_hal_info_log_driver("TOC Swapper Fb: 0x"VXGE_OS_LLXFMT, val64);
vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
__FILE__, __func__, __LINE__, status);
return (status);
}
/*
* __hal_vpath_swapper_set - Set the swapper bits for the vpath.
* @hldev: HAL device object.
* @vp_id: Vpath Id
*
* Set the swapper bits appropriately for the vpath.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_SWAPPER_CTRL - failed.
*
* See also: vxge_hal_status_e {}.
*/
vxge_hal_status_e
__hal_vpath_swapper_set(
vxge_hal_device_t *hldev,
u32 vp_id)
{
#if !defined(VXGE_OS_HOST_BIG_ENDIAN)
u64 val64;
vxge_hal_vpath_reg_t *vpath_reg;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_vpath("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_vpath(
"hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
(ptr_t) hldev, vp_id);
vpath_reg = ((__hal_device_t *) hldev)->vpath_reg[vp_id];
val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
&vpath_reg->vpath_general_cfg1);
vxge_os_wmb();
val64 |= VXGE_HAL_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
vxge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
val64,
&vpath_reg->vpath_general_cfg1);
vxge_os_wmb();
vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
#endif
return (VXGE_HAL_OK);
}
/*
* __hal_kdfc_swapper_set - Set the swapper bits for the kdfc.
* @hldev: HAL device object.
* @vp_id: Vpath Id
*
* Set the swapper bits appropriately for the vpath.
*
* Returns: VXGE_HAL_OK - success.
* VXGE_HAL_ERR_SWAPPER_CTRL - failed.
*
* See also: vxge_hal_status_e {}.
*/
vxge_hal_status_e
__hal_kdfc_swapper_set(
vxge_hal_device_t *hldev,
u32 vp_id)
{
u64 val64;
vxge_hal_vpath_reg_t *vpath_reg;
vxge_hal_legacy_reg_t *legacy_reg;
vxge_assert(hldev != NULL);
vxge_hal_trace_log_vpath("==> %s:%s:%d",
__FILE__, __func__, __LINE__);
vxge_hal_trace_log_vpath("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
(ptr_t) hldev, vp_id);
vpath_reg = ((__hal_device_t *) hldev)->vpath_reg[vp_id];
legacy_reg = ((__hal_device_t *) hldev)->legacy_reg;
val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
&legacy_reg->pifm_wr_swap_en);
if (val64 == VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
&vpath_reg->kdfcctl_cfg0);
vxge_os_wmb();
val64 |= VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
vxge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
val64,
&vpath_reg->kdfcctl_cfg0);
vxge_os_wmb();
}
vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
__FILE__, __func__, __LINE__);
return (VXGE_HAL_OK);
}

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_SWAPPER_H
#define VXGE_HAL_SWAPPER_H
__EXTERN_BEGIN_DECLS
#define VXGE_HAL_SWAPPER_INITIAL_VALUE 0x0123456789abcdefULL
#define VXGE_HAL_SWAPPER_BYTE_SWAPPED 0xefcdab8967452301ULL
#define VXGE_HAL_SWAPPER_BIT_FLIPPED 0x80c4a2e691d5b3f7ULL
#define VXGE_HAL_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED 0xf7b3d591e6a2c480ULL
#define VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_SWAPPER_READ_BYTE_SWAP_DISABLE 0x0000000000000000ULL
#define VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_SWAPPER_READ_BIT_FLAP_DISABLE 0x0000000000000000ULL
#define VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_DISABLE 0x0000000000000000ULL
#define VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL
#define VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_DISABLE 0x0000000000000000ULL
vxge_hal_status_e
__hal_legacy_swapper_set(
pci_dev_h pdev,
pci_reg_h regh,
vxge_hal_legacy_reg_t *legacy_reg);
vxge_hal_status_e
__hal_vpath_swapper_set(
vxge_hal_device_t *hldev,
u32 vp_id);
vxge_hal_status_e
__hal_kdfc_swapper_set(
vxge_hal_device_t *hldev,
u32 vp_id);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_SWAPPER_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_TOC_REGS_H
#define VXGE_HAL_TOC_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_toc_reg_t {
u8 unused00050[0x00050];
/* 0x00050 */ u64 toc_common_pointer;
#define VXGE_HAL_TOC_COMMON_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
/* 0x00058 */ u64 toc_memrepair_pointer;
#define VXGE_HAL_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
/* 0x00060 */ u64 toc_pcicfgmgmt_pointer[17];
#define VXGE_HAL_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
u8 unused001e0[0x001e0 - 0x000e8];
/* 0x001e0 */ u64 toc_mrpcim_pointer;
#define VXGE_HAL_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
/* 0x001e8 */ u64 toc_srpcim_pointer[17];
#define VXGE_HAL_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
u8 unused00278[0x00278 - 0x00270];
/* 0x00278 */ u64 toc_vpmgmt_pointer[17];
#define VXGE_HAL_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
u8 unused00390[0x00390 - 0x00300];
/* 0x00390 */ u64 toc_vpath_pointer[17];
#define VXGE_HAL_TOC_VPATH_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
u8 unused004a0[0x004a0 - 0x00418];
/* 0x004a0 */ u64 toc_kdfc;
#define VXGE_HAL_TOC_KDFC_INITIAL_OFFSET(val) vBIT(val, 0, 61)
#define VXGE_HAL_TOC_KDFC_INITIAL_BIR(val) vBIT(val, 61, 3)
/* 0x004a8 */ u64 toc_usdc;
#define VXGE_HAL_TOC_USDC_INITIAL_OFFSET(val) vBIT(val, 0, 61)
#define VXGE_HAL_TOC_USDC_INITIAL_BIR(val) vBIT(val, 61, 3)
/* 0x004b0 */ u64 toc_kdfc_vpath_stride;
#define VXGE_HAL_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val)\
vBIT(val, 0, 64)
/* 0x004b8 */ u64 toc_kdfc_fifo_stride;
#define VXGE_HAL_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val)\
vBIT(val, 0, 64)
} vxge_hal_toc_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_TOC_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_VIRTUALPATH_H
#define VXGE_HAL_VIRTUALPATH_H
__EXTERN_BEGIN_DECLS
struct __hal_device_t;
/*
* struct __hal_virtualpath_t - Virtual Path
*
* @vp_id: Virtual path id
* @vp_open: This flag specifies if vxge_hal_vp_open is called from LL Driver
* @hldev: Hal device
* @vp_config: Virtual Path Config
* @vp_reg: VPATH Register map address in BAR0
* @vpmgmt_reg: VPATH_MGMT register map address
* @is_first_vpath: 1 if this first vpath in this vfunc, 0 otherwise
* @promisc_en: Promisc mode state flag.
* @min_bandwidth: Guaranteed Band Width in Mbps
* @max_bandwidth: Maximum Band Width in Mbps
* @max_mtu: Max mtu that can be supported
* @sess_grps_available: The mask of available session groups for this vpath
* @bmap_root_assigned: The bitmap root for this vpath
* @vsport_choices: The mask of vsports that are available for this vpath
* @vsport_number: vsport attached to this vpath
* @sess_grp_start: Session oid start
* @sess_grp_end: session oid end
* @max_kdfc_db: Maximum kernel mode doorbells
* @max_nofl_db: Maximum non offload doorbells
* @max_ofl_db: Maximum offload doorbells
* @max_msg_db: Maximum message doorbells
* @rxd_mem_size: Maximum RxD memory size
* @tx_intr_num: Interrupt Number associated with the TX
* @rx_intr_num: Interrupt Number associated with the RX
* @einta_intr_num: Interrupt Number associated with Emulated MSIX DeAssert IntA
* @bmap_intr_num: Interrupt Number associated with the bitmap
* @nce_oid_db: NCE ID database
* @session_oid_db: Session Object Id database
* @active_lros: Active LRO session list
* @active_lro_count: Active LRO count
* @free_lros: Free LRO session list
* @free_lro_count: Free LRO count
* @lro_lock: LRO session lists' lock
* @sqs: List of send queues
* @sq_lock: Lock for operations on sqs
* @srqs: List of SRQs
* @srq_lock: Lock for operations on srqs
* @srq_oid_db: DRQ object id database
* @cqrqs: CQRQs
* @cqrq_lock: Lock for operations on cqrqs
* @cqrq_oid_db: CQRQ object id database
* @umqh: UP Message Queue
* @dmqh: Down Message Queue
* @umq_dmq_ir: The adapter will overwrite and update this location as Messages
* are read from DMQ and written into UMQ.
* @umq_dmq_ir_reg_entry: Reg entry of umq_dmq_ir_t
* @ringh: Ring Queue
* @fifoh: FIFO Queue
* @vpath_handles: Virtual Path handles list
* @vpath_handles_lock: Lock for operations on Virtual Path handles list
* @stats_block: Memory for DMAing stats
* @stats: Vpath statistics
*
* Virtual path structure to encapsulate the data related to a virtual path.
* Virtual paths are allocated by the HAL upon getting configuration from the
* driver and inserted into the list of virtual paths.
*/
typedef struct __hal_virtualpath_t {
u32 vp_id;
u32 vp_open;
#define VXGE_HAL_VP_NOT_OPEN 0
#define VXGE_HAL_VP_OPEN 1
struct __hal_device_t *hldev;
vxge_hal_vp_config_t *vp_config;
vxge_hal_vpath_reg_t *vp_reg;
vxge_hal_vpmgmt_reg_t *vpmgmt_reg;
__hal_non_offload_db_wrapper_t *nofl_db;
__hal_messaging_db_wrapper_t *msg_db;
u32 is_first_vpath;
u32 promisc_en;
#define VXGE_HAL_VP_PROMISC_ENABLE 1
#define VXGE_HAL_VP_PROMISC_DISABLE 0
u32 min_bandwidth;
u32 max_bandwidth;
u32 max_mtu;
u64 sess_grps_available;
u32 bmap_root_assigned;
u32 vsport_choices;
u32 vsport_number;
u32 sess_grp_start;
u32 sess_grp_end;
u32 max_kdfc_db;
u32 max_nofl_db;
u32 max_ofl_db;
u32 max_msg_db;
u32 rxd_mem_size;
u32 tx_intr_num;
u32 rx_intr_num;
u32 einta_intr_num;
u32 bmap_intr_num;
u64 tim_tti_cfg1_saved;
u64 tim_tti_cfg3_saved;
u64 tim_rti_cfg1_saved;
u64 tim_rti_cfg3_saved;
vxge_hal_ring_h ringh;
vxge_hal_fifo_h fifoh;
vxge_list_t vpath_handles;
spinlock_t vpath_handles_lock;
__hal_blockpool_entry_t *stats_block;
vxge_hal_vpath_stats_hw_info_t *hw_stats;
vxge_hal_vpath_stats_hw_info_t *hw_stats_sav;
vxge_hal_vpath_stats_sw_info_t *sw_stats;
} __hal_virtualpath_t;
/*
* struct __hal_vpath_handle_t - List item to store callback information
* @item: List head to keep the item in linked list
* @vpath: Virtual path to which this item belongs
* @cb_fn: Callback function to be called
* @client_handle: Client handle to be returned with the callback
*
* This structure is used to store the callback information.
*/
typedef struct __hal_vpath_handle_t {
vxge_list_t item;
__hal_virtualpath_t *vpath;
vxge_hal_vpath_callback_f cb_fn;
vxge_hal_client_h client_handle;
} __hal_vpath_handle_t;
#define VXGE_HAL_VIRTUAL_PATH_HANDLE(vpath) \
((vxge_hal_vpath_h)(vpath)->vpath_handles.next)
#define VXGE_HAL_VPATH_STATS_PIO_READ(offset) { \
status = __hal_vpath_stats_access(vpath, \
VXGE_HAL_STATS_OP_READ, \
offset, \
&val64); \
if (status != VXGE_HAL_OK) { \
vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", \
__FILE__, __func__, __LINE__, status); \
return (status); \
} \
}
vxge_hal_status_e
__hal_vpath_size_quantum_set(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_mgmt_read(
struct __hal_device_t *hldev,
__hal_virtualpath_t *vpath);
vxge_hal_status_e
__hal_vpath_pci_read(
struct __hal_device_t *hldev,
u32 vp_id,
u32 offset,
u32 length,
void *val);
vxge_hal_status_e
__hal_vpath_reset_check(
__hal_virtualpath_t *vpath);
vxge_hal_status_e
__hal_vpath_fw_memo_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
u32 action,
u64 param_index,
u64 *data0,
u64 *data1);
vxge_hal_status_e
__hal_vpath_fw_flash_ver_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
vxge_hal_device_version_t *fw_version,
vxge_hal_device_date_t *fw_date,
vxge_hal_device_version_t *flash_version,
vxge_hal_device_date_t *flash_date);
vxge_hal_status_e
__hal_vpath_card_info_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
u8 *serial_number,
u8 *part_number,
u8 *product_description);
vxge_hal_status_e
__hal_vpath_pmd_info_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
u32 *ports,
vxge_hal_device_pmd_info_t *pmd_port0,
vxge_hal_device_pmd_info_t *pmd_port1);
u64
__hal_vpath_pci_func_mode_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg);
vxge_hal_device_lag_mode_e
__hal_vpath_lag_mode_get(
__hal_virtualpath_t *vpath);
u64
__hal_vpath_vpath_map_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
u32 vh,
u32 func,
vxge_hal_vpath_reg_t *vpath_reg);
vxge_hal_status_e
__hal_vpath_fw_upgrade(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
u8 *buffer,
u32 length);
vxge_hal_status_e
__hal_vpath_pcie_func_mode_set(
struct __hal_device_t *hldev,
u32 vp_id,
u32 func_mode);
vxge_hal_status_e
__hal_vpath_flick_link_led(
struct __hal_device_t *hldev,
u32 vp_id,
u32 port,
u32 on_off);
vxge_hal_status_e
__hal_vpath_udp_rth_set(
struct __hal_device_t *hldev,
u32 vp_id,
u32 on_off);
vxge_hal_status_e
__hal_vpath_rts_table_get(
vxge_hal_vpath_h vpath_handle,
u32 action,
u32 rts_table,
u32 offset,
u64 *data1,
u64 *data2);
vxge_hal_status_e
__hal_vpath_rts_table_set(
vxge_hal_vpath_h vpath_handle,
u32 action,
u32 rts_table,
u32 offset,
u64 data1,
u64 data2);
vxge_hal_status_e
__hal_vpath_hw_reset(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_sw_reset(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_prc_configure(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_kdfc_configure(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_mac_configure(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_tim_configure(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_hw_initialize(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vp_initialize(
vxge_hal_device_h devh,
u32 vp_id,
vxge_hal_vp_config_t *config);
void
__hal_vp_terminate(
vxge_hal_device_h devh,
u32 vp_id);
vxge_hal_status_e
__hal_vpath_hw_addr_get(
pci_dev_h pdev,
pci_reg_h regh0,
u32 vp_id,
vxge_hal_vpath_reg_t *vpath_reg,
macaddr_t macaddr,
macaddr_t macaddr_mask);
vxge_hal_status_e
__hal_vpath_intr_enable(
__hal_virtualpath_t *vpath);
vxge_hal_status_e
__hal_vpath_intr_disable(
__hal_virtualpath_t *vpath);
vxge_hal_device_link_state_e
__hal_vpath_link_state_test(
__hal_virtualpath_t *vpath);
vxge_hal_device_link_state_e
__hal_vpath_link_state_poll(
__hal_virtualpath_t *vpath);
vxge_hal_device_data_rate_e
__hal_vpath_data_rate_poll(
__hal_virtualpath_t *vpath);
vxge_hal_status_e
__hal_vpath_alarm_process(
__hal_virtualpath_t *vpath,
u32 skip_alarms);
vxge_hal_status_e
__hal_vpath_stats_access(
__hal_virtualpath_t *vpath,
u32 operation,
u32 offset,
u64 *stat);
vxge_hal_status_e
__hal_vpath_xmac_tx_stats_get(
__hal_virtualpath_t *vpath,
vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats);
vxge_hal_status_e
__hal_vpath_xmac_rx_stats_get(
__hal_virtualpath_t *vpath,
vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats);
vxge_hal_status_e
__hal_vpath_hw_stats_get(
__hal_virtualpath_t *vpath,
vxge_hal_vpath_stats_hw_info_t *hw_stats);
__EXTERN_END_DECLS
#endif /* VXGE_HAL_VIRTUALPATH_H */

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sys/dev/vxge/vxgehal/vxgehal-vpath-reg.h Normal file
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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_VPATH_REGS_H
#define VXGE_HAL_VPATH_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_vpath_reg_t {
u8 unused00300[0x00300];
/* 0x00300 */ u64 usdc_vpath;
#define VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(val) vBIT(val, 0, 32)
u8 unused00a00[0x00a00 - 0x00308];
/* 0x00a00 */ u64 wrdma_alarm_status;
#define VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT mBIT(1)
/* 0x00a08 */ u64 wrdma_alarm_mask;
u8 unused00a30[0x00a30 - 0x00a10];
/* 0x00a30 */ u64 prc_alarm_reg;
#define VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP mBIT(0)
#define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR mBIT(1)
#define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT mBIT(2)
#define VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR mBIT(3)
/* 0x00a38 */ u64 prc_alarm_mask;
/* 0x00a40 */ u64 prc_alarm_alarm;
/* 0x00a48 */ u64 prc_cfg1;
#define VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(val) vBIT(val, 3, 29)
#define VXGE_HAL_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE mBIT(34)
#define VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE mBIT(35)
#define VXGE_HAL_PRC_CFG1_GREEDY_RETURN mBIT(36)
#define VXGE_HAL_PRC_CFG1_QUICK_SHOT mBIT(37)
#define VXGE_HAL_PRC_CFG1_RX_TIMER_CI mBIT(39)
#define VXGE_HAL_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vBIT(val, 40, 2)
u8 unused00a60[0x00a60 - 0x00a50];
/* 0x00a60 */ u64 prc_cfg4;
#define VXGE_HAL_PRC_CFG4_IN_SVC mBIT(7)
#define VXGE_HAL_PRC_CFG4_RING_MODE(val) vBIT(val, 14, 2)
#define VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP mBIT(22)
#define VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP mBIT(23)
#define VXGE_HAL_PRC_CFG4_RTH_DISABLE mBIT(31)
#define VXGE_HAL_PRC_CFG4_IGNORE_OWNERSHIP mBIT(32)
#define VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW mBIT(36)
#define VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT mBIT(37)
#define VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(val) vBIT(val, 40, 24)
/* 0x00a68 */ u64 prc_cfg5;
#define VXGE_HAL_PRC_CFG5_RXD0_ADD(val) vBIT(val, 0, 61)
/* 0x00a70 */ u64 prc_cfg6;
#define VXGE_HAL_PRC_CFG6_FRM_PAD_EN mBIT(0)
#define VXGE_HAL_PRC_CFG6_QSIZE_ALIGNED_RXD mBIT(2)
#define VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN mBIT(5)
#define VXGE_HAL_PRC_CFG6_L3_CPC_TRSFR_CODE_EN mBIT(8)
#define VXGE_HAL_PRC_CFG6_L4_CPC_TRSFR_CODE_EN mBIT(9)
#define VXGE_HAL_PRC_CFG6_RXD_CRXDT(val) vBIT(val, 23, 9)
#define VXGE_HAL_PRC_CFG6_RXD_SPAT(val) vBIT(val, 36, 9)
/* 0x00a78 */ u64 prc_cfg7;
#define VXGE_HAL_PRC_CFG7_SCATTER_MODE(val) vBIT(val, 6, 2)
#define VXGE_HAL_PRC_CFG7_SMART_SCAT_EN mBIT(11)
#define VXGE_HAL_PRC_CFG7_RXD_NS_CHG_EN mBIT(12)
#define VXGE_HAL_PRC_CFG7_NO_HDR_SEPARATION mBIT(14)
#define VXGE_HAL_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vBIT(val, 20, 4)
#define VXGE_HAL_PRC_CFG7_BUFF_SIZE0_MASK(val) vBIT(val, 27, 5)
/* 0x00a80 */ u64 tim_dest_addr;
#define VXGE_HAL_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vBIT(val, 0, 64)
/* 0x00a88 */ u64 prc_rxd_doorbell;
#define VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vBIT(val, 48, 16)
/* 0x00a90 */ u64 rqa_prty_for_vp;
#define VXGE_HAL_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vBIT(val, 59, 5)
/* 0x00a98 */ u64 rxdmem_size;
#define VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vBIT(val, 51, 13)
/* 0x00aa0 */ u64 frm_in_progress_cnt;
#define VXGE_HAL_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val)\
vBIT(val, 59, 5)
/* 0x00aa8 */ u64 rx_multi_cast_stats;
#define VXGE_HAL_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vBIT(val, 48, 16)
/* 0x00ab0 */ u64 rx_frm_transferred;
#define VXGE_HAL_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) vBIT(val, 32, 32)
/* 0x00ab8 */ u64 rxd_returned;
#define VXGE_HAL_RXD_RETURNED_RXD_RETURNED(val) vBIT(val, 48, 16)
u8 unused00c00[0x00c00 - 0x00ac0];
/* 0x00c00 */ u64 kdfc_fifo_trpl_partition;
#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vBIT(val, 17, 15)
#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vBIT(val, 33, 15)
#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vBIT(val, 49, 15)
/* 0x00c08 */ u64 kdfc_fifo_trpl_ctrl;
#define VXGE_HAL_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE mBIT(7)
/* 0x00c10 */ u64 kdfc_trpl_fifo_0_ctrl;
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vBIT(val, 14, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN mBIT(22)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN mBIT(23)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vBIT(val, 26, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC mBIT(28)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD mBIT(29)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP mBIT(30)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD mBIT(31)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vBIT(val, 32, 8)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vBIT(val, 41, 7)
#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vBIT(val, 48, 16)
/* 0x00c18 */ u64 kdfc_trpl_fifo_1_ctrl;
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vBIT(val, 14, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN mBIT(22)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN mBIT(23)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vBIT(val, 26, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC mBIT(28)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD mBIT(29)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP mBIT(30)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD mBIT(31)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vBIT(val, 32, 8)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vBIT(val, 41, 7)
#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vBIT(val, 48, 16)
/* 0x00c20 */ u64 kdfc_trpl_fifo_2_ctrl;
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN mBIT(22)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN mBIT(23)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vBIT(val, 26, 2)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC mBIT(28)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD mBIT(29)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP mBIT(30)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD mBIT(31)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vBIT(val, 32, 8)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vBIT(val, 41, 7)
#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vBIT(val, 48, 16)
/* 0x00c28 */ u64 kdfc_trpl_fifo_0_wb_address;
#define VXGE_HAL_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vBIT(val, 0, 64)
/* 0x00c30 */ u64 kdfc_trpl_fifo_1_wb_address;
#define VXGE_HAL_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vBIT(val, 0, 64)
/* 0x00c38 */ u64 kdfc_trpl_fifo_2_wb_address;
#define VXGE_HAL_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vBIT(val, 0, 64)
/* 0x00c40 */ u64 kdfc_trpl_fifo_offset;
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vBIT(val, 1, 15)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vBIT(val, 17, 15)
#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vBIT(val, 33, 15)
/* 0x00c48 */ u64 kdfc_drbl_triplet_total;
#define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) vBIT(val, 17, 15)
u8 unused00c60[0x00c60 - 0x00c50];
/* 0x00c60 */ u64 usdc_drbl_ctrl;
#define VXGE_HAL_USDC_DRBL_CTRL_FLIP_EN mBIT(22)
#define VXGE_HAL_USDC_DRBL_CTRL_SWAP_EN mBIT(23)
/* 0x00c68 */ u64 usdc_vp_ready;
#define VXGE_HAL_USDC_VP_READY_USDC_HTN_READY mBIT(7)
#define VXGE_HAL_USDC_VP_READY_USDC_SRQ_READY mBIT(15)
#define VXGE_HAL_USDC_VP_READY_USDC_CQRQ_READY mBIT(23)
/* 0x00c70 */ u64 kdfc_status;
#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_0_READY mBIT(0)
#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_1_READY mBIT(1)
#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_2_READY mBIT(2)
u8 unused00c80[0x00c80 - 0x00c78];
/* 0x00c80 */ u64 xmac_rpa_vcfg;
#define VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH mBIT(3)
#define VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH mBIT(7)
#define VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH mBIT(11)
#define VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH mBIT(15)
#define VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF mBIT(19)
#define VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG mBIT(23)
/* 0x00c88 */ u64 rxmac_vcfg0;
#define VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vBIT(val, 2, 14)
#define VXGE_HAL_RXMAC_VCFG0_RTS_USE_MIN_LEN mBIT(19)
#define VXGE_HAL_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vBIT(val, 26, 14)
#define VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN mBIT(43)
#define VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN mBIT(47)
#define VXGE_HAL_RXMAC_VCFG0_BCAST_EN mBIT(51)
#define VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN mBIT(55)
/* 0x00c90 */ u64 rxmac_vcfg1;
#define VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vBIT(val, 42, 2)
#define VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE mBIT(47)
#define VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW mBIT(51)
/* 0x00c98 */ u64 rts_access_steer_ctrl;
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(val) vBIT(val, 1, 7)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE mBIT(15)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL mBIT(23)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL mBIT(27)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(val) vBIT(val, 40, 8)
#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS mBIT(0)
/* 0x00ca0 */ u64 rts_access_steer_data0;
#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DATA(val) vBIT(val, 0, 64)
/* 0x00ca8 */ u64 rts_access_steer_data1;
#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DATA(val) vBIT(val, 0, 64)
u8 unused00d00[0x00d00 - 0x00cb0];
/* 0x00d00 */ u64 xmac_vsport_choice;
#define VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vBIT(val, 3, 5)
/* 0x00d08 */ u64 xmac_stats_cfg;
/* 0x00d10 */ u64 xmac_stats_access_cmd;
#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(val) vBIT(val, 6, 2)
#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE mBIT(15)
#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vBIT(val, 32, 8)
/* 0x00d18 */ u64 xmac_stats_access_data;
#define VXGE_HAL_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64)
/* 0x00d20 */ u64 asic_ntwk_vp_ctrl;
#define VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK mBIT(3)
#define VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO mBIT(55)
#define VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM mBIT(63)
u8 unused00d30[0x00d30 - 0x00d28];
/* 0x00d30 */ u64 xgmac_vp_int_status;
#define VXGE_HAL_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_INT mBIT(3)
/* 0x00d38 */ u64 xgmac_vp_int_mask;
/* 0x00d40 */ u64 asic_ntwk_vp_err_reg;
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT mBIT(3)
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK mBIT(7)
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED mBIT(11)
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED mBIT(15)
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_FAULT mBIT(19)
#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_OK mBIT(23)
/* 0x00d48 */ u64 asic_ntwk_vp_err_mask;
/* 0x00d50 */ u64 asic_ntwk_vp_err_alarm;
u8 unused00d80[0x00d80 - 0x00d58];
/* 0x00d80 */ u64 rtdma_bw_ctrl;
#define VXGE_HAL_RTDMA_BW_CTRL_BW_CTRL_EN mBIT(39)
#define VXGE_HAL_RTDMA_BW_CTRL_DESIRED_BW(val) vBIT(val, 46, 18)
/* 0x00d88 */ u64 rtdma_rd_optimization_ctrl;
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT mBIT(3)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vBIT(val, 6, 2)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vBIT(val, 8, 8)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE mBIT(19)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val)\
vBIT(val, 21, 3)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN mBIT(28)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val)\
vBIT(val, 29, 3)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN mBIT(35)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) vBIT(val, 37, 3)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE mBIT(43)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val)\
vBIT(val, 51, 5)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN mBIT(59)
#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) vBIT(val, 61, 3)
/* 0x00d90 */ u64 pda_pcc_job_monitor;
#define VXGE_HAL_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS mBIT(7)
/* 0x00d98 */ u64 tx_protocol_assist_cfg;
#define VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN mBIT(6)
#define VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING mBIT(7)
u8 unused01000[0x01000 - 0x00da0];
/* 0x01000 */ u64 tim_cfg1_int_num[4];
#define VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vBIT(val, 6, 26)
#define VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN mBIT(35)
#define VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN mBIT(36)
#define VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN mBIT(37)
#define VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC mBIT(38)
#define VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI mBIT(39)
#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(val) vBIT(val, 41, 7)
#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(val) vBIT(val, 49, 7)
#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(val) vBIT(val, 57, 7)
/* 0x01020 */ u64 tim_cfg2_int_num[4];
#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(val) vBIT(val, 0, 16)
#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(val) vBIT(val, 16, 16)
#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(val) vBIT(val, 32, 16)
#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(val) vBIT(val, 48, 16)
/* 0x01040 */ u64 tim_cfg3_int_num[4];
#define VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI mBIT(0)
#define VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vBIT(val, 1, 4)
#define VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vBIT(val, 6, 26)
#define VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(val) vBIT(val, 32, 6)
#define VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vBIT(val, 38, 26)
/* 0x01060 */ u64 tim_wrkld_clc;
#define VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vBIT(val, 0, 32)
#define VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vBIT(val, 35, 5)
#define VXGE_HAL_TIM_WRKLD_CLC_CNT_FRM_BYTE mBIT(40)
#define VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(val) vBIT(val, 41, 2)
#define VXGE_HAL_TIM_WRKLD_CLC_CNT_LNK_EN mBIT(43)
#define VXGE_HAL_TIM_WRKLD_CLC_HOST_UTIL(val) vBIT(val, 57, 7)
/* 0x01068 */ u64 tim_bitmap;
#define VXGE_HAL_TIM_BITMAP_MASK(val) vBIT(val, 0, 32)
#define VXGE_HAL_TIM_BITMAP_LLROOT_RXD_EN mBIT(32)
#define VXGE_HAL_TIM_BITMAP_LLROOT_TXD_EN mBIT(33)
/* 0x01070 */ u64 tim_ring_assn;
#define VXGE_HAL_TIM_RING_ASSN_INT_NUM(val) vBIT(val, 6, 2)
/* 0x01078 */ u64 tim_remap;
#define VXGE_HAL_TIM_REMAP_TX_EN mBIT(5)
#define VXGE_HAL_TIM_REMAP_RX_EN mBIT(6)
#define VXGE_HAL_TIM_REMAP_OFFLOAD_EN mBIT(7)
#define VXGE_HAL_TIM_REMAP_TO_VPATH_NUM(val) vBIT(val, 11, 5)
/* 0x01080 */ u64 tim_vpath_map;
#define VXGE_HAL_TIM_VPATH_MAP_BMAP_ROOT(val) vBIT(val, 0, 32)
/* 0x01088 */ u64 tim_pci_cfg;
#define VXGE_HAL_TIM_PCI_CFG_ADD_PAD mBIT(7)
#define VXGE_HAL_TIM_PCI_CFG_NO_SNOOP mBIT(15)
#define VXGE_HAL_TIM_PCI_CFG_RELAXED mBIT(23)
#define VXGE_HAL_TIM_PCI_CFG_CTL_STR mBIT(31)
u8 unused01100[0x01100 - 0x01090];
/* 0x01100 */ u64 sgrp_assign;
#define VXGE_HAL_SGRP_ASSIGN_SGRP_ASSIGN(val) vBIT(val, 0, 64)
/* 0x01108 */ u64 sgrp_aoa_and_result;
#define VXGE_HAL_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val)\
vBIT(val, 0, 64)
/* 0x01110 */ u64 rpe_pci_cfg;
#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE mBIT(7)
#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE mBIT(8)
#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE mBIT(9)
#define VXGE_HAL_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE mBIT(10)
#define VXGE_HAL_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE mBIT(11)
#define VXGE_HAL_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE mBIT(12)
#define VXGE_HAL_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE mBIT(13)
#define VXGE_HAL_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE mBIT(14)
#define VXGE_HAL_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE mBIT(15)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_DATA mBIT(18)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_NONLL_CQE mBIT(19)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_LL_CQE mBIT(20)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRQ_IR mBIT(21)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQSQ_IR mBIT(22)
#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRR_IR mBIT(23)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_DATA mBIT(26)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_NONLL_CQE mBIT(27)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_LL_CQE mBIT(28)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRQ_IR mBIT(29)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQSQ_IR mBIT(30)
#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRR_IR mBIT(31)
/* 0x01118 */ u64 rpe_lro_cfg;
#define VXGE_HAL_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR mBIT(7)
#define VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG mBIT(11)
#define VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG mBIT(15)
#define VXGE_HAL_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE mBIT(23)
/* 0x01120 */ u64 pe_mr2vp_ack_blk_limit;
#define VXGE_HAL_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vBIT(val, 32, 32)
/* 0x01128 */ u64 pe_mr2vp_rirr_lirr_blk_limit;
#define VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val)\
vBIT(val, 0, 32)
#define VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val)\
vBIT(val, 32, 32)
/* 0x01130 */ u64 txpe_pci_nce_cfg;
#define VXGE_HAL_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vBIT(val, 0, 32)
#define VXGE_HAL_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE mBIT(55)
#define VXGE_HAL_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI mBIT(63)
u8 unused01180[0x01180 - 0x01138];
/* 0x01180 */ u64 msg_qpad_en_cfg;
#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_BWR_READ mBIT(3)
#define VXGE_HAL_MSG_QPAD_EN_CFG_DMQ_BWR_READ mBIT(7)
#define VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_READ mBIT(11)
#define VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_READ mBIT(15)
#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE mBIT(19)
#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE mBIT(23)
#define VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE mBIT(27)
#define VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE mBIT(31)
/* 0x01188 */ u64 msg_pci_cfg;
#define VXGE_HAL_MSG_PCI_CFG_GENDMA_NO_SNOOP mBIT(3)
#define VXGE_HAL_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP mBIT(7)
#define VXGE_HAL_MSG_PCI_CFG_UMQ_NO_SNOOP mBIT(11)
#define VXGE_HAL_MSG_PCI_CFG_DMQ_NO_SNOOP mBIT(15)
/* 0x01190 */ u64 umqdmq_ir_init;
#define VXGE_HAL_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vBIT(val, 0, 64)
/* 0x01198 */ u64 dmq_ir_int;
#define VXGE_HAL_DMQ_IR_INT_IMMED_ENABLE mBIT(6)
#define VXGE_HAL_DMQ_IR_INT_EVENT_ENABLE mBIT(7)
#define VXGE_HAL_DMQ_IR_INT_NUMBER(val) vBIT(val, 9, 7)
#define VXGE_HAL_DMQ_IR_INT_BITMAP(val) vBIT(val, 16, 16)
/* 0x011a0 */ u64 dmq_bwr_init_add;
#define VXGE_HAL_DMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64)
/* 0x011a8 */ u64 dmq_bwr_init_byte;
#define VXGE_HAL_DMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32)
/* 0x011b0 */ u64 dmq_ir;
#define VXGE_HAL_DMQ_IR_POLICY(val) vBIT(val, 0, 8)
/* 0x011b8 */ u64 umq_int;
#define VXGE_HAL_UMQ_INT_IMMED_ENABLE mBIT(6)
#define VXGE_HAL_UMQ_INT_EVENT_ENABLE mBIT(7)
#define VXGE_HAL_UMQ_INT_NUMBER(val) vBIT(val, 9, 7)
#define VXGE_HAL_UMQ_INT_BITMAP(val) vBIT(val, 16, 16)
/* 0x011c0 */ u64 umq_mr2vp_bwr_pfch_init;
#define VXGE_HAL_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8)
/* 0x011c8 */ u64 umq_bwr_pfch_ctrl;
#define VXGE_HAL_UMQ_BWR_PFCH_CTRL_POLL_EN mBIT(3)
/* 0x011d0 */ u64 umq_mr2vp_bwr_eol;
#define VXGE_HAL_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32)
/* 0x011d8 */ u64 umq_bwr_init_add;
#define VXGE_HAL_UMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64)
/* 0x011e0 */ u64 umq_bwr_init_byte;
#define VXGE_HAL_UMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32)
/* 0x011e8 */ u64 gendma_int;
#define VXGE_HAL_GENDMA_INT_IMMED_ENABLE mBIT(6)
#define VXGE_HAL_GENDMA_INT_EVENT_ENABLE mBIT(7)
#define VXGE_HAL_GENDMA_INT_NUMBER(val) vBIT(val, 9, 7)
#define VXGE_HAL_GENDMA_INT_BITMAP(val) vBIT(val, 16, 16)
/* 0x011f0 */ u64 umqdmq_ir_init_notify;
#define VXGE_HAL_UMQDMQ_IR_INIT_NOTIFY_PULSE mBIT(3)
/* 0x011f8 */ u64 dmq_init_notify;
#define VXGE_HAL_DMQ_INIT_NOTIFY_PULSE mBIT(3)
/* 0x01200 */ u64 umq_init_notify;
#define VXGE_HAL_UMQ_INIT_NOTIFY_PULSE mBIT(3)
u8 unused01380[0x01380 - 0x01208];
/* 0x01380 */ u64 tpa_cfg;
#define VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR mBIT(3)
#define VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING mBIT(7)
#define VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT mBIT(11)
#define VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS mBIT(15)
u8 unused01400[0x01400 - 0x01388];
/* 0x01400 */ u64 tx_vp_reset_discarded_frms;
#define VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val)\
vBIT(val, 48, 16)
u8 unused01480[0x01480 - 0x01408];
/* 0x01480 */ u64 fau_rpa_vcfg;
#define VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM mBIT(7)
#define VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF mBIT(11)
#define VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM mBIT(15)
u8 unused014a8[0x014a8 - 0x01488];
/* 0x014a8 */ u64 fau_adaptive_lro_filter_ctrl;
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_FILTER_EN mBIT(0)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_MODE mBIT(1)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_VLAN_FILTER_EN mBIT(2)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_A_EN mBIT(3)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_B_EN mBIT(4)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_C_EN mBIT(5)
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_D_EN mBIT(6)
/* 0x014b0 */ u64 fau_adaptive_lro_filter_ip_data0;
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA0_DATA(val) vBIT(val, 0, 64)
/* 0x014b8 */ u64 fau_adaptive_lro_filter_ip_data1;
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA1_DATA(val) vBIT(val, 0, 64)
/* 0x014c0 */ u64 fau_adaptive_lro_filter_vlan_data;
#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_VLAN_DATA_VLAN_VID(val)\
vBIT(val, 0, 12)
u8 unused014d0[0x014d0 - 0x014c8];
/* 0x014d0 */ u64 dbg_stats_rx_mpa;
#define VXGE_HAL_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vBIT(val, 0, 16)
#define VXGE_HAL_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vBIT(val, 16, 16)
#define VXGE_HAL_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vBIT(val, 32, 16)
/* 0x014d8 */ u64 dbg_stats_rx_fau;
#define VXGE_HAL_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vBIT(val, 0, 16)
#define VXGE_HAL_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val)\
vBIT(val, 16, 16)
#define VXGE_HAL_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32)
u8 unused014f0[0x014f0 - 0x014e0];
/* 0x014f0 */ u64 fbmc_vp_rdy;
#define VXGE_HAL_FBMC_VP_RDY_QUEUE_SPAV_FM mBIT(0)
u8 unused01e00[0x01e00 - 0x014f8];
/* 0x01e00 */ u64 vpath_pcipif_int_status;
#define VXGE_HAL_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_INT mBIT(3)
#define VXGE_HAL_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_INT mBIT(7)
/* 0x01e08 */ u64 vpath_pcipif_int_mask;
u8 unused01e20[0x01e20 - 0x01e10];
/* 0x01e20 */ u64 srpcim_msg_to_vpath_reg;
#define VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT mBIT(3)
/* 0x01e28 */ u64 srpcim_msg_to_vpath_mask;
/* 0x01e30 */ u64 srpcim_msg_to_vpath_alarm;
u8 unused01ea0[0x01ea0 - 0x01e38];
/* 0x01ea0 */ u64 vpath_to_srpcim_wmsg;
#define VXGE_HAL_VPATH_TO_SRPCIM_WMSG_WMSG(val) vBIT(val, 0, 64)
/* 0x01ea8 */ u64 vpath_to_srpcim_wmsg_trig;
#define VXGE_HAL_VPATH_TO_SRPCIM_WMSG_TRIG mBIT(0)
u8 unused02000[0x02000 - 0x01eb0];
/* 0x02000 */ u64 vpath_general_int_status;
#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT mBIT(3)
#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT mBIT(7)
#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT mBIT(15)
#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT mBIT(19)
/* 0x02008 */ u64 vpath_general_int_mask;
#define VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT mBIT(3)
#define VXGE_HAL_VPATH_GENERAL_INT_MASK_PCI_INT mBIT(7)
#define VXGE_HAL_VPATH_GENERAL_INT_MASK_WRDMA_INT mBIT(15)
#define VXGE_HAL_VPATH_GENERAL_INT_MASK_XMAC_INT mBIT(19)
/* 0x02010 */ u64 vpath_ppif_int_status;
#define VXGE_HAL_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_INT mBIT(3)
#define VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT mBIT(7)
#define VXGE_HAL_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_INT mBIT(11)
#define VXGE_HAL_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_INT mBIT(15)
#define VXGE_HAL_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_INT mBIT(19)
/* 0x02018 */ u64 vpath_ppif_int_mask;
/* 0x02020 */ u64 kdfcctl_errors_reg;
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR mBIT(3)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR mBIT(7)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR mBIT(11)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON mBIT(15)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON mBIT(19)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON mBIT(23)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR mBIT(31)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR mBIT(35)
#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR mBIT(39)
/* 0x02028 */ u64 kdfcctl_errors_mask;
/* 0x02030 */ u64 kdfcctl_errors_alarm;
u8 unused02040[0x02040 - 0x02038];
/* 0x02040 */ u64 general_errors_reg;
#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW mBIT(3)
#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW mBIT(7)
#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW mBIT(11)
#define VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR mBIT(15)
#define VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT mBIT(19)
#define VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS mBIT(27)
#define VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET mBIT(31)
/* 0x02048 */ u64 general_errors_mask;
/* 0x02050 */ u64 general_errors_alarm;
/* 0x02058 */ u64 pci_config_errors_reg;
#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR mBIT(3)
#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR mBIT(7)
#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR mBIT(11)
/* 0x02060 */ u64 pci_config_errors_mask;
/* 0x02068 */ u64 pci_config_errors_alarm;
/* 0x02070 */ u64 mrpcim_to_vpath_alarm_reg;
#define VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM mBIT(3)
/* 0x02078 */ u64 mrpcim_to_vpath_alarm_mask;
/* 0x02080 */ u64 mrpcim_to_vpath_alarm_alarm;
/* 0x02088 */ u64 srpcim_to_vpath_alarm_reg;
#define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_PPIF_ALARM(val) vBIT(val, 0, 17)
/* 0x02090 */ u64 srpcim_to_vpath_alarm_mask;
/* 0x02098 */ u64 srpcim_to_vpath_alarm_alarm;
u8 unused02108[0x02108 - 0x020a0];
/* 0x02108 */ u64 kdfcctl_status;
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vBIT(val, 0, 8)
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vBIT(val, 8, 8)
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vBIT(val, 16, 8)
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vBIT(val, 24, 8)
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vBIT(val, 32, 8)
#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vBIT(val, 40, 8)
/* 0x02110 */ u64 rsthdlr_status;
#define VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET mBIT(3)
#define VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vBIT(val, 6, 2)
/* 0x02118 */ u64 fifo0_status;
#define VXGE_HAL_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vBIT(val, 0, 12)
/* 0x02120 */ u64 fifo1_status;
#define VXGE_HAL_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vBIT(val, 0, 12)
/* 0x02128 */ u64 fifo2_status;
#define VXGE_HAL_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vBIT(val, 0, 12)
u8 unused02158[0x02158 - 0x02130];
/* 0x02158 */ u64 tgt_illegal_access;
#define VXGE_HAL_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7)
u8 unused02200[0x02200 - 0x02160];
/* 0x02200 */ u64 vpath_general_cfg1;
#define VXGE_HAL_VPATH_GENERAL_CFG1_TC_VALUE(val) vBIT(val, 1, 3)
#define VXGE_HAL_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN mBIT(7)
#define VXGE_HAL_VPATH_GENERAL_CFG1_DATA_FLIPEN mBIT(11)
#define VXGE_HAL_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN mBIT(15)
#define VXGE_HAL_VPATH_GENERAL_CFG1_CTL_FLIPEN mBIT(23)
#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(51)
#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(55)
#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(59)
#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(63)
/* 0x02208 */ u64 vpath_general_cfg2;
#define VXGE_HAL_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vBIT(val, 1, 3)
/* 0x02210 */ u64 vpath_general_cfg3;
#define VXGE_HAL_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA mBIT(3)
u8 unused02220[0x02220 - 0x02218];
/* 0x02220 */ u64 kdfcctl_cfg0;
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 mBIT(1)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 mBIT(2)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2 mBIT(3)
#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0 mBIT(5)
#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1 mBIT(6)
#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2 mBIT(7)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0 mBIT(9)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1 mBIT(10)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2 mBIT(11)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0 mBIT(13)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1 mBIT(14)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2 mBIT(15)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0 mBIT(17)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1 mBIT(18)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2 mBIT(19)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0 mBIT(21)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1 mBIT(22)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2 mBIT(23)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0 mBIT(25)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1 mBIT(26)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2 mBIT(27)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0 mBIT(29)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1 mBIT(30)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2 mBIT(31)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0 mBIT(33)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1 mBIT(34)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2 mBIT(35)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0 mBIT(37)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1 mBIT(38)
#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2 mBIT(39)
/* 0x02228 */ u64 dblgen_cfg0;
#define VXGE_HAL_DBLGEN_CFG0_NO_OF_QWORDS(val) vBIT(val, 0, 12)
#define VXGE_HAL_DBLGEN_CFG0_EN_DMA mBIT(15)
#define VXGE_HAL_DBLGEN_CFG0_NO_SNOOP mBIT(19)
#define VXGE_HAL_DBLGEN_CFG0_RELAX_ORD mBIT(23)
#define VXGE_HAL_DBLGEN_CFG0_RD_SPLIT_ON_ADDR mBIT(27)
/* 0x02230 */ u64 dblgen_cfg1;
#define VXGE_HAL_DBLGEN_CFG1_FIFO0_BUFFER_START_ADDR(val) vBIT(val, 0, 64)
/* 0x02238 */ u64 dblgen_cfg2;
#define VXGE_HAL_DBLGEN_CFG2_FIFO1_BUFFER_START_ADDR(val) vBIT(val, 0, 64)
/* 0x02240 */ u64 dblgen_cfg3;
#define VXGE_HAL_DBLGEN_CFG3_FIFO2_BUFFER_START_ADDR(val) vBIT(val, 0, 64)
/* 0x02248 */ u64 dblgen_cfg4;
#define VXGE_HAL_DBLGEN_CFG4_TRIPLET_PRIORITY_VP_NUMBER(val) vBIT(val, 3, 5)
/* 0x02250 */ u64 dblgen_cfg5;
#define VXGE_HAL_DBLGEN_CFG5_FIFO0_WRIDX(val) vBIT(val, 0, 12)
/* 0x02258 */ u64 dblgen_cfg6;
#define VXGE_HAL_DBLGEN_CFG6_FIFO1_WRIDX(val) vBIT(val, 0, 12)
/* 0x02260 */ u64 dblgen_cfg7;
#define VXGE_HAL_DBLGEN_CFG7_FIFO2_WRIDX(val) vBIT(val, 0, 12)
/* 0x02268 */ u64 stats_cfg;
#define VXGE_HAL_STATS_CFG_START_HOST_ADDR(val) vBIT(val, 0, 57)
/* 0x02270 */ u64 interrupt_cfg0;
#define VXGE_HAL_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vBIT(val, 1, 7)
#define VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vBIT(val, 9, 7)
#define VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vBIT(val, 17, 7)
#define VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vBIT(val, 25, 7)
#define VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vBIT(val, 33, 7)
u8 unused02280[0x02280 - 0x02278];
/* 0x02280 */ u64 interrupt_cfg2;
#define VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7)
/* 0x02288 */ u64 one_shot_vect0_en;
#define VXGE_HAL_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN mBIT(3)
/* 0x02290 */ u64 one_shot_vect1_en;
#define VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN mBIT(3)
/* 0x02298 */ u64 one_shot_vect2_en;
#define VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN mBIT(3)
/* 0x022a0 */ u64 one_shot_vect3_en;
#define VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN mBIT(3)
u8 unused022b0[0x022b0 - 0x022a8];
/* 0x022b0 */ u64 pci_config_access_cfg1;
#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 0, 12)
#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 mBIT(15)
/* 0x022b8 */ u64 pci_config_access_cfg2;
#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG2_REQ mBIT(0)
/* 0x022c0 */ u64 pci_config_access_status;
#define VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR mBIT(0)
#define VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32)
u8 unused02300[0x02300 - 0x022c8];
/* 0x02300 */ u64 vpath_debug_stats0;
#define VXGE_HAL_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vBIT(val, 0, 32)
/* 0x02308 */ u64 vpath_debug_stats1;
#define VXGE_HAL_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vBIT(val, 0, 32)
/* 0x02310 */ u64 vpath_debug_stats2;
#define VXGE_HAL_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vBIT(val, 0, 32)
/* 0x02318 */ u64 vpath_debug_stats3;
#define VXGE_HAL_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) vBIT(val, 0, 64)
/* 0x02320 */ u64 vpath_debug_stats4;
#define VXGE_HAL_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) vBIT(val, 0, 64)
/* 0x02328 */ u64 vpath_debug_stats5;
#define VXGE_HAL_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vBIT(val, 32, 32)
/* 0x02330 */ u64 vpath_debug_stats6;
#define VXGE_HAL_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vBIT(val, 32, 32)
/* 0x02338 */ u64 vpath_genstats_count01;
#define VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val)\
vBIT(val, 0, 32)
#define VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val)\
vBIT(val, 32, 32)
/* 0x02340 */ u64 vpath_genstats_count23;
#define VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val)\
vBIT(val, 0, 32)
#define VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val)\
vBIT(val, 32, 32)
/* 0x02348 */ u64 vpath_genstats_count4;
#define VXGE_HAL_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val)\
vBIT(val, 32, 32)
/* 0x02350 */ u64 vpath_genstats_count5;
#define VXGE_HAL_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val)\
vBIT(val, 32, 32)
u8 unused02540[0x02540 - 0x02358];
/* 0x02540 */ u64 qcc_pci_cfg;
#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE mBIT(5)
#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_WQE mBIT(6)
#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_SRQIR mBIT(7)
#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE mBIT(13)
#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE mBIT(14)
#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR mBIT(15)
#define VXGE_HAL_QCC_PCI_CFG_RELAXED_SRQIR mBIT(23)
#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_CQE_SPACE mBIT(29)
#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_WQE mBIT(30)
#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_SRQIR mBIT(31)
u8 unused02600[0x02600 - 0x02548];
/* 0x02600 */ u64 h2l_vpath_config;
#define VXGE_HAL_H2L_VPATH_CONFIG_OD_PAD_ENABLE mBIT(7)
#define VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP mBIT(15)
/* 0x02608 */ u64 h2l_zero_byte_read_address;
#define VXGE_HAL_H2L_ZERO_BYTE_READ_ADDRESS_H2L_ZERO_BYTE_READ_ADDRESS(val)\
vBIT(val, 0, 64)
u8 unused02640[0x02640 - 0x02610];
/* 0x02640 */ u64 ph2l_vp_cfg0;
#define VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA mBIT(7)
} vxge_hal_vpath_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_VPATH_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_VPMGMT_REGS_H
#define VXGE_HAL_VPMGMT_REGS_H
__EXTERN_BEGIN_DECLS
typedef struct vxge_hal_vpmgmt_reg_t {
/* 0x00000 */ u64 one_cfg_sr_rdy;
#define VXGE_HAL_ONE_CFG_SR_RDY_ONE_CFG_SR_RDY mBIT(7)
/* 0x00008 */ u64 sgrp_own;
#define VXGE_HAL_SGRP_OWN_SGRP_OWN(val) vBIT(val, 0, 64)
u8 unused00040[0x00040 - 0x00010];
/* 0x00040 */ u64 vpath_to_func_map_cfg1;
#define VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val)\
vBIT(val, 3, 5)
/* 0x00048 */ u64 vpath_is_first;
#define VXGE_HAL_VPATH_IS_FIRST_VPATH_IS_FIRST mBIT(3)
/* 0x00050 */ u64 srpcim_to_vpath_wmsg;
#define VXGE_HAL_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val)\
vBIT(val, 0, 64)
/* 0x00058 */ u64 srpcim_to_vpath_wmsg_trig;
#define VXGE_HAL_SRPCIM_TO_VPATH_WMSG_TRIG_TRIG mBIT(0)
u8 unused00100[0x00100 - 0x00060];
/* 0x00100 */ u64 tim_vpath_assignment;
#define VXGE_HAL_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vBIT(val, 0, 32)
u8 unused00140[0x00140 - 0x00108];
/* 0x00140 */ u64 rqa_top_prty_for_vp;
#define VXGE_HAL_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) vBIT(val, 59, 5)
u8 unused00180[0x00180 - 0x00148];
/* 0x00180 */ u64 usdc_vpath_own;
#define VXGE_HAL_USDC_VPATH_OWN_SGRP_OWN(val) vBIT(val, 0, 32)
u8 unused001c0[0x001c0 - 0x00188];
/* 0x001c0 */ u64 rxmac_rx_pa_cfg0_vpmgmt_clone;
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR mBIT(3)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N mBIT(7)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO mBIT(18)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS\
mBIT(19)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING mBIT(23)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN mBIT(27)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE mBIT(35)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR\
mBIT(39)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR\
mBIT(43)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR\
mBIT(47)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR\
mBIT(51)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR\
mBIT(55)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR\
mBIT(59)
#define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN mBIT(63)
/* 0x001c8 */ u64 rts_mgr_cfg0_vpmgmt_clone;
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY mBIT(3)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val)\
vBIT(val, 24, 8)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH mBIT(35)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH mBIT(39)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH mBIT(43)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH mBIT(47)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH mBIT(51)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH mBIT(55)
#define VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH mBIT(59)
/* 0x001d0 */ u64 rts_mgr_criteria_priority_vpmgmt_clone;
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val)\
vBIT(val, 5, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val)\
vBIT(val, 9, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val)\
vBIT(val, 13, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val)\
vBIT(val, 17, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val)\
vBIT(val, 21, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val)\
vBIT(val, 25, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val)\
vBIT(val, 29, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val)\
vBIT(val, 33, 3)
#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val)\
vBIT(val, 37, 3)
/* 0x001d8 */ u64 rxmac_cfg0_port_vpmgmt_clone[3];
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN mBIT(3)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS mBIT(7)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM mBIT(11)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR mBIT(15)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR mBIT(19)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR mBIT(23)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH mBIT(27)
#define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val)\
vBIT(val, 50, 14)
/* 0x001f0 */ u64 rxmac_pause_cfg_port_vpmgmt_clone[3];
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN mBIT(3)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN mBIT(7)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val)\
vBIT(val, 9, 3)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR mBIT(15)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val)\
vBIT(val, 20, 16)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR mBIT(39)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR mBIT(43)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN mBIT(47)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val)\
vBIT(val, 48, 8)
#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL mBIT(59)
u8 unused00240[0x00240 - 0x00208];
/* 0x00240 */ u64 xmac_vsport_choices_vp;
#define VXGE_HAL_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vBIT(val, 0, 17)
u8 unused00260[0x00260 - 0x00248];
/* 0x00260 */ u64 xgmac_gen_status_vpmgmt_clone;
#define VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK mBIT(3)
#define VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE mBIT(11)
/* 0x00268 */ u64 xgmac_status_port_vpmgmt_clone[2];
#define VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT mBIT(3)
#define VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT mBIT(7)
#define VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL\
mBIT(11)
#define VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK mBIT(15)
/* 0x00278 */ u64 xmac_gen_cfg_vpmgmt_clone;
#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val)\
vBIT(val, 2, 2)
#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT\
mBIT(7)
#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR\
mBIT(27)
#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val)\
vBIT(val, 28, 4)
#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val)\
vBIT(val, 32, 4)
/* 0x00280 */ u64 xmac_timestamp_vpmgmt_clone;
#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_EN mBIT(3)
#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val)\
vBIT(val, 6, 2)
#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val)\
vBIT(val, 12, 4)
#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART\
mBIT(19)
#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val)\
vBIT(val, 32, 16)
/* 0x00288 */ u64 xmac_stats_gen_cfg_vpmgmt_clone;
#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val)\
vBIT(val, 4, 4)
#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val)\
vBIT(val, 8, 4)
#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING\
mBIT(15)
/* 0x00290 */ u64 xmac_cfg_port_vpmgmt_clone[3];
#define VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK\
mBIT(3)
#define VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK\
mBIT(7)
#define VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV\
mBIT(11)
#define VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV\
mBIT(15)
u8 unused002c0[0x002c0 - 0x002a8];
/* 0x002c0 */ u64 txmac_gen_cfg0_vpmgmt_clone;
#define VXGE_HAL_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT\
mBIT(7)
/* 0x002c8 */ u64 txmac_cfg0_port_vpmgmt_clone[3];
#define VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN\
mBIT(3)
#define VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD\
mBIT(7)
#define VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vBIT(val, 8, 8)
u8 unused00300[0x00300 - 0x002e0];
/* 0x00300 */ u64 wol_mp_crc;
#define VXGE_HAL_WOL_MP_CRC_CRC(val) vBIT(val, 0, 32)
#define VXGE_HAL_WOL_MP_CRC_RC_EN mBIT(63)
/* 0x00308 */ u64 wol_mp_mask_a;
#define VXGE_HAL_WOL_MP_MASK_A_MASK(val) vBIT(val, 0, 64)
/* 0x00310 */ u64 wol_mp_mask_b;
#define VXGE_HAL_WOL_MP_MASK_B_MASK(val) vBIT(val, 0, 64)
u8 unused00360[0x00360 - 0x00318];
/* 0x00360 */ u64 fau_pa_cfg_vpmgmt_clone;
#define VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM mBIT(3)
#define VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF mBIT(7)
#define VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM mBIT(11)
/* 0x00368 */ u64 rx_datapath_util_vp_clone;
#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val)\
vBIT(val, 7, 9)
#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) vBIT(val, 16, 4)
#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val)\
vBIT(val, 20, 4)
#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val)\
vBIT(val, 24, 4)
u8 unused00380[0x00380 - 0x00370];
/* 0x00380 */ u64 tx_datapath_util_vp_clone;
#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val)\
vBIT(val, 7, 9)
#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) vBIT(val, 16, 4)
#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val)\
vBIT(val, 20, 4)
#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) vBIT(val, 24, 4)
} vxge_hal_vpmgmt_reg_t;
__EXTERN_END_DECLS
#endif /* VXGE_HAL_VPMGMT_REGS_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef VXGE_HAL_H
#define VXGE_HAL_H
#include <dev/vxge/include/vxgehal-ll.h>
#include <dev/vxge/vxgehal/vxgehal-debug.h>
#include <dev/vxge/vxgehal/vxgehal-regdefs.h>
#include <dev/vxge/vxgehal/vxgehal-legacy-reg.h>
#include <dev/vxge/vxgehal/vxgehal-toc-reg.h>
#include <dev/vxge/vxgehal/vxgehal-common-reg.h>
#include <dev/vxge/vxgehal/vxgehal-memrepair-reg.h>
#include <dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h>
#include <dev/vxge/vxgehal/vxgehal-mrpcim-reg.h>
#include <dev/vxge/vxgehal/vxgehal-srpcim-reg.h>
#include <dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h>
#include <dev/vxge/vxgehal/vxgehal-vpath-reg.h>
#include <dev/vxge/vxgehal/vxgehal-regs.h>
#include <dev/vxge/vxgehal/vxgehal-config-priv.h>
#include <dev/vxge/vxgehal/vxgehal-swapper.h>
#include <dev/vxge/vxgehal/vxgehal-mm.h>
#include <dev/vxge/vxgehal/vxgehal-blockpool.h>
#include <dev/vxge/vxgehal/vxgehal-doorbells.h>
#include <dev/vxge/vxgehal/vxgehal-virtualpath.h>
#include <dev/vxge/vxgehal/vxgehal-device.h>
#include <dev/vxge/vxgehal/vxgehal-channel.h>
#include <dev/vxge/vxgehal/vxgehal-srpcim.h>
#include <dev/vxge/vxgehal/vxgehal-mrpcim.h>
#include <dev/vxge/vxgehal/vxgehal-driver.h>
#include <dev/vxge/vxgehal/vxgehal-ring.h>
#include <dev/vxge/vxgehal/vxgehal-fifo.h>
#include <dev/vxge/vxgehal/vxgehal-ifmsg.h>
#endif /* VXGE_HAL_H */

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/*-
* Copyright(c) 2002-2011 Exar Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification are permitted provided the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Exar Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _VXGELL_VERSION_H_
#define _VXGELL_VERSION_H_
#define XGELL_VERSION_MAJOR 2
#define XGELL_VERSION_MINOR 5
#define XGELL_VERSION_FIX 1
#define XGELL_VERSION_BUILD GENERATED_BUILD_VERSION
#define VXGE_FW_VERSION(major, minor, build) \
((major << 16) + (minor << 8) + build)
#define VXGE_FW_MAJ_MIN_VERSION(major, minor) \
((major << 16) + (minor << 8))
/* Adapter should be running with this fw version for using FW_UPGRADE API's */
#define VXGE_BASE_FW_MAJOR_VERSION 1
#define VXGE_BASE_FW_MINOR_VERSION 4
#define VXGE_BASE_FW_BUILD_VERSION 4
#define VXGE_BASE_FW_VERSION \
VXGE_FW_VERSION(VXGE_BASE_FW_MAJOR_VERSION, \
VXGE_BASE_FW_MINOR_VERSION, \
VXGE_BASE_FW_BUILD_VERSION)
#define VXGE_DRV_FW_VERSION \
VXGE_FW_VERSION(VXGE_MIN_FW_MAJOR_VERSION, \
VXGE_MIN_FW_MINOR_VERSION, \
VXGE_MIN_FW_BUILD_NUMBER)
#define VXGE_DRV_FW_MAJ_MIN_VERSION \
VXGE_FW_MAJ_MIN_VERSION(VXGE_MIN_FW_MAJOR_VERSION, \
VXGE_MIN_FW_MINOR_VERSION)
#define VXGE_FW_ARRAY_NAME X3fw_ncf
#define VXGE_COPYRIGHT "Copyright(c) 2002-2011 Exar Corp.\n"
#define VXGE_ADAPTER_NAME "Neterion x3100 10GbE PCIe Server Adapter " \
"(Rev %d)"
#endif /* _VXGELL_VERSION_H_ */

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# $FreeBSD$
.PATH: ${.CURDIR}/../../dev/vxge
VPATH = ${.CURDIR}/../../dev/vxge/vxgehal
CFLAGS_VXGE =
# Debugging/Tracing:
#VXGE_COMPONENT_HAL_DEVICE 0x00000001
#VXGE_COMPONENT_HAL_DEVICE_IRQ 0x00000002
#VXGE_COMPONENT_HAL_VPATH 0x00000004
#VXGE_COMPONENT_HAL_VPATH_IRQ 0x00000008
#VXGE_COMPONENT_HAL_CONFIG 0x00000010
#VXGE_COMPONENT_HAL_MM 0x00000020
#VXGE_COMPONENT_HAL_POOL 0x00000040
#VXGE_COMPONENT_HAL_QUEUE 0x00000080
#VXGE_COMPONENT_HAL_CHANNEL 0x00000200
#VXGE_COMPONENT_HAL_FIFO 0x00000400
#VXGE_COMPONENT_HAL_RING 0x00000800
#VXGE_COMPONENT_HAL_LRO 0x00100000
#VXGE_COMPONENT_HAL_STATS 0x00800000
#VXGE_COMPONENT_HAL_MRPCIM 0x01000000
#VXGE_COMPONENT_HAL_MRPCIM_IRQ 0x02000000
#VXGE_COMPONENT_HAL_SRPCIM 0x04000000
#VXGE_COMPONENT_HAL_SRPCIM_IRQ 0x08000000
#VXGE_COMPONENT_HAL_DRIVER 0x10000000
#VXGE_COMPONENT_OSDEP 0x20000000
#VXGE_COMPONENT_LL 0x40000000
#VXGE_COMPONENT_ULD 0x80000000
#VXGE_COMPONENT_ALL 0xffffffff
#CFLAGS_VXGE += -DVXGE_DEBUG_MODULE_MASK=VXGE_COMPONENT_ALL
#CFLAGS_VXGE += -DVXGE_DEBUG_ERR_MASK=VXGE_COMPONENT_ALL
#CFLAGS_VXGE += -DVXGE_DEBUG_TRACE_MASK=VXGE_COMPONENT_ALL
#CFLAGS_VXGE += -DVXGE_OS_MEMORY_CHECK
CFLAGS_VXGE += -DVXGE_HAL_RX_MULTI_POST
CFLAGS_VXGE += -DVXGE_HAL_TX_MULTI_POST
CFLAGS += $(CFLAGS_VXGE)
KMOD = vxge
SRCS = vxge.c
SRCS += vxgehal-driver.c
SRCS += vxgehal-swapper.c
SRCS += vxgehal-config.c
SRCS += vxgehal-device.c
SRCS += vxge-queue.c
SRCS += vxgehal-mm.c
SRCS += vxgehal-blockpool.c
SRCS += vxgehal-channel.c
SRCS += vxgehal-fifo.c
SRCS += vxgehal-ring.c
SRCS += vxgehal-virtualpath.c
SRCS += vxgehal-doorbells.c
SRCS += vxgehal-mgmt.c
SRCS += vxgehal-mgmtaux.c
SRCS += vxgehal-mrpcim.c
SRCS += vxgehal-srpcim.c
SRCS += vxgehal-ifmsg.c
SRCS+= bus_if.h device_if.h pci_if.h
.include <bsd.kmod.mk>