Add driver for Altera modular Scatter-Gather DMA engine (mSGDMA).
Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D9619
This commit is contained in:
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parent
99f48cdaff
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d610cb72d0
@ -831,6 +831,7 @@ dev/alpm/alpm.c optional alpm pci
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dev/altera/avgen/altera_avgen.c optional altera_avgen
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dev/altera/avgen/altera_avgen_fdt.c optional altera_avgen fdt
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dev/altera/avgen/altera_avgen_nexus.c optional altera_avgen
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dev/altera/msgdma/msgdma.c optional altera_msgdma xdma
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dev/altera/sdcard/altera_sdcard.c optional altera_sdcard
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dev/altera/sdcard/altera_sdcard_disk.c optional altera_sdcard
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dev/altera/sdcard/altera_sdcard_io.c optional altera_sdcard
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641
sys/dev/altera/msgdma/msgdma.c
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641
sys/dev/altera/msgdma/msgdma.c
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@ -0,0 +1,641 @@
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/*-
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* Copyright (c) 2016-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Altera mSGDMA driver. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/endian.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/sglist.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/cache.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/xdma/xdma.h>
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#include "xdma_if.h"
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#include <dev/altera/msgdma/msgdma.h>
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#define MSGDMA_DEBUG
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#undef MSGDMA_DEBUG
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#ifdef MSGDMA_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define MSGDMA_NCHANNELS 1
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struct msgdma_channel {
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struct msgdma_softc *sc;
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struct mtx mtx;
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xdma_channel_t *xchan;
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struct proc *p;
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int used;
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int index;
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int idx_head;
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int idx_tail;
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struct msgdma_desc **descs;
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bus_dma_segment_t *descs_phys;
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uint32_t descs_num;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t *dma_map;
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uint32_t map_descr;
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uint8_t map_err;
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uint32_t descs_used_count;
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};
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struct msgdma_softc {
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device_t dev;
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struct resource *res[3];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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bus_space_tag_t bst_d;
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bus_space_handle_t bsh_d;
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void *ih;
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struct msgdma_desc desc;
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struct msgdma_channel channels[MSGDMA_NCHANNELS];
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};
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static struct resource_spec msgdma_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define HWTYPE_NONE 0
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#define HWTYPE_STD 1
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static struct ofw_compat_data compat_data[] = {
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{ "altr,msgdma-16.0", HWTYPE_STD },
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{ "altr,msgdma-1.0", HWTYPE_STD },
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{ NULL, HWTYPE_NONE },
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};
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static int msgdma_probe(device_t dev);
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static int msgdma_attach(device_t dev);
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static int msgdma_detach(device_t dev);
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static inline uint32_t
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msgdma_next_desc(struct msgdma_channel *chan, uint32_t curidx)
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{
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return ((curidx + 1) % chan->descs_num);
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}
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static void
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msgdma_intr(void *arg)
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{
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xdma_transfer_status_t status;
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struct xdma_transfer_status st;
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struct msgdma_desc *desc;
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struct msgdma_channel *chan;
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struct xdma_channel *xchan;
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struct msgdma_softc *sc;
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uint32_t tot_copied;
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sc = arg;
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chan = &sc->channels[0];
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xchan = chan->xchan;
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dprintf("%s(%d): status 0x%08x next_descr 0x%08x, control 0x%08x\n",
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__func__, device_get_unit(sc->dev),
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READ4_DESC(sc, PF_STATUS),
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READ4_DESC(sc, PF_NEXT_LO),
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READ4_DESC(sc, PF_CONTROL));
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tot_copied = 0;
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while (chan->idx_tail != chan->idx_head) {
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dprintf("%s: idx_tail %d idx_head %d\n", __func__,
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chan->idx_tail, chan->idx_head);
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bus_dmamap_sync(chan->dma_tag, chan->dma_map[chan->idx_tail],
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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desc = chan->descs[chan->idx_tail];
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if ((le32toh(desc->control) & CONTROL_OWN) != 0) {
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break;
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}
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tot_copied += le32toh(desc->transferred);
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st.error = 0;
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st.transferred = le32toh(desc->transferred);
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xchan_seg_done(xchan, &st);
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chan->idx_tail = msgdma_next_desc(chan, chan->idx_tail);
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atomic_subtract_int(&chan->descs_used_count, 1);
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}
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WRITE4_DESC(sc, PF_STATUS, PF_STATUS_IRQ);
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/* Finish operation */
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status.error = 0;
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status.transferred = tot_copied;
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xdma_callback(chan->xchan, &status);
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}
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static int
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msgdma_reset(struct msgdma_softc *sc)
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{
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int timeout;
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dprintf("%s: read status: %x\n", __func__, READ4(sc, 0x00));
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dprintf("%s: read control: %x\n", __func__, READ4(sc, 0x04));
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dprintf("%s: read 1: %x\n", __func__, READ4(sc, 0x08));
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dprintf("%s: read 2: %x\n", __func__, READ4(sc, 0x0C));
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WRITE4(sc, DMA_CONTROL, CONTROL_RESET);
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timeout = 100;
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do {
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if ((READ4(sc, DMA_STATUS) & STATUS_RESETTING) == 0)
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break;
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} while (timeout--);
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dprintf("timeout %d\n", timeout);
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if (timeout == 0)
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return (-1);
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dprintf("%s: read control after reset: %x\n",
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__func__, READ4(sc, DMA_CONTROL));
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return (0);
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}
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static int
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msgdma_probe(device_t dev)
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{
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int hwtype;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (hwtype == HWTYPE_NONE)
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return (ENXIO);
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device_set_desc(dev, "Altera mSGDMA");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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msgdma_attach(device_t dev)
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{
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struct msgdma_softc *sc;
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phandle_t xref, node;
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int err;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, msgdma_spec, sc->res)) {
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device_printf(dev, "could not allocate resources for device\n");
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return (ENXIO);
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}
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/* CSR memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Descriptor memory interface */
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sc->bst_d = rman_get_bustag(sc->res[1]);
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sc->bsh_d = rman_get_bushandle(sc->res[1]);
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, msgdma_intr, sc, &sc->ih);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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node = ofw_bus_get_node(dev);
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xref = OF_xref_from_node(node);
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OF_device_register_xref(xref, dev);
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if (msgdma_reset(sc) != 0)
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return (-1);
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WRITE4(sc, DMA_CONTROL, CONTROL_GIEM);
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return (0);
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}
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static int
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msgdma_detach(device_t dev)
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{
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struct msgdma_softc *sc;
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sc = device_get_softc(dev);
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return (0);
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}
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static void
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msgdma_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
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{
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struct msgdma_channel *chan;
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chan = (struct msgdma_channel *)arg;
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KASSERT(chan != NULL, ("xchan is NULL"));
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if (err) {
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chan->map_err = 1;
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return;
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}
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chan->descs_phys[chan->map_descr].ds_addr = segs[0].ds_addr;
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chan->descs_phys[chan->map_descr].ds_len = segs[0].ds_len;
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dprintf("map desc %d: descs phys %lx len %ld\n",
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chan->map_descr, segs[0].ds_addr, segs[0].ds_len);
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}
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static int
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msgdma_desc_free(struct msgdma_softc *sc, struct msgdma_channel *chan)
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{
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struct msgdma_desc *desc;
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int nsegments;
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int i;
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nsegments = chan->descs_num;
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for (i = 0; i < nsegments; i++) {
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desc = chan->descs[i];
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bus_dmamap_unload(chan->dma_tag, chan->dma_map[i]);
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bus_dmamem_free(chan->dma_tag, desc, chan->dma_map[i]);
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}
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bus_dma_tag_destroy(chan->dma_tag);
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free(chan->descs, M_DEVBUF);
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free(chan->dma_map, M_DEVBUF);
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free(chan->descs_phys, M_DEVBUF);
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return (0);
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}
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static int
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msgdma_desc_alloc(struct msgdma_softc *sc, struct msgdma_channel *chan,
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uint32_t desc_size, uint32_t align)
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{
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int nsegments;
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int err;
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int i;
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nsegments = chan->descs_num;
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dprintf("%s: nseg %d\n", __func__, nsegments);
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err = bus_dma_tag_create(
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bus_get_dma_tag(sc->dev),
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align, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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desc_size, 1, /* maxsize, nsegments*/
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desc_size, 0, /* maxsegsize, flags */
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NULL, NULL, /* lockfunc, lockarg */
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&chan->dma_tag);
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if (err) {
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device_printf(sc->dev,
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"%s: Can't create bus_dma tag.\n", __func__);
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return (-1);
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}
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/* Descriptors. */
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chan->descs = malloc(nsegments * sizeof(struct msgdma_desc *),
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M_DEVBUF, (M_WAITOK | M_ZERO));
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if (chan->descs == NULL) {
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device_printf(sc->dev,
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"%s: Can't allocate memory.\n", __func__);
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return (-1);
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}
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chan->dma_map = malloc(nsegments * sizeof(bus_dmamap_t),
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M_DEVBUF, (M_WAITOK | M_ZERO));
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chan->descs_phys = malloc(nsegments * sizeof(bus_dma_segment_t),
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M_DEVBUF, (M_WAITOK | M_ZERO));
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/* Allocate bus_dma memory for each descriptor. */
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for (i = 0; i < nsegments; i++) {
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err = bus_dmamem_alloc(chan->dma_tag, (void **)&chan->descs[i],
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BUS_DMA_WAITOK | BUS_DMA_ZERO, &chan->dma_map[i]);
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if (err) {
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device_printf(sc->dev,
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"%s: Can't allocate memory for descriptors.\n",
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__func__);
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return (-1);
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}
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chan->map_err = 0;
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chan->map_descr = i;
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err = bus_dmamap_load(chan->dma_tag, chan->dma_map[i], chan->descs[i],
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desc_size, msgdma_dmamap_cb, chan, BUS_DMA_WAITOK);
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if (err) {
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device_printf(sc->dev,
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"%s: Can't load DMA map.\n", __func__);
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return (-1);
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}
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if (chan->map_err != 0) {
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device_printf(sc->dev,
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"%s: Can't load DMA map.\n", __func__);
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return (-1);
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}
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}
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return (0);
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}
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static int
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msgdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
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{
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struct msgdma_channel *chan;
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struct msgdma_softc *sc;
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int i;
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sc = device_get_softc(dev);
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for (i = 0; i < MSGDMA_NCHANNELS; i++) {
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chan = &sc->channels[i];
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if (chan->used == 0) {
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chan->xchan = xchan;
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xchan->chan = (void *)chan;
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xchan->caps |= XCHAN_CAP_BUSDMA;
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chan->index = i;
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chan->sc = sc;
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chan->used = 1;
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chan->idx_head = 0;
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chan->idx_tail = 0;
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chan->descs_used_count = 0;
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chan->descs_num = 1024;
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return (0);
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}
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}
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return (-1);
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}
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static int
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msgdma_channel_free(device_t dev, struct xdma_channel *xchan)
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{
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struct msgdma_channel *chan;
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struct msgdma_softc *sc;
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sc = device_get_softc(dev);
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chan = (struct msgdma_channel *)xchan->chan;
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msgdma_desc_free(sc, chan);
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chan->used = 0;
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return (0);
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}
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static int
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msgdma_channel_capacity(device_t dev, xdma_channel_t *xchan,
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uint32_t *capacity)
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{
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struct msgdma_channel *chan;
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uint32_t c;
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chan = (struct msgdma_channel *)xchan->chan;
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/* At least one descriptor must be left empty. */
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c = (chan->descs_num - chan->descs_used_count - 1);
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*capacity = c;
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return (0);
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}
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static int
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msgdma_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
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struct xdma_sglist *sg, uint32_t sg_n)
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{
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||||
struct msgdma_channel *chan;
|
||||
struct msgdma_desc *desc;
|
||||
struct msgdma_softc *sc;
|
||||
uint32_t src_addr_lo;
|
||||
uint32_t dst_addr_lo;
|
||||
uint32_t len;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct msgdma_channel *)xchan->chan;
|
||||
|
||||
for (i = 0; i < sg_n; i++) {
|
||||
src_addr_lo = (uint32_t)sg[i].src_addr;
|
||||
dst_addr_lo = (uint32_t)sg[i].dst_addr;
|
||||
len = (uint32_t)sg[i].len;
|
||||
|
||||
dprintf("%s: src %x dst %x len %d\n", __func__,
|
||||
src_addr_lo, dst_addr_lo, len);
|
||||
|
||||
desc = chan->descs[chan->idx_head];
|
||||
desc->read_lo = htole32(src_addr_lo);
|
||||
desc->write_lo = htole32(dst_addr_lo);
|
||||
desc->length = htole32(len);
|
||||
desc->transferred = 0;
|
||||
desc->status = 0;
|
||||
desc->reserved = 0;
|
||||
desc->control = 0;
|
||||
|
||||
if (sg[i].direction == XDMA_MEM_TO_DEV) {
|
||||
if (sg[i].first == 1) {
|
||||
desc->control |= htole32(CONTROL_GEN_SOP);
|
||||
}
|
||||
|
||||
if (sg[i].last == 1) {
|
||||
desc->control |= htole32(CONTROL_GEN_EOP);
|
||||
desc->control |= htole32(CONTROL_TC_IRQ_EN |
|
||||
CONTROL_ET_IRQ_EN | CONTROL_ERR_M);
|
||||
}
|
||||
} else {
|
||||
desc->control |= htole32(CONTROL_END_ON_EOP | (1 << 13));
|
||||
desc->control |= htole32(CONTROL_TC_IRQ_EN |
|
||||
CONTROL_ET_IRQ_EN | CONTROL_ERR_M);
|
||||
}
|
||||
|
||||
tmp = chan->idx_head;
|
||||
|
||||
atomic_add_int(&chan->descs_used_count, 1);
|
||||
chan->idx_head = msgdma_next_desc(chan, chan->idx_head);
|
||||
|
||||
desc->control |= htole32(CONTROL_OWN | CONTROL_GO);
|
||||
|
||||
bus_dmamap_sync(chan->dma_tag, chan->dma_map[tmp],
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
msgdma_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
|
||||
{
|
||||
struct msgdma_channel *chan;
|
||||
struct msgdma_desc *desc;
|
||||
struct msgdma_softc *sc;
|
||||
uint32_t addr;
|
||||
uint32_t reg;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
dprintf("%s(%d)\n", __func__, device_get_unit(dev));
|
||||
|
||||
chan = (struct msgdma_channel *)xchan->chan;
|
||||
|
||||
ret = msgdma_desc_alloc(sc, chan, sizeof(struct msgdma_desc), 16);
|
||||
if (ret != 0) {
|
||||
device_printf(sc->dev,
|
||||
"%s: Can't allocate descriptors.\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
for (i = 0; i < chan->descs_num; i++) {
|
||||
desc = chan->descs[i];
|
||||
|
||||
if (i == (chan->descs_num - 1)) {
|
||||
desc->next = htole32(chan->descs_phys[0].ds_addr);
|
||||
} else {
|
||||
desc->next = htole32(chan->descs_phys[i+1].ds_addr);
|
||||
}
|
||||
|
||||
dprintf("%s(%d): desc %d vaddr %lx next paddr %x\n", __func__,
|
||||
device_get_unit(dev), i, (uint64_t)desc, le32toh(desc->next));
|
||||
}
|
||||
|
||||
addr = chan->descs_phys[0].ds_addr;
|
||||
WRITE4_DESC(sc, PF_NEXT_LO, addr);
|
||||
WRITE4_DESC(sc, PF_NEXT_HI, 0);
|
||||
WRITE4_DESC(sc, PF_POLL_FREQ, 1000);
|
||||
|
||||
reg = (PF_CONTROL_GIEM | PF_CONTROL_DESC_POLL_EN);
|
||||
reg |= PF_CONTROL_RUN;
|
||||
WRITE4_DESC(sc, PF_CONTROL, reg);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
msgdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
|
||||
{
|
||||
struct msgdma_channel *chan;
|
||||
struct msgdma_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct msgdma_channel *)xchan->chan;
|
||||
|
||||
switch (cmd) {
|
||||
case XDMA_CMD_BEGIN:
|
||||
case XDMA_CMD_TERMINATE:
|
||||
case XDMA_CMD_PAUSE:
|
||||
/* TODO: implement me */
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef FDT
|
||||
static int
|
||||
msgdma_ofw_md_data(device_t dev, pcell_t *cells, int ncells, void **ptr)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static device_method_t msgdma_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, msgdma_probe),
|
||||
DEVMETHOD(device_attach, msgdma_attach),
|
||||
DEVMETHOD(device_detach, msgdma_detach),
|
||||
|
||||
/* xDMA Interface */
|
||||
DEVMETHOD(xdma_channel_alloc, msgdma_channel_alloc),
|
||||
DEVMETHOD(xdma_channel_free, msgdma_channel_free),
|
||||
DEVMETHOD(xdma_channel_control, msgdma_channel_control),
|
||||
|
||||
/* xDMA SG Interface */
|
||||
DEVMETHOD(xdma_channel_capacity, msgdma_channel_capacity),
|
||||
DEVMETHOD(xdma_channel_prep_sg, msgdma_channel_prep_sg),
|
||||
DEVMETHOD(xdma_channel_submit_sg, msgdma_channel_submit_sg),
|
||||
|
||||
#ifdef FDT
|
||||
DEVMETHOD(xdma_ofw_md_data, msgdma_ofw_md_data),
|
||||
#endif
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t msgdma_driver = {
|
||||
"msgdma",
|
||||
msgdma_methods,
|
||||
sizeof(struct msgdma_softc),
|
||||
};
|
||||
|
||||
static devclass_t msgdma_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(msgdma, simplebus, msgdma_driver, msgdma_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
||||
96
sys/dev/altera/msgdma/msgdma.h
Normal file
96
sys/dev/altera/msgdma/msgdma.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*-
|
||||
* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* Altera mSGDMA registers. */
|
||||
#define DMA_STATUS 0x00
|
||||
#define STATUS_RESETTING (1 << 6)
|
||||
#define DMA_CONTROL 0x04
|
||||
#define CONTROL_GIEM (1 << 4) /* Global Interrupt Enable Mask */
|
||||
#define CONTROL_RESET (1 << 1) /* Reset Dispatcher */
|
||||
|
||||
/* Descriptor fields. */
|
||||
#define CONTROL_GO (1 << 31) /* Commit all the descriptor info */
|
||||
#define CONTROL_OWN (1 << 30) /* Owned by hardware (prefetcher-enabled only) */
|
||||
#define CONTROL_EDE (1 << 24) /* Early done enable */
|
||||
#define CONTROL_ERR_S 16 /* Transmit Error, Error IRQ Enable */
|
||||
#define CONTROL_ERR_M (0xff << CONTROL_ERR_S)
|
||||
#define CONTROL_ET_IRQ_EN (1 << 15) /* Early Termination IRQ Enable */
|
||||
#define CONTROL_TC_IRQ_EN (1 << 14) /* Transfer Complete IRQ Enable */
|
||||
#define CONTROL_END_ON_EOP (1 << 12) /* End on EOP */
|
||||
#define CONTROL_PARK_WR (1 << 11) /* Park Writes */
|
||||
#define CONTROL_PARK_RD (1 << 10) /* Park Reads */
|
||||
#define CONTROL_GEN_EOP (1 << 9) /* Generate EOP */
|
||||
#define CONTROL_GEN_SOP (1 << 8) /* Generate SOP */
|
||||
#define CONTROL_TX_CHANNEL_S 0 /* Transmit Channel */
|
||||
#define CONTROL_TX_CHANNEL_M (0xff << CONTROL_TRANSMIT_CH_S)
|
||||
|
||||
/* Prefetcher */
|
||||
#define PF_CONTROL 0x00
|
||||
#define PF_CONTROL_GIEM (1 << 3)
|
||||
#define PF_CONTROL_RESET (1 << 2)
|
||||
#define PF_CONTROL_DESC_POLL_EN (1 << 1)
|
||||
#define PF_CONTROL_RUN (1 << 0)
|
||||
#define PF_NEXT_LO 0x04
|
||||
#define PF_NEXT_HI 0x08
|
||||
#define PF_POLL_FREQ 0x0C
|
||||
#define PF_STATUS 0x10
|
||||
#define PF_STATUS_IRQ (1 << 0)
|
||||
|
||||
#define READ4(_sc, _reg) \
|
||||
le32toh(bus_space_read_4(_sc->bst, _sc->bsh, _reg))
|
||||
#define WRITE4(_sc, _reg, _val) \
|
||||
bus_space_write_4(_sc->bst, _sc->bsh, _reg, htole32(_val))
|
||||
|
||||
#define READ4_DESC(_sc, _reg) \
|
||||
le32toh(bus_space_read_4(_sc->bst_d, _sc->bsh_d, _reg))
|
||||
#define WRITE4_DESC(_sc, _reg, _val) \
|
||||
bus_space_write_4(_sc->bst_d, _sc->bsh_d, _reg, htole32(_val))
|
||||
|
||||
/* Prefetcher-disabled descriptor format. */
|
||||
struct msgdma_desc_nonpf {
|
||||
uint32_t src_addr;
|
||||
uint32_t dst_addr;
|
||||
uint32_t length;
|
||||
uint32_t control;
|
||||
};
|
||||
|
||||
/* Prefetcher-enabled descriptor format. */
|
||||
struct msgdma_desc {
|
||||
uint32_t read_lo;
|
||||
uint32_t write_lo;
|
||||
uint32_t length;
|
||||
uint32_t next;
|
||||
uint32_t transferred;
|
||||
uint32_t status;
|
||||
uint32_t reserved;
|
||||
uint32_t control;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user