The ar and sr devices have moved to sys/dev/.

This commit is contained in:
jhay 2001-01-30 10:05:44 +00:00
parent 20531fb538
commit d692564caf
8 changed files with 0 additions and 6645 deletions

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/*
* if_ar.h
*
* Copyright (C) 1997-1999 Whistle Communications Inc.
* All rights reserved.
*
* Subject to the following obligations and disclaimer of warranty, use and
* redistribution of this software, in source or object code forms, with or
* without modifications are expressly permitted by Whistle Communications;
* provided, however, that:
* 1. Any and all reproductions of the source or object code must include the
* copyright notice above and the following disclaimer of warranties; and
* 2. No rights are granted, in any manner or form, to use Whistle
* Communications, Inc. trademarks, including the mark "WHISTLE
* COMMUNICATIONS" on advertising, endorsements, or otherwise except as
* such appears in the above copyright notice or in the software.
*
* THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
* INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
* WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
* REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
* SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
* IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
* RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
* WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _I386_ISA_IF_AR_H_
#define _I386_ISA_IF_AR_H_
/* Node type name and type cookie */
#define NG_AR_NODE_TYPE "sync_ar"
#define NG_AR_COOKIE 860552149
/* Netgraph hooks */
#define NG_AR_HOOK_DEBUG "debug"
#define NG_AR_HOOK_RAW "rawdata"
#endif /* _I386_ISA_IF_AR_H_ */

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/*
* Copyright (c) 1995 - 2001 John Hay. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IF_ARREGS_H_
#define _IF_ARREGS_H_
#define NCHAN 2 /* A HD64570 chip have 2 channels */
#define NPORT 4 /* A ArNet board can have 4 ports or */
/* channels */
#define AR_BUF_SIZ 512
#define AR_TX_BLOCKS 2
#define ARC_IO_SIZ 0x10
#define ARC_WIN_SIZ 0x00004000
#define ARC_WIN_MSK (ARC_WIN_SIZ - 1)
#define ARC_WIN_SHFT 14
/* Some PCI specific offsets. */
#define AR_PCI_SCA_1_OFFSET 0x00040000
#define AR_PCI_SCA_2_OFFSET 0x00040400
#define AR_PCI_ORBASE_OFFSET 0x00041000
#define AR_PCI_SCA_PCR 0x0208
#define AR_PCI_SCA_DMER 0x0309
/* PCI Legacy (below 1M) offsets. */
#define AR_PCI_L_SCA_1_OFFSET 0x00004000
#define AR_PCI_L_SCA_2_OFFSET 0x00004400
#define AR_PCI_L_ORBASE_OFFSET 0x00005000
#define AR_ID_5 0x00 /* RO, Card probe '5' */
#define AR_ID_7 0x01 /* RO, Card probe '7' */
#define AR_ID_0 0x02 /* RO, Card probe '0' */
#define AR_BMI 0x03 /* RO, Bus, mem and interface type */
#define AR_REV 0x04 /* RO, Adapter revision */
#define AR_PNUM 0x05 /* RO, Port number */
#define AR_HNDSH 0x06 /* RO, Supported handshake */
#define AR_ISTAT 0x07 /* RO, DCD and Interrupt status */
#define AR_MSCA_EN 0x08 /* WO, Memory and SCA enable */
#define AR_TXC_DTR0 0x09 /* WO, Tx Clock and DTR control 0 + 1 */
#define AR_SEC_PAL 0x0A /* RW, Security PAL */
#define AR_INT_ACK0 0x0B /* RO, Interrupt Acknowledge 0 + 1 */
#define AR_INT_SEL 0x0C /* RW, Interrupt Select */
#define AR_MEM_SEL 0x0D /* RW, Memory Select */
#define AR_INT_ACK2 0x0E /* RO, Interrupt Acknowledge 2 + 3 */
#define AR_TXC_DTR2 0x0E /* WO, Tx Clock and DTR control 2 + 3 */
/* PCI only */
#define AR_PIMCTRL 0x4C /* RW, PIM and LEDs */
#define AR_INT_SCB 0x50 /* RO, Interrupt Scoreboard */
#define AR_REV_MSK 0x0F
#define AR_WSIZ_MSK 0xE0
#define AR_WSIZ_SHFT 5
/* Bus memory and interface type */
#define AR_BUS_MSK 0x03
#define AR_BUS_ISA 0x00
#define AR_BUS_MCA 0x01
#define AR_BUS_EISA 0x02
#define AR_BUS_PCI 0x03
#define AR_MEM_MSK 0x1C
#define AR_MEM_SHFT 0x02
#define AR_MEM_64K 0x00
#define AR_MEM_128K 0x04
#define AR_MEM_256K 0x08
#define AR_MEM_512K 0x0C
/*
* EIA-232
* V.35/EIA-232
* EIA-530
* X.21
* EIA-530/X.21 Combo
*/
#define AR_IFACE_MSK 0xE0
#define AR_IFACE_SHFT 0x05
#define AR_IFACE_EIA_232 0x00 /* Only on the 570 card, not 570i */
#define AR_IFACE_V_35 0x20 /* Selectable between V.35 and EIA-232 */
#define AR_IFACE_EIA_530 0x40
#define AR_IFACE_X_21 0x60
#define AR_IFACE_COMBO 0xC0 /* X.21 / EIA-530 */
#define AR_IFACE_PIM 0xE0 /* PIM module */
#define AR_IFACE_LOOPBACK 0xFE
#define AR_IFACE_UNKNOWN 0xFF
/* Supported Handshake signals */
#define AR_SHSK_DTR 0x01
#define AR_SHSK_RTS 0x02
#define AR_SHSK_CTS 0x10
#define AR_SHSK_DSR 0x20
#define AR_SHSK_RI 0x40
#define AR_SHSK_DCD 0x80
/* DCD and Interrupt status */
#define AR_BD_INT 0x01
#define AR_INT_0 0x20
#define AR_INT_1 0x40
#define AR_DCD_MSK 0x1E
#define AR_DCD_SHFT 0x01
#define AR_DCD_0 0x02
#define AR_DCD_1 0x04
#define AR_DCD_2 0x08
#define AR_DCD_3 0x10
/* Memory and SCA enable */
#define AR_WIN_MSK 0x1F
#define AR_SEL_SCA_0 0x00
#define AR_SEL_SCA_1 0x20
#define AR_ENA_SCA 0x40
#define AR_ENA_MEM 0x80
/* Transmit Clock and DTR and RESET */
#define AR_TXC_DTR_TX0 0x01
#define AR_TXC_DTR_TX1 0x02
#define AR_TXC_DTR_DTR0 0x04
#define AR_TXC_DTR_DTR1 0x08
#define AR_TXC_DTR_TXCS0 0x10
#define AR_TXC_DTR_TXCS1 0x20
#define AR_TXC_DTR_NOTRESET 0x40
#define AR_TXC_DTR_RESET 0x00
/* Interrupt select register */
#define AR_INTS_CEN 0x01
#define AR_INTS_ISEL0 0x02
#define AR_INTS_ISEL1 0x04
#define AR_INTS_ISEL2 0x08
#define AR_INTS_CMA14 0x10
#define AR_INTS_CMA15 0x20
/* Advanced PIM Control */
#define AR_PIM_STROBE 0x01
#define AR_PIM_DATA 0x02
#define AR_PIM_MODEG 0x04
#define AR_PIM_A2D_STROBE 0x04
#define AR_PIM_MODEY 0x08
#define AR_PIM_A2D_DOUT 0x08
#define AR_PIM_AUTO_LED 0x10
#define AR_PIM_INT 0x20
#define AR_PIM_RESET 0x00 /* MODEG and MODEY 0 */
#define AR_PIM_READ AR_PIM_MODEG
#define AR_PIM_WRITE AR_PIM_MODEY
#define ARC_GET_WIN(addr) ((addr >> ARC_WIN_SHFT) & AR_WIN_MSK)
#define ARC_SET_MEM(iobase,win) outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
ARC_GET_WIN(win))
#define ARC_SET_SCA(iobase,ch) outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
AR_ENA_SCA | (ch ? AR_SEL_SCA_1:AR_SEL_SCA_0))
#define ARC_SET_OFF(iobase) outb(iobase+AR_MSCA_EN, 0)
struct ar_hardc {
int cunit;
struct ar_softc *sc;
u_short iobase;
int isa_irq;
int numports;
caddr_t mem_start;
caddr_t mem_end;
caddr_t plx_mem;
u_char *orbase;
u_int memsize; /* in bytes */
u_int winsize; /* in bytes */
u_int winmsk;
u_char bustype; /* ISA, MCA, PCI.... */
u_char interface[NPORT];/* X21, V.35, EIA-530.... */
u_char revision;
u_char handshake; /* handshake lines supported by card. */
u_char txc_dtr[NPORT/NCHAN]; /* the register is write only */
u_int txc_dtr_off[NPORT/NCHAN];
sca_regs *sca[NPORT/NCHAN];
bus_space_tag_t bt;
bus_space_handle_t bh;
int rid_ioport;
int rid_memory;
int rid_plx_memory;
int rid_irq;
int rid_drq;
struct resource* res_ioport; /* resource for port range */
struct resource* res_memory; /* resource for mem range */
struct resource* res_plx_memory;
struct resource* res_irq; /* resource for irq range */
struct resource* res_drq; /* resource for dma channel */
void *intr_cookie;
};
extern devclass_t ar_devclass;
int ar_allocate_ioport(device_t device, int rid, u_long size);
int ar_allocate_irq(device_t device, int rid, u_long size);
int ar_allocate_memory(device_t device, int rid, u_long size);
int ar_allocate_plx_memory(device_t device, int rid, u_long size);
int ar_deallocate_resources(device_t device);
int ar_attach(device_t device);
int ar_detach (device_t);
#endif /* _IF_ARREGS_H_ */

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/*
* if_sr.h
*
* Copyright (C) 1997-1999 Whistle Communications Inc.
* All rights reserved.
*
* Subject to the following obligations and disclaimer of warranty, use and
* redistribution of this software, in source or object code forms, with or
* without modifications are expressly permitted by Whistle Communications;
* provided, however, that:
* 1. Any and all reproductions of the source or object code must include the
* copyright notice above and the following disclaimer of warranties; and
* 2. No rights are granted, in any manner or form, to use Whistle
* Communications, Inc. trademarks, including the mark "WHISTLE
* COMMUNICATIONS" on advertising, endorsements, or otherwise except as
* such appears in the above copyright notice or in the software.
*
* THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
* INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
* WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
* REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
* SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
* IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
* RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
* WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
* $FreeBSD$
*/
#ifndef _I386_ISA_IF_SR_H_
#define _I386_ISA_IF_SR_H_
/* Node type name and type cookie */
#define NG_SR_NODE_TYPE "sync_sr"
#define NG_SR_COOKIE 860552148
/* Netgraph hooks */
#define NG_SR_HOOK_DEBUG "debug"
#define NG_SR_HOOK_RAW "rawdata"
#endif /* _I386_ISA_IF_SR_H_ */

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/*
* Copyright (c) 1995 John Hay.
* Copyright (c) 1996 SDL Communications, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IF_SRREGS_H_
#define _IF_SRREGS_H_
#define NCHAN 2 /* A HD64570 chip have 2 channels */
#define SR_BUF_SIZ 512
#define SR_TX_BLOCKS 2 /* Sepperate sets of tx buffers */
#define SR_CRD_N2 1
#define SR_CRD_N2PCI 2
/*
* RISCom/N2 ISA card.
*/
#define SRC_IO_SIZ 0x10 /* Actually a lie. It uses a lot more. */
#define SRC_WIN_SIZ 0x00004000
#define SRC_WIN_MSK (SRC_WIN_SIZ - 1)
#define SRC_WIN_SHFT 14
#define SR_FLAGS_NCHAN_MSK 0x0000000F
#define SR_FLAGS_0_CLK_MSK 0x00000030
#define SR_FLAGS_0_EXT_CLK 0x00000000 /* External RX clock shared by TX */
#define SR_FLAGS_0_EXT_SEP_CLK 0x00000010 /* Sepperate external clocks */
#define SR_FLAGS_0_INT_CLK 0x00000020 /* Internal clock */
#define SR_FLAGS_1_CLK_MSK 0x000000C0
#define SR_FLAGS_1_EXT_CLK 0x00000000 /* External RX clock shared by TX */
#define SR_FLAGS_1_EXT_SEP_CLK 0x00000040 /* Sepperate external clocks */
#define SR_FLAGS_1_INT_CLK 0x00000080 /* Internal clock */
#define SR_FLAGS_CLK_SHFT 4
#define SR_FLAGS_CLK_CHAN_SHFT 2
#define SR_FLAGS_EXT_CLK 0x00000000 /* External RX clock shared by TX */
#define SR_FLAGS_EXT_SEP_CLK 0x00000001 /* Sepperate external clocks */
#define SR_FLAGS_INT_CLK 0x00000002 /* Internal clock */
#define SR_PCR 0x00 /* RW, PC Control Register */
#define SR_BAR 0x02 /* RW, Base Address Register */
#define SR_PSR 0x04 /* RW, Page Scan Register */
#define SR_MCR 0x06 /* RW, Modem Control Register */
#define SR_PCR_SCARUN 0x01 /* !Reset */
#define SR_PCR_EN_VPM 0x02 /* Running above 1M */
#define SR_PCR_MEM_WIN 0x04 /* Open memory window */
#define SR_PCR_ISA16 0x08 /* 16 bit ISA mode */
#define SR_PCR_16M_SEL 0xF0 /* A20-A23 Addresses */
#define SR_PSR_PG_SEL 0x1F /* Page 0 - 31 select */
#define SR_PG_MSK 0x1F
#define SR_PSR_WIN_SIZ 0x60 /* Window size select */
#define SR_PSR_WIN_16K 0x00
#define SR_PSR_WIN_32K 0x20
#define SR_PSR_WIN_64K 0x40
#define SR_PSR_WIN_128K 0x60
#define SR_PSR_EN_SCA_DMA 0x80 /* Enable the SCA DMA */
#define SR_MCR_DTR0 0x01 /* Deactivate DTR0 */
#define SR_MCR_DTR1 0x02 /* Deactivate DTR1 */
#define SR_MCR_DSR0 0x04 /* DSR0 Status */
#define SR_MCR_DSR1 0x08 /* DSR1 Status */
#define SR_MCR_TE0 0x10 /* Enable RS422 TXD */
#define SR_MCR_TE1 0x20 /* Enable RS422 TXD */
#define SR_MCR_ETC0 0x40 /* Enable Ext Clock out */
#define SR_MCR_ETC1 0x80 /* Enable Ext Clock out */
/*
* RISCom/N2 PCI card.
*/
#define SR_FECR 0x0200 /* Front End Control Register */
#define SR_FECR_ETC0 0x0001 /* Enable Ext Clock out */
#define SR_FECR_ETC1 0x0002 /* Enable Ext Clock out */
#define SR_FECR_TE0 0x0004 /* Enable RS422 TXD */
#define SR_FECR_TE1 0x0008 /* Enable RS422 TXD */
#define SR_FECR_GPO0 0x0010 /* General Purpose Output */
#define SR_FECR_GPO1 0x0020 /* General Purpose Output */
#define SR_FECR_DTR0 0x0040 /* 0 for active, 1 for inactive */
#define SR_FECR_DTR1 0x0080 /* 0 for active, 1 for inactive */
#define SR_FECR_DSR0 0x0100 /* DSR0 Status */
#define SR_FECR_ID0 0x0E00 /* ID of channel 0 */
#define SR_FECR_DSR1 0x1000 /* DSR1 Status */
#define SR_FECR_ID1 0xE000 /* ID of channel 1 */
#define SR_FE_ID_V35 0x00 /* V.35 Interface */
#define SR_FE_ID_RS232 0x01 /* RS232 Interface */
#define SR_FE_ID_TEST 0x02 /* Test Board */
#define SR_FE_ID_RS422 0x03 /* RS422 Interface */
#define SR_FE_ID_HSSI 0x05 /* HSSI Interface */
#define SR_FE_ID_X21 0x06 /* X.21 Interface */
#define SR_FE_ID_NONE 0x07 /* No card present */
#define SR_FE_ID0_SHFT 9
#define SR_FE_ID1_SHFT 13
#endif /* _IF_SRREGS_H_ */

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/*
* Copyright (c) 1999 - 2001 John Hay.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <sys/rman.h>
#include <pci/pcireg.h>
#include <pci/pcivar.h>
#include <i386/isa/ic/hd64570.h>
#include <i386/isa/if_arregs.h>
#ifdef TRACE
#define TRC(x) x
#else
#define TRC(x)
#endif
#define TRCL(x) x
static int ar_pci_probe(device_t);
static int ar_pci_attach(device_t);
static device_method_t ar_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ar_pci_probe),
DEVMETHOD(device_attach, ar_pci_attach),
DEVMETHOD(device_detach, ar_detach),
{ 0, 0 }
};
static driver_t ar_pci_driver = {
"ar",
ar_pci_methods,
sizeof(struct ar_hardc),
};
DRIVER_MODULE(if_ar, pci, ar_pci_driver, ar_devclass, 0, 0);
static int
ar_pci_probe(device_t device)
{
u_int32_t type = pci_get_devid(device);
switch(type) {
case 0x5012114f:
device_set_desc(device, "Digi SYNC/570i-PCI 2 port");
return (0);
break;
case 0x5010114f:
printf("Digi SYNC/570i-PCI 2 port (mapped below 1M)\n");
printf("Please change the jumper to select linear mode.\n");
break;
case 0x5013114f:
device_set_desc(device, "Digi SYNC/570i-PCI 4 port");
return (0);
break;
case 0x5011114f:
printf("Digi SYNC/570i-PCI 4 port (mapped below 1M)\n");
printf("Please change the jumper to select linear mode.\n");
break;
default:
break;
}
return (ENXIO);
}
static int
ar_pci_attach(device_t device)
{
int error;
u_int i, tmp;
u_char *inten;
struct ar_hardc *hc;
hc = (struct ar_hardc *)device_get_softc(device);
bzero(hc, sizeof(struct ar_hardc));
error = ar_allocate_plx_memory(device, 0x10, 1);
if(error)
goto errexit;
error = ar_allocate_memory(device, 0x18, 1);
if(error)
goto errexit;
error = ar_allocate_irq(device, 0, 1);
if(error)
goto errexit;
hc->plx_mem = rman_get_virtual(hc->res_plx_memory);
hc->mem_start = rman_get_virtual(hc->res_memory);
hc->cunit = device_get_unit(device);
hc->sca[0] = (sca_regs *)(hc->mem_start + AR_PCI_SCA_1_OFFSET);
hc->sca[1] = (sca_regs *)(hc->mem_start + AR_PCI_SCA_2_OFFSET);
hc->iobase = 0;
hc->orbase = (u_char *)(hc->mem_start + AR_PCI_ORBASE_OFFSET);
tmp = hc->orbase[AR_BMI * 4];
hc->bustype = tmp & AR_BUS_MSK;
hc->memsize = (tmp & AR_MEM_MSK) >> AR_MEM_SHFT;
hc->memsize = 1 << hc->memsize;
hc->memsize <<= 16;
hc->interface[0] = (tmp & AR_IFACE_MSK);
tmp = hc->orbase[AR_REV * 4];
hc->revision = tmp & AR_REV_MSK;
hc->winsize = (1 << ((tmp & AR_WSIZ_MSK) >> AR_WSIZ_SHFT)) * 16 * 1024;
hc->mem_end = (caddr_t)(hc->mem_start + hc->winsize);
hc->winmsk = hc->winsize - 1;
hc->numports = hc->orbase[AR_PNUM * 4];
hc->handshake = hc->orbase[AR_HNDSH * 4];
for(i = 1; i < hc->numports; i++)
hc->interface[i] = hc->interface[0];
TRC(printf("arp%d: bus %x, rev %d, memstart %p, winsize %d, "
"winmsk %x, interface %x\n",
unit, hc->bustype, hc->revision, hc->mem_start, hc->winsize,
hc->winmsk, hc->interface[0]));
ar_attach(device);
/* Magic to enable the card to generate interrupts. */
inten = (u_char *)hc->plx_mem;
inten[0x69] = 0x09;
return (0);
errexit:
ar_deallocate_resources(device);
return (ENXIO);
}

View File

@ -1,138 +0,0 @@
/*
* Copyright (c) 1996 John Hay.
* Copyright (c) 1996 SDL Communications, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifdef COMPILING_LINT
#warning "The sr pci driver is broken and is not compiled with LINT"
#else
#include "sr.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <pci/pcivar.h>
#ifndef COMPAT_OLDPCI
#error "The sr device requires the old pci compatibility shims"
#endif
#ifndef BUGGY
#define BUGGY 0
#endif
/*
* The must match with the real functions in if_sr.c
*/
extern void *srattach_pci(int unit,
vm_offset_t plx_vaddr,
vm_offset_t sca_vaddr);
extern void srintr_hc(void *hc);
static const char *sr_pci_probe(pcici_t tag, pcidi_t type);
static void sr_pci_attach(pcici_t config_id, int unit);
static u_long src_count = NSR;
static struct pci_device sr_pci_driver =
{
"src",
sr_pci_probe,
sr_pci_attach,
&src_count,
NULL
};
COMPAT_PCI_DRIVER (sr_pci, sr_pci_driver);
static const char *
sr_pci_probe(pcici_t tag, pcidi_t type)
{
switch(type) {
case 0x556812aa:
return ("RISCom/N2pci");
break;
case 0x55684778:
case 0x55684877:
/*
* XXX This can probably be removed sometime.
*/
return ("RISCom/N2pci (old id)");
break;
default:
break;
}
return (0);
}
static void
sr_pci_attach(pcici_t config_id, int unit)
{
void *hc;
#if BUGGY > 0
u_int *fecr;
#endif
vm_offset_t plx_vaddr, plx_paddr, sca_vaddr, sca_paddr;
#if BUGGY > 0
printf("srp: ID %x\n", pci_conf_read(config_id, 0));
printf("srp: BADR0 %x\n", pci_conf_read(config_id, 0x10));
printf("srp: BADR1 %x\n", pci_conf_read(config_id, 0x18));
#endif
if(!pci_map_mem(config_id, 0x10, &plx_vaddr, &plx_paddr)) {
printf("srp: map failed.\n");
return;
}
#if BUGGY > 0
printf("srp: vaddr %x, paddr %x\n", plx_vaddr, plx_paddr);
#endif
if(!pci_map_mem(config_id, 0x18, &sca_vaddr, &sca_paddr)) {
printf("srp: map failed.\n");
return;
}
#if BUGGY > 0
printf("srp: vaddr %x, paddr %x\n", sca_vaddr, sca_paddr);
fecr = (u_int *)(sca_vaddr + 0x200);
printf("srp: FECR %x\n", *fecr);
#endif
hc = srattach_pci(unit, plx_vaddr, sca_vaddr);
if(!hc)
return;
if(!pci_map_int(config_id, srintr_hc, (void *)hc, &net_imask)) {
free(hc, M_DEVBUF);
return;
}
}
#endif