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allwinner: aw_thermal: Cope with DTS changes

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The upstream DTS now include the thermal device node and the SID
calibration entry.
Update our driver to cope with this change and remove the DTB
overlays that aren't needed anymore.

MFC after:	2 months
X-MFC-With:	r359934
This commit is contained in:
Emmanuel Vadot 2020-04-14 19:05:17 +00:00
parent 211b4e4259
commit d6b4447496
9 changed files with 21 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
UPDATING
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@ -26,6 +26,14 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 13.x IS SLOW:
disable the most expensive debugging functionality run
"ln -s 'abort:false,junk:false' /etc/malloc.conf".)
20200414:
Upstream DTS from Linux 5.6 was merged and they now have the SID
and THS (Secure ID controller and THermal Sensor) node present.
The DTB overlays have now been removed from the tree for the H3/H5 and
A64 SoCs and the aw_sid and aw_thermal driver have been updated to
deal with upstream DTS. If you are using those overlays you need to
remove them from loader.conf and update the DTBs on the FAT partition.
20200310:
Clang, llvm, lld, lldb, compiler-rt, libc++, libunwind and openmp have
been upgraded to 10.0.0. Please see the 20141231 entry below for

13
sys/arm/allwinner/aw_sid.c
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@ -100,7 +100,7 @@ static struct aw_sid_efuse a64_efuses[] = {
.public = true,
},
{
.name = "ths-calib",
.name = "calibration",
.desc = "Thermal Sensor Calibration Data",
.base = EFUSE_OFFSET,
.offset = 0x34,
@ -121,7 +121,7 @@ static struct aw_sid_efuse a83t_efuses[] = {
.public = true,
},
{
.name = "ths-calib",
.name = "calibration",
.desc = "Thermal Sensor Calibration Data",
.base = EFUSE_OFFSET,
.offset = 0x34,
@ -142,11 +142,11 @@ static struct aw_sid_efuse h3_efuses[] = {
.public = true,
},
{
.name = "ths-calib",
.name = "calibration",
.desc = "Thermal Sensor Calibration Data",
.base = EFUSE_OFFSET,
.offset = 0x34,
.size = 2,
.size = 4,
.id = AW_SID_FUSE_THSSENSOR,
.public = false,
},
@ -163,7 +163,7 @@ static struct aw_sid_efuse h5_efuses[] = {
.public = true,
},
{
.name = "ths-calib",
.name = "calibration",
.desc = "Thermal Sensor Calibration Data",
.base = EFUSE_OFFSET,
.offset = 0x34,
@ -350,8 +350,7 @@ aw_sid_read(device_t dev, uint32_t offset, uint32_t size, uint8_t *buffer)
sc = device_get_softc(dev);
for (i = 0; i < sc->sid_conf->nfuses; i++)
if (offset == (sc->sid_conf->efuses[i].base +
sc->sid_conf->efuses[i].offset)) {
if (offset == sc->sid_conf->efuses[i].offset) {
fuse_id = sc->sid_conf->efuses[i].id;
break;
}

14
sys/arm/allwinner/aw_thermal.c
View File

@ -267,7 +267,7 @@ static const struct aw_thermal_config h3_config = {
.thermal_per = H3_THERMAL_PER,
.to_temp = h3_to_temp,
.to_reg = h3_to_reg,
.calib0_mask = 0xffff,
.calib0_mask = 0xffffffff,
};
static int
@ -387,12 +387,12 @@ aw_thermal_init(struct aw_thermal_softc *sc)
int error;
node = ofw_bus_get_node(sc->dev);
if (nvmem_get_cell_len(node, "ths-calib") > sizeof(calib)) {
device_printf(sc->dev, "ths-calib nvmem cell is too large\n");
if (nvmem_get_cell_len(node, "calibration") > sizeof(calib)) {
device_printf(sc->dev, "calibration nvmem cell is too large\n");
return (ENXIO);
}
error = nvmem_read_cell_by_name(node, "ths-calib",
(void *)&calib, nvmem_get_cell_len(node, "ths-calib"));
error = nvmem_read_cell_by_name(node, "calibration",
(void *)&calib, nvmem_get_cell_len(node, "calibration"));
/* Read calibration settings from EFUSE */
if (error != 0) {
device_printf(sc->dev, "Cannot read THS efuse\n");
@ -624,7 +624,7 @@ aw_thermal_attach(device_t dev)
return (ENXIO);
}
if (clk_get_by_ofw_name(dev, 0, "apb", &sc->clk_apb) == 0) {
if (clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_apb) == 0) {
error = clk_enable(sc->clk_apb);
if (error != 0) {
device_printf(dev, "cannot enable apb clock\n");
@ -632,7 +632,7 @@ aw_thermal_attach(device_t dev)
}
}
if (clk_get_by_ofw_name(dev, 0, "ths", &sc->clk_ths) == 0) {
if (clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_ths) == 0) {
error = clk_set_freq(sc->clk_ths, sc->conf->clk_rate, 0);
if (error != 0) {
device_printf(dev, "cannot set ths clock rate\n");

19
sys/dts/arm/overlays/sun8i-h3-sid.dtso
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@ -1,19 +0,0 @@
/dts-v1/;
/plugin/;
/ {
compatible = "allwinner,sun8i-h3";
};
&{/soc} {
sid: eeprom@1c14000 {
compatible = "allwinner,sun8i-h3-sid";
reg = <0x1c14000 0x400>;
status = "okay";
/* Data cells */
ths_calib: calib@234 {
reg = <0x234 0x2>;
};
};
};

27
sys/dts/arm/overlays/sun8i-h3-ths.dtso
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@ -1,27 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
/ {
compatible = "allwinner,sun8i-h3";
};
&{/soc} {
ths: thermal_sensor@1c25000 {
compatible = "allwinner,sun8i-h3-ths";
reg = <0x01c25000 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
clock-names = "apb", "ths";
resets = <&ccu RST_BUS_THS>;
reset-names = "apb";
#thermal-sensor-cells = <0>;
status = "okay";
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "ths-calib";
};
};

17
sys/dts/arm64/overlays/sun50i-a64-sid.dtso
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@ -1,17 +0,0 @@
/dts-v1/;
/plugin/;
/ {
compatible = "allwinner,sun50i-a64";
};
&{/soc} {
sid: eeprom@1c14000 {
compatible = "allwinner,sun50i-a64-sid";
reg = <0x1c14000 0x400>;
ths_calib: calib@234 {
reg = <0x234 0x6>;
};
};
};

27
sys/dts/arm64/overlays/sun50i-a64-ths.dtso
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@ -1,27 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
/ {
compatible = "allwinner,sun50i-a64";
};
&{/soc} {
ths: thermal_sensor@1c25000 {
compatible = "allwinner,sun50i-a64-ths";
reg = <0x01c25000 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
clock-names = "apb", "ths";
resets = <&ccu RST_BUS_THS>;
reset-names = "apb";
#thermal-sensor-cells = <2>;
status = "okay";
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "ths-calib";
};
};

17
sys/dts/arm64/overlays/sun50i-h5-sid.dtso
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@ -1,17 +0,0 @@
/dts-v1/;
/plugin/;
/ {
compatible = "allwinner,sun50i-h5";
};
&{/soc} {
sid: eeprom@1c14000 {
compatible = "allwinner,sun50i-h5-sid";
reg = <0x1c14000 0x400>;
ths_calib: calib@234 {
reg = <0x234 0x4>;
};
};
};

26
sys/dts/arm64/overlays/sun50i-h5-ths.dtso
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@ -1,26 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
/ {
compatible = "allwinner,sun50i-h5";
};
&{/soc} {
ths: thermal_sensor@1c25000 {
compatible = "allwinner,sun50i-h5-ths";
reg = <0x01c25000 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
clock-names = "apb", "ths";
resets = <&ccu RST_BUS_THS>;
reset-names = "apb";
#thermal-sensor-cells = <1>;
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "ths-calib";
};
};