Remove this abortive attempt.
This commit is contained in:
jake
parent
b1ae8f9d32
commit
d759311779
@ -526,7 +526,6 @@ dev/ray/if_ray.c optional ray pccard
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dev/rp/rp.c optional rp
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dev/rp/rp_isa.c optional rp isa
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dev/rp/rp_pci.c optional rp pci
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dev/se/se_console.c optional se ebus
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dev/si/si.c optional si
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dev/si/si2_z280.c optional si
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dev/si/si3_t225.c optional si
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@ -1,320 +0,0 @@
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/*-
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* Copyright (c) 2002 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/types.h>
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#include <sys/conf.h>
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#include <sys/cons.h>
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#include <sys/consio.h>
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#include <sys/reboot.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/tty.h>
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#include <sys/ktr.h>
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#ifdef __sparc64__
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#include <ofw/openfirm.h>
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#include <ofw/ofw_pci.h>
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#include <machine/ofw_upa.h>
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#include <machine/resource.h>
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#include <sparc64/pci/ofw_pci.h>
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#include <sparc64/isa/ofw_isa.h>
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#include <sparc64/ebus/ebusvar.h>
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#include <dev/se/sereg.h>
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#define SE_CNREAD_1(off) \
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bus_space_read_1(&se_cntag, se_cnhandle, se_cnchan + (off))
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#define SE_CNWRITE_1(off, val) \
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bus_space_write_1(&se_cntag, se_cnhandle, se_cnchan + (off), (val))
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#define SE_CONSOLE(flags) ((flags) & 0x10)
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#define SE_FORCECONSOLE(flags) ((flags) & 0x20)
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#define SE_CHANNELS 2
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#define KTR_SE KTR_CT4
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#define CDEV_MAJOR 168
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static cn_probe_t se_cnprobe;
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static cn_init_t se_cninit;
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static cn_getc_t se_cngetc;
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static cn_checkc_t se_cncheckc;
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static cn_putc_t se_cnputc;
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static void se_cnregdump(void);
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static u_char se_cnchan;
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static struct bus_space_tag se_cntag;
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static bus_space_handle_t se_cnhandle;
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CONS_DRIVER(se, se_cnprobe, se_cninit, NULL, se_cngetc, se_cncheckc,
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se_cnputc, NULL);
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static int
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OF_traverse(phandle_t root, phandle_t *node,
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int (*func)(phandle_t, phandle_t *))
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{
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phandle_t child;
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for (child = OF_child(root); child != 0; child = OF_peer(child)) {
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if (func(child, node) == 0 ||
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OF_traverse(child, node, func) == 0)
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return (0);
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}
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return (-1);
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}
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static int
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se_cnfind(phandle_t child, phandle_t *node)
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{
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char name[8];
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if (OF_getprop(child, "name", name, sizeof(name)) != -1 &&
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strncmp(name, "se", sizeof(name)) == 0) {
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*node = child;
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return (0);
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}
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return (-1);
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}
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static int
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se_cnmap(phandle_t node, phandle_t parent)
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{
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struct isa_ranges ir[4];
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struct upa_ranges ur[4];
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struct isa_regs reg;
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vm_offset_t child;
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vm_offset_t dummy;
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vm_offset_t phys;
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phandle_t pbus;
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phandle_t bus;
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char name[32];
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int error;
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int type;
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int rsz;
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int bs;
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int cs;
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int i;
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if (OF_getprop(node, "reg", ®, sizeof(reg)) == -1 ||
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(rsz = OF_getprop(parent, "ranges", ir, sizeof(ir))) == -1) {
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return (ENXIO);
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}
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phys = ISA_REG_PHYS(®);
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dummy = phys + 8;
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type = ofw_isa_map_iorange(ir, rsz / sizeof(*ir), &phys, &dummy);
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if (type == SYS_RES_MEMORY) {
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cs = PCI_CS_MEM32;
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bs = PCI_MEMORY_BUS_SPACE;
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} else {
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cs = PCI_CS_IO;
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bs = PCI_IO_BUS_SPACE;
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}
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bus = OF_parent(parent);
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if (OF_getprop(bus, "name", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "pci") != 0)
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return (ENXIO);
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while ((pbus = OF_parent(bus)) != 0) {
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if (OF_getprop(pbus, "name", name, sizeof(name)) != -1) {
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "pci") != 0)
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break;
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}
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bus = pbus;
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}
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if (pbus == 0)
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return (ENXIO);
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if ((rsz = OF_getprop(bus, "ranges", ur, sizeof(ur))) == -1)
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return (ENXIO);
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error = ENXIO;
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for (i = 0; i < (rsz / sizeof(ur[0])); i++) {
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child = UPA_RANGE_CHILD(&ur[i]);
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if (UPA_RANGE_CS(&ur[i]) == cs && phys >= child &&
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phys - child < UPA_RANGE_SIZE(&ur[i])) {
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se_cnhandle = sparc64_fake_bustag(bs,
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UPA_RANGE_PHYS(&ur[i]) + phys, &se_cntag);
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error = 0;
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break;
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}
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}
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return (error);
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}
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static void
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se_cnprobe(struct consdev *cn)
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{
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phandle_t parent;
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phandle_t node;
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phandle_t root;
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char name[8];
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int channel;
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int disabled;
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int flags;
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disabled = 0;
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cn->cn_pri = CN_DEAD;
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if ((root = OF_peer(0)) == -1 ||
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OF_traverse(root, &node, se_cnfind) == -1)
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return;
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for (channel = 0; channel < SE_CHANNELS; channel++) {
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if (resource_int_value("se", channel, "disabled",
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&disabled) != 0) {
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disabled = 0;
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}
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if (resource_int_value("se", channel, "flags", &flags) == 0) {
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if (!disabled && SE_CONSOLE(flags))
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goto map;
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}
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}
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return;
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map:
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if ((parent = OF_parent(node)) <= 0 ||
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OF_getprop(parent, "name", name, sizeof(name)) <= 0)
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return;
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if (strncmp(name, "ebus", sizeof(name)) != 0)
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return;
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if (se_cnmap(node, parent) != 0)
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return;
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se_cnchan = (channel == 0 ? SE_CHA : SE_CHB);
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cn->cn_dev = makedev(CDEV_MAJOR, channel);
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cn->cn_pri = SE_FORCECONSOLE(flags) || boothowto & RB_SERIAL ?
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CN_REMOTE : CN_NORMAL;
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}
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static void
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se_cninit(struct consdev *cn)
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{
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u_char ccr0;
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/*
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* Power down the chip for initialization.
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*/
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SE_CNWRITE_1(SE_CCR0, 0x0);
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/*
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* Now program the chip for polled asynchronous serial io.
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*/
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SE_CNWRITE_1(SE_CCR0, CCR0_MCE | CCR0_SM_ASYNC);
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SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES);
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SE_CNWRITE_1(SE_CCR1, CCR1_ODS | CCR1_BCR | CCR1_CM_7);
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SE_CNWRITE_1(SE_BGR, SE_DIV_9600);
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SE_CNWRITE_1(SE_CCR2, CCR2_TOE | CCR2_SSEL | CCR2_BDF);
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SE_CNWRITE_1(SE_CCR3, 0x0);
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SE_CNWRITE_1(SE_CCR4, CCR4_EBRG | CCR4_MCK4);
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SE_CNWRITE_1(SE_MODE, MODE_FCTS | MODE_RAC | MODE_RTS);
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SE_CNWRITE_1(SE_DAFO, DAFO_CHL_8);
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SE_CNWRITE_1(SE_RFC, RFC_DPS | RFC_RFTH_32);
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SE_CNWRITE_1(SE_IPC, IPC_VIS);
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/*
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* Now power up the chip again.
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*/
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ccr0 = SE_CNREAD_1(SE_CCR0);
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ccr0 |= CCR0_PU;
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SE_CNWRITE_1(SE_CCR0, ccr0);
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SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES);
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}
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static int
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se_cngetc(dev_t dev)
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{
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u_char c;
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while ((SE_CNREAD_1(SE_STAR) & (STAR_CEC | STAR_RFNE)) != STAR_RFNE)
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;
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SE_CNWRITE_1(SE_CMDR, CMDR_RFRD);
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while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0)
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;
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c = SE_CNREAD_1(SE_RFIFO);
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SE_CNWRITE_1(SE_CMDR, CMDR_RMC);
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return (c);
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}
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static int
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se_cncheckc(dev_t dev)
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{
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u_char c;
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if ((SE_CNREAD_1(SE_STAR) & STAR_RFNE) != 0) {
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while ((SE_CNREAD_1(SE_STAR) & STAR_CEC) != 0)
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;
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SE_CNWRITE_1(SE_CMDR, CMDR_RFRD);
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while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0)
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;
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c = SE_CNREAD_1(SE_RFIFO);
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SE_CNWRITE_1(SE_CMDR, CMDR_RMC);
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return (c);
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}
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return (-1);
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}
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static void
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se_cnputc(dev_t dev, int c)
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{
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while ((SE_CNREAD_1(SE_STAR) & (STAR_CTS | STAR_CEC | STAR_XFW)) !=
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(STAR_CTS | STAR_XFW))
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;
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SE_CNWRITE_1(SE_XFIFO, c);
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SE_CNWRITE_1(SE_CMDR, CMDR_XF);
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}
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static void
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se_cnregdump(void)
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{
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CTR1(KTR_SE, "se_cnprobe: mode=%#x", SE_CNREAD_1(SE_MODE));
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CTR1(KTR_SE, "se_cnprobe: timr=%#x", SE_CNREAD_1(SE_TIMR));
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CTR1(KTR_SE, "se_cnprobe: xon=%#x", SE_CNREAD_1(SE_XON));
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CTR1(KTR_SE, "se_cnprobe: xoff=%#x", SE_CNREAD_1(SE_XOFF));
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CTR1(KTR_SE, "se_cnprobe: tcr=%#x", SE_CNREAD_1(SE_TCR));
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CTR1(KTR_SE, "se_cnprobe: dafo=%#x", SE_CNREAD_1(SE_DAFO));
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CTR1(KTR_SE, "se_cnprobe: rfc=%#x", SE_CNREAD_1(SE_RFC));
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CTR1(KTR_SE, "se_cnprobe: ccr0=%#x", SE_CNREAD_1(SE_CCR0));
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CTR1(KTR_SE, "se_cnprobe: ccr1=%#x", SE_CNREAD_1(SE_CCR1));
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CTR1(KTR_SE, "se_cnprobe: ccr2=%#x", SE_CNREAD_1(SE_CCR2));
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CTR1(KTR_SE, "se_cnprobe: ccr3=%#x", SE_CNREAD_1(SE_CCR3));
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CTR1(KTR_SE, "se_cnprobe: vstr=%#x", SE_CNREAD_1(SE_VSTR));
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CTR1(KTR_SE, "se_cnprobe: ipc=%#x", SE_CNREAD_1(SE_IPC));
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CTR1(KTR_SE, "se_cnprobe: ccr4=%#x", SE_CNREAD_1(SE_CCR4));
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}
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#endif
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@ -1,205 +0,0 @@
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/*-
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* Copyright (c) 2002 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_SE_SEREG_H_
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#define _DEV_SE_SEREG_H_
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#define SE_DIV(n, m) (((m) << 6) | ((n) - 1))
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#define SE_DIV_9600 SE_DIV(48, 2)
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#define SE_DIV_19200 SE_DIV(48, 1)
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#define SE_DIV_38400 SE_DIV(24, 1)
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#define SE_DIV_115200 SE_DIV(8, 1)
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#define SE_CHA 0x0 /* channel a offset */
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#define SE_CHB 0x40 /* channel b offset */
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#define SE_RFIFO 0x0 /* receive fifo */
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#define SE_XFIFO 0x0 /* transmit fifo */
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#define SE_STAR 0x20 /* status register */
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#define STAR_CTS 0x2 /* clear to send state */
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#define STAR_CEC 0x4 /* command executing */
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#define STAR_TEC 0x8 /* tic executing */
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#define STAR_FCS 0x10 /* flow control status */
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#define STAR_RFNE 0x20 /* receive fifo not empty */
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#define STAR_XFW 0x40 /* transmit fifo write enable */
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#define STAR_XDOV 0x80 /* transmit data overflow */
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#define SE_CMDR 0x20 /* command register */
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#define CMDR_XRES 0x1 /* transmitter reset */
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#define CMDR_XF 0x8 /* transmit frame */
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#define CMDR_STI 0x10 /* start timer */
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#define CMDR_RFRD 0x20 /* receive fifo read enable */
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#define CMDR_RRES 0x40 /* reveiver reset */
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#define CMDR_RMC 0x80 /* receive message complete */
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#define SE_MODE 0x22 /* mode register */
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#define MODE_TLP 0x1 /* test loop */
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#define MODE_TRS 0x2 /* timer resolution */
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#define MODE_RTS 0x4 /* request to send */
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#define MODE_RAC 0x8 /* receiver active */
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#define MODE_FLON 0x10 /* flow control on */
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#define MODE_FCTS 0x20 /* flow control using cts */
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#define MODE_FRTS 0x40 /* flow control using rts */
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#define SE_TIMR 0x23 /* timer register */
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#define SE_XON 0x24 /* xon character */
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#define SE_XOFF 0x25 /* xoff character */
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#define SE_TCR 0x26 /* transmit character register */
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#define SE_DAFO 0x27 /* data format */
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#define DAFO_CHL 0x2 /* character length */
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#define DAFO_CHL_8 0x0 /* 8 bits */
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#define DAFO_CHL_7 0x1 /* 7 bits */
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#define DAFO_CHL_6 0x2 /* 6 bits */
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#define DAFO_CHL_5 0x3 /* 5 bits */
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#define DAFO_PARE 0x4 /* parity enable */
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#define DAFO_PAR 0x18 /* parity format */
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#define DAFO_STOP 0x20 /* stop bit */
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#define DAFO_XBRK 0x40 /* transmit break */
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#define SE_RFC 0x28 /* rfifo control register */
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#define RFC_TCDE 0x1 /* termination character detection enable */
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#define RFC_RFTH 0xc /* rfifo threshold level */
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#define RFC_RFTH_2 0x0 /* 2 bytes */
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#define RFC_RFTH_4 0x4 /* 4 bytes */
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#define RFC_RFTH_16 0x8 /* 16 bytes */
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#define RFC_RFTH_32 0xc /* 32 bytes */
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#define RFC_RFDF 0x10 /* rfifo data format */
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||||
#define RFC_DXS 0x20 /* disable storage of xon/xoff characters */
|
||||
#define RFC_DPS 0x40 /* disable parity storage */
|
||||
|
||||
#define SE_RBCL 0x2a /* receive byte count low */
|
||||
#define SE_XBCL 0x2a /* transmit byte count low */
|
||||
#define SE_RBCH 0x2b /* receive byte count high */
|
||||
#define SE_XBCH 0x2b /* transmit byte count high */
|
||||
|
||||
#define SE_CCR0 0x2c /* channel configuration register 0 */
|
||||
#define CCR0_SM 0x3 /* serial mode */
|
||||
#define CCR0_SM_HDLC 0x0 /* hdlc/sdlc mode */
|
||||
#define CCR0_SM_SDLC 0x1 /* sdlc loop mode */
|
||||
#define CCR0_SM_BISYNC 0x2 /* bisync mode */
|
||||
#define CCR0_SM_ASYNC 0x3 /* async mode */
|
||||
#define CCR0_SC 0x1c /* serial configuration */
|
||||
#define CCR0_SC_NRZ 0x0 /* nrz data encoding */
|
||||
#define CCR0_SC_NRZI 0x2 /* nrzi data encoding */
|
||||
#define CCR0_SC_FM0 0x4 /* fm0 data encoding */
|
||||
#define CCR0_SC_FM1 0x5 /* fm1 data encoding */
|
||||
#define CCR0_SC_MCHSTR 0x6 /* manchester data encoding */
|
||||
#define CCR0_MCE 0x40 /* master clock enable */
|
||||
#define CCR0_PU 0x80 /* power up */
|
||||
|
||||
#define SE_CCR1 0x2d /* channel configuration register 1 */
|
||||
#define CCR1_CM 0x7 /* clock mode */
|
||||
#define CCR1_CM_7 0x7 /* clock mode 7 */
|
||||
#define CCR1_BCR 0x8 /* bit clock rate */
|
||||
#define CCR1_ODS 0x10 /* output driver select */
|
||||
|
||||
#define SE_CCR2 0x2e /* channel configuration register 2 */
|
||||
#define CCR2_DIV 0x1 /* data inversion */
|
||||
#define CCR2_RWX 0x4 /* read/write exchange */
|
||||
#define CCR2_TOE 0x8 /* txclk ouput enable */
|
||||
#define CCR2_SSEL 0x10 /* clock source select */
|
||||
#define CCR2_BDF 0x20 /* baud rate division factor */
|
||||
#define CCR2_BR8 0x40 /* baud rate 8 */
|
||||
#define CCR2_BR9 0x80 /* baud rate 9 */
|
||||
#define CCR2_RCS0 0x10 /* receive clock shift 0 (5) */
|
||||
#define CCR2_XCS0 0x20 /* transmit clock shift 0 (5) */
|
||||
#define CCR2_SOC0 0x40 /* special output control 0 (0a, 1, 4, 5) */
|
||||
#define CCR2_SOC1 0x80 /* special output control 1 (0a, 1, 4, 5) */
|
||||
|
||||
#define SE_CCR3 0x2f /* channel configuration register 3 */
|
||||
#define CCR3_PSD 0x1 /* dpll phase shift disable */
|
||||
|
||||
#define SE_TSAX 0x30 /* transmit timeslot assignment register */
|
||||
#define SE_TSAR 0x31 /* receive timeslot assignment register */
|
||||
#define SE_XCCR 0x32 /* transmit channel capacity register */
|
||||
#define SE_RCCR 0x33 /* receive channel capacity register */
|
||||
|
||||
#define SE_VSTR 0x34 /* version status register */
|
||||
#define VSTR_VN 0xf /* version number 0 */
|
||||
#define VSTR_DPLA 0x40 /* dpll asynchronous */
|
||||
#define VSTR_CD 0x80 /* carrier detect */
|
||||
|
||||
#define SE_BGR 0x34 /* baud rate generator register */
|
||||
#define SE_TIC 0x35 /* trasmit immediate character */
|
||||
#define SE_MXN 0x36 /* mask xon character */
|
||||
#define SE_MXF 0x37 /* mask xoff character */
|
||||
|
||||
#define SE_GIS 0x38 /* global interrupt status */
|
||||
#define GIS_ISB0 0x1 /* interrupt status channel B 0 */
|
||||
#define GIS_ISB1 0x2 /* interrupt status channel B 1 */
|
||||
#define GIS_ISA0 0x4 /* interrupt status channel A 0 */
|
||||
#define GIS_ISA1 0x8 /* interrupt status channel A 1 */
|
||||
#define GIS_PI 0x80 /* univerisal port interrupt */
|
||||
|
||||
#define SE_IVA 0x38 /* interrupt vector address */
|
||||
|
||||
#define SE_IPC 0x39 /* interrupt port configuration */
|
||||
#define IPC_IC0 0x1 /* interrupt configuration 0 */
|
||||
#define IPC_IC1 0x2 /* interrupt configuration 1 */
|
||||
#define IPC_CASM 0x4 /* cascading mode */
|
||||
#define IPC_SLA0 0x8 /* slave address 0 */
|
||||
#define IPC_SLA1 0x10 /* slave address 1 */
|
||||
#define IPC_VIS 0x80 /* masked interrupts visible */
|
||||
|
||||
#define SE_ISR0 0x3a /* interrupt status 0 */
|
||||
#define ISR0_RPF 0x1 /* receive pool full */
|
||||
#define ISR0_RFO 0x2 /* receive frame overflow */
|
||||
#define ISR0_CDSC 0x4 /* carrier detect status change */
|
||||
#define ISR0_PLLA 0x8 /* dpll asynchronous */
|
||||
#define ISR0_FERR 0x10 /* framing error */
|
||||
#define ISR0_PERR 0x20 /* parity error */
|
||||
#define ISR0_TIME 0x40 /* time out */
|
||||
#define ISR0_TCD 0x80 /* termination character detected */
|
||||
|
||||
#define SE_IMR0 0x3a /* interrupt mask 0 */
|
||||
|
||||
#define SE_ISR1 0x3b /* interrupt status 1 */
|
||||
#define ISR1_XPR 0x1 /* transmit pool ready */
|
||||
#define ISR1_XON 0x2 /* transmit message repeat */
|
||||
#define ISR1_CSC 0x4 /* clear to send status change */
|
||||
#define ISR1_TIN 0x8 /* timer interrupt */
|
||||
#define ISR1_XOFF 0x10 /* xoff character detected */
|
||||
#define ISR1_ALLS 0x20 /* all sent */
|
||||
#define ISR1_BRKT 0x40 /* break terminated */
|
||||
#define ISR1_BRK 0x80 /* break */
|
||||
|
||||
#define SE_IMR1 0x3b /* interrupt mask 1 */
|
||||
#define SE_PVR 0x3c /* port value register */
|
||||
#define SE_PIS 0x3d /* port interrupt status */
|
||||
#define SE_PIM 0x3d /* port interrupt mask */
|
||||
#define SE_PCR 0x3e /* port configuration register */
|
||||
|
||||
#define SE_CCR4 0x3f /* channel configuration register 4 */
|
||||
#define CCR4_ICD 0x10 /* invert polarity of carrier detect signal */
|
||||
#define CCR4_TST1 0x20 /* test pin */
|
||||
#define CCR4_EBRG 0x40 /* enhanced baud rate generator mode */
|
||||
#define CCR4_MCK4 0x80 /* master clock divide by 4 */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user