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qlxge: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:56:30 +00:00
parent 790cd2071a
commit d7c853dee0
12 changed files with 26 additions and 165 deletions
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6
sys/dev/qlxge/qls_dbg.c
View File

@ -41,7 +41,6 @@ __FBSDID("$FreeBSD$");
#include "qls_glbl.h" #include "qls_glbl.h"
#include "qls_dbg.h" #include "qls_dbg.h"
uint32_t qls_dbg_level = 0 ; uint32_t qls_dbg_level = 0 ;
/* /*
* Name: qls_dump_buf32 * Name: qls_dump_buf32
@ -162,7 +161,7 @@ qls_dump_buf8(qla_host_t *ha, const char *msg, void *dbuf, uint32_t len)
buf = dbuf; buf = dbuf;
device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len); device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
while (len >= 16) { while (len >= 16) {
device_printf(dev,"0x%08x:" device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x" " %02x %02x %02x %02x %02x %02x %02x %02x"
@ -265,7 +264,7 @@ qls_dump_buf8(qla_host_t *ha, const char *msg, void *dbuf, uint32_t len)
default: default:
break; break;
} }
device_printf(dev, "%s: %s dump end\n", __func__, msg); device_printf(dev, "%s: %s dump end\n", __func__, msg);
return; return;
@ -306,4 +305,3 @@ qls_dump_cq(qla_host_t *ha)
return; return;
} }

2
sys/dev/qlxge/qls_dbg.h
View File

@ -48,7 +48,6 @@ extern void qls_dump_buf32(qla_host_t *ha, const char *str, void *dbuf,
extern void qls_dump_cq(qla_host_t *ha); extern void qls_dump_cq(qla_host_t *ha);
#ifdef QL_DBG #ifdef QL_DBG
#define QL_DPRINT1(x) if (qls_dbg_level & 0x0001) device_printf x #define QL_DPRINT1(x) if (qls_dbg_level & 0x0001) device_printf x
@ -92,5 +91,4 @@ extern void qls_dump_cq(qla_host_t *ha);
#endif #endif
#endif /* #ifndef _QL_DBG_H_ */ #endif /* #ifndef _QL_DBG_H_ */

9
sys/dev/qlxge/qls_def.h
View File

@ -96,7 +96,6 @@ struct qla_tx_buf {
typedef struct qla_tx_buf qla_tx_buf_t; typedef struct qla_tx_buf qla_tx_buf_t;
struct qla_tx_ring { struct qla_tx_ring {
volatile struct { volatile struct {
uint32_t wq_dma:1, uint32_t wq_dma:1,
privb_dma:1; privb_dma:1;
@ -119,7 +118,7 @@ struct qla_tx_ring {
uint32_t *txr_cons_vaddr; uint32_t *txr_cons_vaddr;
bus_addr_t txr_cons_paddr; bus_addr_t txr_cons_paddr;
volatile uint32_t txr_free; /* # of free entries in tx ring */ volatile uint32_t txr_free; /* # of free entries in tx ring */
volatile uint32_t txr_next; /* # next available tx ring entry */ volatile uint32_t txr_next; /* # next available tx ring entry */
volatile uint32_t txr_done; volatile uint32_t txr_done;
@ -147,7 +146,6 @@ typedef struct qla_tx_ring qla_tx_ring_t;
#define QLA_LGBQ_AND_TABLE_SIZE \ #define QLA_LGBQ_AND_TABLE_SIZE \
((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1)) ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
/* Please note that Small Buffer size is determined by max mtu size */ /* Please note that Small Buffer size is determined by max mtu size */
#define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS #define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS
@ -222,7 +220,6 @@ struct qla_rx_ring {
}; };
typedef struct qla_rx_ring qla_rx_ring_t; typedef struct qla_rx_ring qla_rx_ring_t;
#define QLA_WATCHDOG_CALLOUT_TICKS 1 #define QLA_WATCHDOG_CALLOUT_TICKS 1
/* /*
@ -326,7 +323,7 @@ struct qla_host {
uint8_t mac_addr[ETHER_ADDR_LEN]; uint8_t mac_addr[ETHER_ADDR_LEN];
uint32_t nmcast; uint32_t nmcast;
qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
/* Link Related */ /* Link Related */
uint8_t link_up; uint8_t link_up;
uint32_t link_status; uint32_t link_status;
@ -358,7 +355,7 @@ struct qla_host {
/* mpi dump related */ /* mpi dump related */
qla_dma_t mpi_dma; qla_dma_t mpi_dma;
qla_dma_t rss_dma; qla_dma_t rss_dma;
}; };
typedef struct qla_host qla_host_t; typedef struct qla_host qla_host_t;

23
sys/dev/qlxge/qls_dump.c
View File

@ -33,7 +33,6 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "qls_os.h" #include "qls_os.h"
#include "qls_hw.h" #include "qls_hw.h"
#include "qls_def.h" #include "qls_def.h"
@ -380,7 +379,6 @@ qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit)
int count = 10; int count = 10;
while (count) { while (count) {
data = READ_REG32(ha, reg); data = READ_REG32(ha, reg);
if (data & err_bit) if (data & err_bit)
@ -439,7 +437,6 @@ qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data)
return (ret); return (ret);
} }
#define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002
#define Q81_INVALID_NUM 0xFFFFFFFF #define Q81_INVALID_NUM 0xFFFFFFFF
@ -528,7 +525,6 @@ qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit,
int count = 10; int count = 10;
while (count) { while (count) {
data = qls_rd_ofunc_reg(ha, reg); data = qls_rd_ofunc_reg(ha, reg);
if (data & err_bit) if (data & err_bit)
@ -685,7 +681,6 @@ qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump)
temp = 0; temp = 0;
if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) {
if (ha->pci_func & 1) if (ha->pci_func & 1)
xfi_ind_valid = 1; /* NIC 2, so the indirect xfi_ind_valid = 1; /* NIC 2, so the indirect
(NIC1) xfi is up*/ (NIC1) xfi is up*/
@ -694,7 +689,6 @@ qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump)
} }
if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) {
if(ha->pci_func & 1) if(ha->pci_func & 1)
xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1)
xfi is up */ xfi is up */
@ -855,7 +849,6 @@ qls_get_intr_states(qla_host_t *ha, uint32_t *buf)
int i; int i;
for (i = 0; i < MAX_RX_RINGS; i++, buf++) { for (i = 0; i < MAX_RX_RINGS; i++, buf++) {
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
*buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
@ -892,7 +885,6 @@ qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func)
int i; int i;
for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) {
switch (i) { switch (i) {
case Q81_PAUSE_SRC_LO : case Q81_PAUSE_SRC_LO :
case Q81_PAUSE_SRC_HI : case Q81_PAUSE_SRC_HI :
@ -1158,7 +1150,6 @@ qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func)
default: default:
break; break;
} }
} }
return 0; return 0;
@ -1170,7 +1161,6 @@ qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count)
int i, ret = 0; int i, ret = 0;
for (i = 0; i < count; i++, buf++) { for (i = 0; i < count; i++, buf++) {
ret = qls_rd_mpi_reg(ha, (offset + i), buf); ret = qls_rd_mpi_reg(ha, (offset + i), buf);
if (ret) if (ret)
@ -1191,7 +1181,6 @@ qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf)
#define Q81_SHADOW_OFFSET 0xb0000000 #define Q81_SHADOW_OFFSET 0xb0000000
for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) {
ret = qls_wr_mpi_reg(ha, ret = qls_wr_mpi_reg(ha,
(Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124),
(Q81_SHADOW_OFFSET | i << 20)); (Q81_SHADOW_OFFSET | i << 20));
@ -1225,11 +1214,8 @@ qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf)
uint32_t module, mux_sel, probe, lo_val, hi_val; uint32_t module, mux_sel, probe, lo_val, hi_val;
for (module = 0; module < Q81_MAX_MODULES; module ++) { for (module = 0; module < Q81_MAX_MODULES; module ++) {
if (valid[module]) { if (valid[module]) {
for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) {
probe = clock | Q81_ADDRESS_REGISTER_ENABLE | probe = clock | Q81_ADDRESS_REGISTER_ENABLE |
mux_sel | (module << 9); mux_sel | (module << 9);
WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
@ -1300,7 +1286,6 @@ qls_get_probe_dump(qla_host_t *ha, uint32_t *buf)
0 // 0x1F 0 // 0x1F
}; };
uint8_t pci_clock_valid_modules[0x20] = { uint8_t pci_clock_valid_modules[0x20] = {
1, // 0x00 1, // 0x00
0, // 0x01 0, // 0x01
@ -1336,7 +1321,6 @@ qls_get_probe_dump(qla_host_t *ha, uint32_t *buf)
0 // 0x1F 0 // 0x1F
}; };
uint8_t xgm_clock_valid_modules[0x20] = { uint8_t xgm_clock_valid_modules[0x20] = {
1, // 0x00 1, // 0x00
0, // 0x01 0, // 0x01
@ -1435,7 +1419,6 @@ qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf)
idx_max = 16; idx_max = 16;
for (idx = 0; idx < idx_max; idx ++) { for (idx = 0; idx < idx_max; idx ++) {
val = 0x04000000 | (type << 16) | (idx << 8); val = 0x04000000 | (type << 16) | (idx << 8);
WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val);
@ -1476,7 +1459,6 @@ qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf)
for (type = 0; type < Q81_NUM_TYPES; type ++) { for (type = 0; type < Q81_NUM_TYPES; type ++) {
switch (type) { switch (type) {
case 0: // CAM case 0: // CAM
initial_val = Q81_RS_AND_ADR; initial_val = Q81_RS_AND_ADR;
max_index = 512; max_index = 512;
@ -1540,9 +1522,7 @@ qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf)
} }
for (index = 0; index < max_index; index ++) { for (index = 0; index < max_index; index ++) {
for (offset = 0; offset < max_offset; offset ++) { for (offset = 0; offset < max_offset; offset ++) {
val = initial_val | (type << 16) | val = initial_val | (type << 16) |
(index << 4) | (offset); (index << 4) | (offset);
@ -1663,7 +1643,6 @@ qls_mpi_core_dump(qla_host_t *ha)
qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1);
} }
qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr,
Q81_XAUI1_AN_SEG_NUM, Q81_XAUI1_AN_SEG_NUM,
(sizeof(qls_mpid_seg_hdr_t) + (sizeof(qls_mpid_seg_hdr_t) +
@ -1928,7 +1907,6 @@ qls_mpi_core_dump(qla_host_t *ha)
"Sem Registers"); "Sem Registers");
for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) {
reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) |
(Q81_CTL_SEMAPHORE >> 2); (Q81_CTL_SEMAPHORE >> 2);
@ -1991,4 +1969,3 @@ qls_mpi_core_dump(qla_host_t *ha)
return 0; return 0;
} }

1
sys/dev/qlxge/qls_dump.h
View File

@ -276,4 +276,3 @@ typedef struct qls_mpi_coredump qls_mpi_coredump_t;
#define Q81_BAD_DATA 0xDEADBEEF #define Q81_BAD_DATA 0xDEADBEEF
#endif /* #ifndef _QLS_DUMP_H_ */ #endif /* #ifndef _QLS_DUMP_H_ */

60
sys/dev/qlxge/qls_hw.c
View File

@ -35,8 +35,6 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "qls_os.h" #include "qls_os.h"
#include "qls_hw.h" #include "qls_hw.h"
#include "qls_def.h" #include "qls_def.h"
@ -76,7 +74,6 @@ static int qls_alloc_rss_dma(qla_host_t *ha);
static int qls_flash_validate(qla_host_t *ha, const char *signature); static int qls_flash_validate(qla_host_t *ha, const char *signature);
static int qls_wait_for_proc_addr_ready(qla_host_t *ha); static int qls_wait_for_proc_addr_ready(qla_host_t *ha);
static int qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_module, static int qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_module,
uint32_t reg, uint32_t *data); uint32_t reg, uint32_t *data);
@ -112,7 +109,6 @@ qls_syctl_mpi_dump(SYSCTL_HANDLER_ARGS)
if (err || !req->newptr) if (err || !req->newptr)
return (err); return (err);
if (ret == 1) { if (ret == 1) {
ha = (qla_host_t *)arg1; ha = (qla_host_t *)arg1;
qls_mpi_core_dump(ha); qls_mpi_core_dump(ha);
@ -131,7 +127,6 @@ qls_syctl_link_status(SYSCTL_HANDLER_ARGS)
if (err || !req->newptr) if (err || !req->newptr)
return (err); return (err);
if (ret == 1) { if (ret == 1) {
ha = (qla_host_t *)arg1; ha = (qla_host_t *)arg1;
qls_mbx_get_link_status(ha); qls_mbx_get_link_status(ha);
@ -217,7 +212,6 @@ qls_alloc_dma(qla_host_t *ha)
return (0); return (0);
} }
static int static int
qls_wait_for_mac_proto_idx_ready(qla_host_t *ha, uint32_t op) qls_wait_for_mac_proto_idx_ready(qla_host_t *ha, uint32_t op)
{ {
@ -262,7 +256,7 @@ qls_config_unicast_mac_addr(qla_host_t *ha, uint32_t add_mac)
ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW); ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW);
if (ret) if (ret)
goto qls_config_unicast_mac_addr_exit; goto qls_config_unicast_mac_addr_exit;
index = 128 * (ha->pci_func & 0x1); /* index */ index = 128 * (ha->pci_func & 0x1); /* index */
value = (index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) | value = (index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) |
@ -328,7 +322,7 @@ qls_config_mcast_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac,
ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW); ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW);
if (ret) if (ret)
goto qls_config_mcast_mac_addr_exit; goto qls_config_mcast_mac_addr_exit;
value = Q81_CTL_MAC_PROTO_AI_E | value = Q81_CTL_MAC_PROTO_AI_E |
(index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) | (index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) |
Q81_CTL_MAC_PROTO_AI_TYPE_MCAST ; Q81_CTL_MAC_PROTO_AI_TYPE_MCAST ;
@ -388,7 +382,6 @@ qls_load_route_idx_reg(qla_host_t *ha, uint32_t index, uint32_t data)
goto qls_load_route_idx_reg_exit; goto qls_load_route_idx_reg_exit;
} }
WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index); WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index);
WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data); WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data);
@ -481,7 +474,6 @@ qls_reset_allmulti(qla_host_t *ha)
return; return;
} }
static int static int
qls_init_fw_routing_table(qla_host_t *ha) qls_init_fw_routing_table(qla_host_t *ha)
{ {
@ -596,7 +588,6 @@ qls_tx_tso_chksum(qla_host_t *ha, struct mbuf *mp, q81_tx_tso_t *tx_mac)
} }
tx_mac->vlan_off |= Q81_TX_TSO_VLAN_OFF_IC ; tx_mac->vlan_off |= Q81_TX_TSO_VLAN_OFF_IC ;
if (ip->ip_p == IPPROTO_TCP) { if (ip->ip_p == IPPROTO_TCP) {
tx_mac->flags |= Q81_TX_TSO_FLAGS_TC; tx_mac->flags |= Q81_TX_TSO_FLAGS_TC;
} else if (ip->ip_p == IPPROTO_UDP) { } else if (ip->ip_p == IPPROTO_UDP) {
@ -702,10 +693,9 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
tx_mac = (q81_tx_mac_t *)&ha->tx_ring[txr_idx].wq_vaddr[txr_next]; tx_mac = (q81_tx_mac_t *)&ha->tx_ring[txr_idx].wq_vaddr[txr_next];
bzero(tx_mac, sizeof(q81_tx_mac_t)); bzero(tx_mac, sizeof(q81_tx_mac_t));
if ((mp->m_pkthdr.csum_flags & if ((mp->m_pkthdr.csum_flags &
(CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO)) != 0) { (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO)) != 0) {
ret = qls_tx_tso_chksum(ha, mp, (q81_tx_tso_t *)tx_mac); ret = qls_tx_tso_chksum(ha, mp, (q81_tx_tso_t *)tx_mac);
if (ret) if (ret)
return (EINVAL); return (EINVAL);
@ -720,7 +710,6 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
} }
if (mp->m_flags & M_VLANTAG) { if (mp->m_flags & M_VLANTAG) {
tx_mac->vlan_tci = mp->m_pkthdr.ether_vtag; tx_mac->vlan_tci = mp->m_pkthdr.ether_vtag;
tx_mac->vlan_off |= Q81_TX_MAC_VLAN_OFF_V; tx_mac->vlan_off |= Q81_TX_MAC_VLAN_OFF_V;
@ -732,7 +721,6 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
tx_mac->tid_lo = txr_next; tx_mac->tid_lo = txr_next;
if (nsegs <= MAX_TX_MAC_DESC) { if (nsegs <= MAX_TX_MAC_DESC) {
QL_DPRINT2((dev, "%s: 1 [%d, %d]\n", __func__, total_length, QL_DPRINT2((dev, "%s: 1 [%d, %d]\n", __func__, total_length,
tx_mac->tid_lo)); tx_mac->tid_lo));
@ -832,7 +820,6 @@ qls_init_hw_if(qla_host_t *ha)
int ret = 0; int ret = 0;
int i; int i;
QL_DPRINT2((ha->pci_dev, "%s:enter\n", __func__)); QL_DPRINT2((ha->pci_dev, "%s:enter\n", __func__));
dev = ha->pci_dev; dev = ha->pci_dev;
@ -871,7 +858,7 @@ qls_init_hw_if(qla_host_t *ha)
/* Interrupt Mask Register */ /* Interrupt Mask Register */
value = Q81_CTL_INTRM_PI; value = Q81_CTL_INTRM_PI;
value = (value << Q81_CTL_INTRM_MASK_SHIFT) | value; value = (value << Q81_CTL_INTRM_MASK_SHIFT) | value;
WRITE_REG32(ha, Q81_CTL_INTR_MASK, value); WRITE_REG32(ha, Q81_CTL_INTR_MASK, value);
/* Initialiatize Completion Queue */ /* Initialiatize Completion Queue */
@ -945,7 +932,6 @@ qls_init_hw_if(qla_host_t *ha)
ha->tx_ring[0].wq_db_offset)); ha->tx_ring[0].wq_db_offset));
for (i = 0; i < ha->num_rx_rings; i++) { for (i = 0; i < ha->num_rx_rings; i++) {
Q81_WR_CQ_CONS_IDX(i, 0); Q81_WR_CQ_CONS_IDX(i, 0);
Q81_WR_LBQ_PROD_IDX(i, ha->rx_ring[i].lbq_in); Q81_WR_LBQ_PROD_IDX(i, ha->rx_ring[i].lbq_in);
Q81_WR_SBQ_PROD_IDX(i, ha->rx_ring[i].sbq_in); Q81_WR_SBQ_PROD_IDX(i, ha->rx_ring[i].sbq_in);
@ -972,7 +958,6 @@ qls_wait_for_config_reg_bits(qla_host_t *ha, uint32_t bits, uint32_t value)
uint32_t count = 3; uint32_t count = 3;
while (count--) { while (count--) {
data32 = READ_REG32(ha, Q81_CTL_CONFIG); data32 = READ_REG32(ha, Q81_CTL_CONFIG);
if ((data32 & bits) == value) if ((data32 & bits) == value)
@ -1076,7 +1061,7 @@ qls_init_comp_queue(qla_host_t *ha, int cid)
Q81_CQ_ICB_FLAGS_LL | Q81_CQ_ICB_FLAGS_LL |
Q81_CQ_ICB_FLAGS_LS | Q81_CQ_ICB_FLAGS_LS |
Q81_CQ_ICB_FLAGS_LV; Q81_CQ_ICB_FLAGS_LV;
cq_icb->length_v = NUM_CQ_ENTRIES; cq_icb->length_v = NUM_CQ_ENTRIES;
cq_icb->cq_baddr_lo = (rxr->cq_base_paddr & 0xFFFFFFFF); cq_icb->cq_baddr_lo = (rxr->cq_base_paddr & 0xFFFFFFFF);
@ -1221,7 +1206,6 @@ qls_hw_add_all_mcast(qla_host_t *ha)
(ha->mcast[i].addr[3] != 0) || (ha->mcast[i].addr[3] != 0) ||
(ha->mcast[i].addr[4] != 0) || (ha->mcast[i].addr[4] != 0) ||
(ha->mcast[i].addr[5] != 0)) { (ha->mcast[i].addr[5] != 0)) {
if (qls_config_mcast_mac_addr(ha, ha->mcast[i].addr, if (qls_config_mcast_mac_addr(ha, ha->mcast[i].addr,
1, i)) { 1, i)) {
device_printf(ha->pci_dev, "%s: failed\n", device_printf(ha->pci_dev, "%s: failed\n",
@ -1241,20 +1225,17 @@ qls_hw_add_mcast(qla_host_t *ha, uint8_t *mta)
int i; int i;
for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0)
return 0; /* its been already added */ return 0; /* its been already added */
} }
for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
if ((ha->mcast[i].addr[0] == 0) && if ((ha->mcast[i].addr[0] == 0) &&
(ha->mcast[i].addr[1] == 0) && (ha->mcast[i].addr[1] == 0) &&
(ha->mcast[i].addr[2] == 0) && (ha->mcast[i].addr[2] == 0) &&
(ha->mcast[i].addr[3] == 0) && (ha->mcast[i].addr[3] == 0) &&
(ha->mcast[i].addr[4] == 0) && (ha->mcast[i].addr[4] == 0) &&
(ha->mcast[i].addr[5] == 0)) { (ha->mcast[i].addr[5] == 0)) {
if (qls_config_mcast_mac_addr(ha, mta, 1, i)) if (qls_config_mcast_mac_addr(ha, mta, 1, i))
return (-1); return (-1);
@ -1274,7 +1255,6 @@ qls_hw_del_mcast(qla_host_t *ha, uint8_t *mta)
for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) { if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) {
if (qls_config_mcast_mac_addr(ha, mta, 0, i)) if (qls_config_mcast_mac_addr(ha, mta, 0, i))
return (-1); return (-1);
@ -1338,8 +1318,6 @@ qls_update_link_state(qla_host_t *ha)
ha->link_up = ((link_state & Q81_CTL_STATUS_PL1)? 1 : 0); ha->link_up = ((link_state & Q81_CTL_STATUS_PL1)? 1 : 0);
if (prev_link_state != ha->link_up) { if (prev_link_state != ha->link_up) {
if (ha->link_up) { if (ha->link_up) {
if_link_state_change(ha->ifp, LINK_STATE_UP); if_link_state_change(ha->ifp, LINK_STATE_UP);
} else { } else {
@ -1371,11 +1349,9 @@ qls_free_tx_dma(qla_host_t *ha)
qla_tx_buf_t *txb; qla_tx_buf_t *txb;
for (i = 0; i < ha->num_tx_rings; i++) { for (i = 0; i < ha->num_tx_rings; i++) {
qls_free_tx_ring_dma(ha, i); qls_free_tx_ring_dma(ha, i);
for (j = 0; j < NUM_TX_DESCRIPTORS; j++) { for (j = 0; j < NUM_TX_DESCRIPTORS; j++) {
txb = &ha->tx_ring[i].tx_buf[j]; txb = &ha->tx_ring[i].tx_buf[j];
if (txb->map) { if (txb->map) {
@ -1444,7 +1420,6 @@ qls_alloc_tx_ring_dma(qla_host_t *ha, int ridx)
txb = ha->tx_ring[ridx].tx_buf; txb = ha->tx_ring[ridx].tx_buf;
for (i = 0; i < NUM_TX_DESCRIPTORS; i++) { for (i = 0; i < NUM_TX_DESCRIPTORS; i++) {
txb[i].oal_vaddr = v_addr; txb[i].oal_vaddr = v_addr;
txb[i].oal_paddr = p_addr; txb[i].oal_paddr = p_addr;
@ -1481,7 +1456,6 @@ qls_alloc_tx_dma(qla_host_t *ha)
} }
for (i = 0; i < ha->num_tx_rings; i++) { for (i = 0; i < ha->num_tx_rings; i++) {
ret = qls_alloc_tx_ring_dma(ha, i); ret = qls_alloc_tx_ring_dma(ha, i);
if (ret) { if (ret) {
@ -1490,7 +1464,6 @@ qls_alloc_tx_dma(qla_host_t *ha)
} }
for (j = 0; j < NUM_TX_DESCRIPTORS; j++) { for (j = 0; j < NUM_TX_DESCRIPTORS; j++) {
txb = &ha->tx_ring[i].tx_buf[j]; txb = &ha->tx_ring[i].tx_buf[j];
ret = bus_dmamap_create(ha->tx_tag, ret = bus_dmamap_create(ha->tx_tag,
@ -1691,7 +1664,7 @@ qls_alloc_rx_ring_dma(qla_host_t *ha, int ridx)
/* large buffer queue */ /* large buffer queue */
ha->rx_ring[ridx].lbq_vaddr = v_addr + PAGE_SIZE; ha->rx_ring[ridx].lbq_vaddr = v_addr + PAGE_SIZE;
ha->rx_ring[ridx].lbq_paddr = p_addr + PAGE_SIZE; ha->rx_ring[ridx].lbq_paddr = p_addr + PAGE_SIZE;
v_addr = ha->rx_ring[ridx].sbq_dma.dma_b; v_addr = ha->rx_ring[ridx].sbq_dma.dma_b;
p_addr = ha->rx_ring[ridx].sbq_dma.dma_addr; p_addr = ha->rx_ring[ridx].sbq_dma.dma_addr;
@ -1760,7 +1733,6 @@ qls_alloc_rx_dma(qla_host_t *ha)
NULL, /* lockfunc */ NULL, /* lockfunc */
NULL, /* lockfuncarg */ NULL, /* lockfuncarg */
&ha->rx_tag)) { &ha->rx_tag)) {
device_printf(ha->pci_dev, "%s: rx_tag alloc failed\n", device_printf(ha->pci_dev, "%s: rx_tag alloc failed\n",
__func__); __func__);
@ -1786,7 +1758,6 @@ qls_wait_for_flash_ready(qla_host_t *ha)
uint32_t count = 3; uint32_t count = 3;
while (count--) { while (count--) {
data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR); data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR);
if (data32 & Q81_CTL_FLASH_ADDR_ERR) if (data32 & Q81_CTL_FLASH_ADDR_ERR)
@ -1878,7 +1849,6 @@ qls_rd_nic_params(qla_host_t *ha)
qflash = (uint32_t *)&ha->flash; qflash = (uint32_t *)&ha->flash;
for (i = 0; i < (sizeof(q81_flash_t) >> 2) ; i++) { for (i = 0; i < (sizeof(q81_flash_t) >> 2) ; i++) {
ret = qls_rd_flash32(ha, faddr, qflash); ret = qls_rd_flash32(ha, faddr, qflash);
if (ret) if (ret)
@ -1916,7 +1886,7 @@ qls_sem_lock(qla_host_t *ha, uint32_t mask, uint32_t value)
while (count--) { while (count--) {
WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value)); WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value));
data = READ_REG32(ha, Q81_CTL_SEMAPHORE); data = READ_REG32(ha, Q81_CTL_SEMAPHORE);
if (data & value) { if (data & value) {
@ -1942,7 +1912,6 @@ qls_wait_for_proc_addr_ready(qla_host_t *ha)
uint32_t count = 3; uint32_t count = 3;
while (count--) { while (count--) {
data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR); data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR);
if (data32 & Q81_CTL_PROC_ADDR_ERR) if (data32 & Q81_CTL_PROC_ADDR_ERR)
@ -1981,7 +1950,7 @@ qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_module, uint32_t reg,
if (ret) if (ret)
goto qls_proc_addr_rd_reg_exit; goto qls_proc_addr_rd_reg_exit;
*data = READ_REG32(ha, Q81_CTL_PROC_DATA); *data = READ_REG32(ha, Q81_CTL_PROC_DATA);
qls_proc_addr_rd_reg_exit: qls_proc_addr_rd_reg_exit:
@ -2018,7 +1987,7 @@ qls_hw_nic_reset(qla_host_t *ha)
int count; int count;
uint32_t data; uint32_t data;
device_t dev = ha->pci_dev; device_t dev = ha->pci_dev;
ha->hw_init = 0; ha->hw_init = 0;
data = (Q81_CTL_RESET_FUNC << Q81_CTL_RESET_MASK_SHIFT) | data = (Q81_CTL_RESET_FUNC << Q81_CTL_RESET_MASK_SHIFT) |
@ -2039,7 +2008,7 @@ qls_hw_nic_reset(qla_host_t *ha)
} }
return (0); return (0);
} }
static int static int
qls_hw_reset(qla_host_t *ha) qls_hw_reset(qla_host_t *ha)
{ {
@ -2096,7 +2065,7 @@ qls_hw_reset(qla_host_t *ha)
ret = qls_hw_nic_reset(ha); ret = qls_hw_nic_reset(ha);
if (ret) if (ret)
goto qls_hw_reset_exit; goto qls_hw_reset_exit;
ret = qls_mbx_set_mgmt_ctrl(ha, Q81_MBX_SET_MGMT_CTL_RESUME); ret = qls_mbx_set_mgmt_ctrl(ha, Q81_MBX_SET_MGMT_CTL_RESUME);
qls_hw_reset_exit: qls_hw_reset_exit:
@ -2159,7 +2128,6 @@ qls_mbx_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data)
return (ret); return (ret);
} }
static int static int
qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count, qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count,
uint32_t *out_mbx, uint32_t o_count) uint32_t *out_mbx, uint32_t o_count)
@ -2190,7 +2158,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count,
mbx_cmd = *in_mbx; mbx_cmd = *in_mbx;
for (i = 0; i < i_count; i++) { for (i = 0; i < i_count; i++) {
ret = qls_mbx_wr_reg(ha, i, *in_mbx); ret = qls_mbx_wr_reg(ha, i, *in_mbx);
if (ret) { if (ret) {
@ -2211,7 +2178,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count,
ha->mbx_done = 0; ha->mbx_done = 0;
while (count--) { while (count--) {
if (ha->flags.intr_enable == 0) { if (ha->flags.intr_enable == 0) {
data32 = READ_REG32(ha, Q81_CTL_STATUS); data32 = READ_REG32(ha, Q81_CTL_STATUS);
@ -2224,7 +2190,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count,
if (ret == 0 ) { if (ret == 0 ) {
if ((data32 & 0xF000) == 0x4000) { if ((data32 & 0xF000) == 0x4000) {
out_mbx[0] = data32; out_mbx[0] = data32;
for (i = 1; i < o_count; i++) { for (i = 1; i < o_count; i++) {
@ -2422,7 +2387,7 @@ qls_mpi_reset(qla_host_t *ha)
int count; int count;
uint32_t data; uint32_t data;
device_t dev = ha->pci_dev; device_t dev = ha->pci_dev;
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\ WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
Q81_CTL_HCS_CMD_SET_RISC_RESET); Q81_CTL_HCS_CMD_SET_RISC_RESET);
@ -2442,4 +2407,3 @@ qls_mpi_reset(qla_host_t *ha)
} }
return (0); return (0);
} }

30
sys/dev/qlxge/qls_hw.h
View File

@ -86,7 +86,6 @@
#define BIT_30 (0x1 << 30) #define BIT_30 (0x1 << 30)
#define BIT_31 (0x1 << 31) #define BIT_31 (0x1 << 31)
/* /*
* Firmware Interface * Firmware Interface
*/ */
@ -169,7 +168,6 @@
#define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ #define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */
#define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ #define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */
/* /*
* Process Address Register (0x00) * Process Address Register (0x00)
*/ */
@ -181,7 +179,6 @@
#define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) #define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16)
#define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) #define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16)
/* /*
* System Register (0x08) * System Register (0x08)
*/ */
@ -228,7 +225,6 @@
#define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 #define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02
#define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03
/* /*
* Host Command/Status Register (0x14) * Host Command/Status Register (0x14)
*/ */
@ -250,7 +246,6 @@
#define Q81_CTL_HCS_RISC_RESET BIT_8 #define Q81_CTL_HCS_RISC_RESET BIT_8
#define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F #define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F
/* /*
* Configuration Register (0x28) * Configuration Register (0x28)
*/ */
@ -265,7 +260,6 @@
#define Q81_CTL_CONFIG_DRQ BIT_1 #define Q81_CTL_CONFIG_DRQ BIT_1
#define Q81_CTL_CONFIG_LRQ BIT_0 #define Q81_CTL_CONFIG_LRQ BIT_0
/* /*
* Status Register (0x30) * Status Register (0x30)
*/ */
@ -363,7 +357,6 @@
#define Q81_CTL_SEM_SET_XGMAC1 0x0004 #define Q81_CTL_SEM_SET_XGMAC1 0x0004
#define Q81_CTL_SEM_SET_XGMAC0 0x0001 #define Q81_CTL_SEM_SET_XGMAC0 0x0001
/* /*
* Flash Address Register (0x88) * Flash Address Register (0x88)
*/ */
@ -439,7 +432,6 @@
#define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) #define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1)
#define Q81_CTL_NIC_RCVC_PPE BIT_0 #define Q81_CTL_NIC_RCVC_PPE BIT_0
/* /*
* Routing Index Register (0xE4) * Routing Index Register (0xE4)
*/ */
@ -505,7 +497,6 @@
#define Q81_CTL_RD_RSS_IPV4 BIT_30 #define Q81_CTL_RD_RSS_IPV4 BIT_30
#define Q81_CTL_RD_RSS_MATCH BIT_31 #define Q81_CTL_RD_RSS_MATCH BIT_31
/********************************************************************* /*********************************************************************
* Host Data Structures * * Host Data Structures *
*********************************************************************/ *********************************************************************/
@ -515,7 +506,6 @@
*/ */
typedef struct _q81_wq_icb { typedef struct _q81_wq_icb {
uint16_t length_v; uint16_t length_v;
#define Q81_WQ_ICB_VALID BIT_4 #define Q81_WQ_ICB_VALID BIT_4
@ -540,7 +530,6 @@ typedef struct _q81_wq_icb {
uint32_t ci_addr_hi; uint32_t ci_addr_hi;
} __packed q81_wq_icb_t; } __packed q81_wq_icb_t;
/* /*
* Completion Queue Initialization Control Block * Completion Queue Initialization Control Block
*/ */
@ -606,8 +595,6 @@ typedef struct _q81_rss_icb {
uint32_t ipv4_rss_hash_key[4]; uint32_t ipv4_rss_hash_key[4];
} __packed q81_rss_icb_t; } __packed q81_rss_icb_t;
/* /*
* Transmit Buffer Descriptor * Transmit Buffer Descriptor
*/ */
@ -622,7 +609,6 @@ typedef struct _q81_txb_desc {
} __packed q81_txb_desc_t; } __packed q81_txb_desc_t;
/* /*
* Receive Buffer Descriptor * Receive Buffer Descriptor
*/ */
@ -651,7 +637,6 @@ typedef struct _q81_rxb_desc {
#define Q81_IOCB_MPI 0x21 #define Q81_IOCB_MPI 0x21
#define Q81_IOCB_SYS 0x3F #define Q81_IOCB_SYS 0x3F
/* /*
* IOCB Definitions * IOCB Definitions
*/ */
@ -663,7 +648,6 @@ typedef struct _q81_rxb_desc {
#define MAX_TX_MAC_DESC 8 #define MAX_TX_MAC_DESC 8
typedef struct _q81_tx_mac { typedef struct _q81_tx_mac {
uint8_t opcode; uint8_t opcode;
uint16_t flags; uint16_t flags;
@ -692,8 +676,7 @@ typedef struct _q81_tx_mac {
q81_txb_desc_t txd[MAX_TX_MAC_DESC]; q81_txb_desc_t txd[MAX_TX_MAC_DESC];
} __packed q81_tx_mac_t; } __packed q81_tx_mac_t;
/* /*
* MAC Tx Frame with TSO IOCB * MAC Tx Frame with TSO IOCB
* Total Size of each IOCB Entry = 4 * 32 = 128 bytes * Total Size of each IOCB Entry = 4 * 32 = 128 bytes
@ -734,7 +717,7 @@ typedef struct _q81_tx_tso {
q81_txb_desc_t txd[MAX_TX_MAC_DESC]; q81_txb_desc_t txd[MAX_TX_MAC_DESC];
} __packed q81_tx_tso_t; } __packed q81_tx_tso_t;
typedef struct _q81_tx_cmd { typedef struct _q81_tx_cmd {
uint8_t bytes[128]; uint8_t bytes[128];
} __packed q81_tx_cmd_t; } __packed q81_tx_cmd_t;
@ -766,7 +749,6 @@ typedef struct _q81_tx_mac_comp {
uint32_t rsrvd1[13]; uint32_t rsrvd1[13];
} __packed q81_tx_mac_comp_t; } __packed q81_tx_mac_comp_t;
/* /*
* MAC TX Frame with LSO Completion * MAC TX Frame with LSO Completion
* Total Size of each IOCB Entry = 4 * 16 = 64 bytes * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
@ -793,7 +775,6 @@ typedef struct _q81_tx_tso_comp {
uint32_t rsrvd1[13]; uint32_t rsrvd1[13];
} __packed q81_tx_tso_comp_t; } __packed q81_tx_tso_comp_t;
/* /*
* SYS - Chip Event Notification Completion * SYS - Chip Event Notification Completion
* Total Size of each IOCB Entry = 4 * 16 = 64 bytes * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
@ -823,8 +804,6 @@ typedef struct _q81_sys_comp {
uint32_t rsrvd1[15]; uint32_t rsrvd1[15];
} __packed q81_sys_comp_t; } __packed q81_sys_comp_t;
/* /*
* Mac Rx Packet Completion * Mac Rx Packet Completion
* Total Size of each IOCB Entry = 4 * 16 = 64 bytes * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
@ -904,7 +883,6 @@ typedef struct _q81_bq_addr_e {
uint32_t addr_hi; uint32_t addr_hi;
} __packed q81_bq_addr_e_t; } __packed q81_bq_addr_e_t;
/* /*
* Macros for reading and writing registers * Macros for reading and writing registers
*/ */
@ -946,7 +924,6 @@ typedef struct _q81_bq_addr_e {
#define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ #define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\
(ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG))
#define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ #define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\
(ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\
Q81_COMPQ_VALID_V) Q81_COMPQ_VALID_V)
@ -981,7 +958,6 @@ typedef struct _q81_bq_addr_e {
#define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ #define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\
(ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG))
/* /*
* Flash Related * Flash Related
*/ */
@ -991,7 +967,6 @@ typedef struct _q81_bq_addr_e {
#define Q81_FLASH_ID "8000" #define Q81_FLASH_ID "8000"
typedef struct _q81_flash { typedef struct _q81_flash {
uint8_t id[4]; /* equal to "8000" */ uint8_t id[4]; /* equal to "8000" */
uint16_t version; uint16_t version;
@ -1025,7 +1000,6 @@ typedef struct _q81_flash {
uint8_t rsrvd2[4]; uint8_t rsrvd2[4];
} __packed q81_flash_t; } __packed q81_flash_t;
/* /*
* MPI Related * MPI Related
*/ */

4
sys/dev/qlxge/qls_ioctl.c
View File

@ -33,7 +33,6 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "qls_os.h" #include "qls_os.h"
#include "qls_hw.h" #include "qls_hw.h"
#include "qls_def.h" #include "qls_def.h"
@ -95,7 +94,6 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
pci_dev= ha->pci_dev; pci_dev= ha->pci_dev;
switch(cmd) { switch(cmd) {
case QLA_MPI_DUMP: case QLA_MPI_DUMP:
mpi_dump = (qls_mpi_dump_t *)data; mpi_dump = (qls_mpi_dump_t *)data;
@ -119,7 +117,6 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
__func__, rval); __func__, rval);
} }
} }
} }
break; break;
@ -129,4 +126,3 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
return rval; return rval;
} }

1
sys/dev/qlxge/qls_ioctl.h
View File

@ -49,5 +49,4 @@ typedef struct qls_mpi_dump qls_mpi_dump_t;
*/ */
#define QLA_MPI_DUMP _IOWR('q', 1, qls_mpi_dump_t) #define QLA_MPI_DUMP _IOWR('q', 1, qls_mpi_dump_t)
#endif /* #ifndef _QLS_IOCTL_H_ */ #endif /* #ifndef _QLS_IOCTL_H_ */

18
sys/dev/qlxge/qls_isr.c
View File

@ -36,8 +36,6 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "qls_os.h" #include "qls_os.h"
#include "qls_hw.h" #include "qls_hw.h"
#include "qls_def.h" #include "qls_def.h"
@ -46,7 +44,6 @@ __FBSDID("$FreeBSD$");
#include "qls_glbl.h" #include "qls_glbl.h"
#include "qls_dbg.h" #include "qls_dbg.h"
static void static void
qls_tx_comp(qla_host_t *ha, uint32_t txr_idx, q81_tx_mac_comp_t *tx_comp) qls_tx_comp(qla_host_t *ha, uint32_t txr_idx, q81_tx_mac_comp_t *tx_comp)
{ {
@ -90,7 +87,6 @@ qls_replenish_rx(qla_host_t *ha, uint32_t r_idx)
sbq_e = rxr->sbq_vaddr; sbq_e = rxr->sbq_vaddr;
while (count--) { while (count--) {
rxb = &rxr->rx_buf[rxr->sbq_next]; rxb = &rxr->rx_buf[rxr->sbq_next];
if (rxb->m_head == NULL) { if (rxb->m_head == NULL) {
@ -117,7 +113,6 @@ qls_replenish_rx(qla_host_t *ha, uint32_t r_idx)
} }
if (rxr->sbq_free == 16) { if (rxr->sbq_free == 16) {
rxr->sbq_in += 16; rxr->sbq_in += 16;
rxr->sbq_in = rxr->sbq_in & (NUM_RX_DESCRIPTORS - 1); rxr->sbq_in = rxr->sbq_in & (NUM_RX_DESCRIPTORS - 1);
rxr->sbq_free = 0; rxr->sbq_free = 0;
@ -149,7 +144,6 @@ qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t cq_idx, q81_rx_t *cq_e)
return -1; return -1;
} }
if (rxb->paddr != cq_e->b_paddr) { if (rxb->paddr != cq_e->b_paddr) {
device_printf(dev, device_printf(dev,
"%s: (rxb->paddr != cq_e->b_paddr)[%p, %p] \n", "%s: (rxb->paddr != cq_e->b_paddr)[%p, %p] \n",
__func__, (void *)rxb->paddr, (void *)cq_e->b_paddr); __func__, (void *)rxb->paddr, (void *)cq_e->b_paddr);
@ -164,7 +158,6 @@ qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t cq_idx, q81_rx_t *cq_e)
rxr->rx_int++; rxr->rx_int++;
if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) { if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) {
mp = rxb->m_head; mp = rxb->m_head;
rxb->m_head = NULL; rxb->m_head = NULL;
@ -245,11 +238,9 @@ qls_cq_isr(qla_host_t *ha, uint32_t cq_idx)
i = ha->rx_ring[cq_idx].cq_next; i = ha->rx_ring[cq_idx].cq_next;
while (i != cq_comp_idx) { while (i != cq_comp_idx) {
cq_e = &cq_b[i]; cq_e = &cq_b[i];
switch (cq_e->opcode) { switch (cq_e->opcode) {
case Q81_IOCB_TX_MAC: case Q81_IOCB_TX_MAC:
case Q81_IOCB_TX_TSO: case Q81_IOCB_TX_TSO:
qls_tx_comp(ha, cq_idx, (q81_tx_mac_comp_t *)cq_e); qls_tx_comp(ha, cq_idx, (q81_tx_mac_comp_t *)cq_e);
@ -258,7 +249,7 @@ qls_cq_isr(qla_host_t *ha, uint32_t cq_idx)
case Q81_IOCB_RX: case Q81_IOCB_RX:
ret = qls_rx_comp(ha, cq_idx, i, (q81_rx_t *)cq_e); ret = qls_rx_comp(ha, cq_idx, i, (q81_rx_t *)cq_e);
break; break;
case Q81_IOCB_MPI: case Q81_IOCB_MPI:
@ -311,7 +302,6 @@ qls_mbx_isr(qla_host_t *ha)
device_t dev = ha->pci_dev; device_t dev = ha->pci_dev;
if (qls_mbx_rd_reg(ha, 0, &data) == 0) { if (qls_mbx_rd_reg(ha, 0, &data) == 0) {
if ((data & 0xF000) == 0x4000) { if ((data & 0xF000) == 0x4000) {
ha->mbox[0] = data; ha->mbox[0] = data;
for (i = 1; i < Q81_NUM_MBX_REGISTERS; i++) { for (i = 1; i < Q81_NUM_MBX_REGISTERS; i++) {
@ -321,9 +311,8 @@ qls_mbx_isr(qla_host_t *ha)
} }
ha->mbx_done = 1; ha->mbx_done = 1;
} else if ((data & 0xF000) == 0x8000) { } else if ((data & 0xF000) == 0x8000) {
/* we have an AEN */ /* we have an AEN */
ha->aen[0] = data; ha->aen[0] = data;
for (i = 1; i < Q81_NUM_AEN_REGISTERS; i++) { for (i = 1; i < Q81_NUM_AEN_REGISTERS; i++) {
if (qls_mbx_rd_reg(ha, i, &data)) if (qls_mbx_rd_reg(ha, i, &data))
@ -339,7 +328,6 @@ qls_mbx_isr(qla_host_t *ha)
ha->aen[6], ha->aen[7], ha->aen[8]); ha->aen[6], ha->aen[7], ha->aen[8]);
switch ((ha->aen[0] & 0xFFFF)) { switch ((ha->aen[0] & 0xFFFF)) {
case 0x8011: case 0x8011:
ha->link_up = 1; ha->link_up = 1;
break; break;
@ -355,7 +343,6 @@ qls_mbx_isr(qla_host_t *ha)
case 0x8131: case 0x8131:
ha->link_hw_info = 0; ha->link_hw_info = 0;
break; break;
} }
} }
} }
@ -397,4 +384,3 @@ qls_isr(void *arg)
return; return;
} }

32
sys/dev/qlxge/qls_os.c
View File

@ -35,7 +35,6 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "qls_os.h" #include "qls_os.h"
#include "qls_hw.h" #include "qls_hw.h"
#include "qls_def.h" #include "qls_def.h"
@ -162,11 +161,9 @@ qls_sysctl_get_drvr_stats(SYSCTL_HANDLER_ARGS)
return (err); return (err);
if (ret == 1) { if (ret == 1) {
ha = (qla_host_t *)arg1; ha = (qla_host_t *)arg1;
for (i = 0; i < ha->num_tx_rings; i++) { for (i = 0; i < ha->num_tx_rings; i++) {
device_printf(ha->pci_dev, device_printf(ha->pci_dev,
"%s: tx_ring[%d].tx_frames= %p\n", "%s: tx_ring[%d].tx_frames= %p\n",
__func__, i, __func__, i,
@ -204,7 +201,6 @@ qls_sysctl_get_drvr_stats(SYSCTL_HANDLER_ARGS)
} }
for (i = 0; i < ha->num_rx_rings; i++) { for (i = 0; i < ha->num_rx_rings; i++) {
device_printf(ha->pci_dev, device_printf(ha->pci_dev,
"%s: rx_ring[%d].rx_int= %p\n", "%s: rx_ring[%d].rx_int= %p\n",
__func__, i, __func__, i,
@ -303,16 +299,13 @@ qls_watchdog(void *arg)
ha->qla_watchdog_exited = 0; ha->qla_watchdog_exited = 0;
if (!ha->flags.qla_watchdog_pause) { if (!ha->flags.qla_watchdog_pause) {
if (ha->qla_initiate_recovery) { if (ha->qla_initiate_recovery) {
ha->qla_watchdog_paused = 1; ha->qla_watchdog_paused = 1;
ha->qla_initiate_recovery = 0; ha->qla_initiate_recovery = 0;
ha->err_inject = 0; ha->err_inject = 0;
taskqueue_enqueue(ha->err_tq, &ha->err_task); taskqueue_enqueue(ha->err_tq, &ha->err_task);
} else if ((ifp->if_snd.ifq_head != NULL) && QL_RUNNING(ifp)) { } else if ((ifp->if_snd.ifq_head != NULL) && QL_RUNNING(ifp)) {
taskqueue_enqueue(ha->tx_tq, &ha->tx_task); taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
} }
@ -454,7 +447,7 @@ qls_pci_attach(device_t dev)
taskqueue_thread_enqueue, &ha->tx_tq); taskqueue_thread_enqueue, &ha->tx_tq);
taskqueue_start_threads(&ha->tx_tq, 1, PI_NET, "%s txq", taskqueue_start_threads(&ha->tx_tq, 1, PI_NET, "%s txq",
device_get_nameunit(ha->pci_dev)); device_get_nameunit(ha->pci_dev));
callout_init(&ha->tx_callout, 1); callout_init(&ha->tx_callout, 1);
ha->flags.qla_callout_init = 1; ha->flags.qla_callout_init = 1;
@ -555,7 +548,6 @@ qls_release(qla_host_t *ha)
qls_free_parent_dma_tag(ha); qls_free_parent_dma_tag(ha);
for (i = 0; i < ha->num_rx_rings; i++) { for (i = 0; i < ha->num_rx_rings; i++) {
if (ha->irq_vec[i].handle) { if (ha->irq_vec[i].handle) {
(void)bus_teardown_intr(dev, ha->irq_vec[i].irq, (void)bus_teardown_intr(dev, ha->irq_vec[i].irq,
ha->irq_vec[i].handle); ha->irq_vec[i].handle);
@ -708,7 +700,7 @@ qls_alloc_parent_dma_tag(qla_host_t *ha)
} }
ha->flags.parent_tag = 1; ha->flags.parent_tag = 1;
return (0); return (0);
} }
@ -1039,7 +1031,7 @@ qls_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
ifmr->ifm_status = IFM_AVALID; ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER; ifmr->ifm_active = IFM_ETHER;
qls_update_link_state(ha); qls_update_link_state(ha);
if (ha->link_up) { if (ha->link_up) {
ifmr->ifm_status |= IFM_ACTIVE; ifmr->ifm_status |= IFM_ACTIVE;
@ -1069,7 +1061,6 @@ qls_start(struct ifnet *ifp)
if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) ==
IFF_DRV_RUNNING) { IFF_DRV_RUNNING) {
for (i = 0; i < ha->num_tx_rings; i++) { for (i = 0; i < ha->num_tx_rings; i++) {
ret |= qls_hw_tx_done(ha, i); ret |= qls_hw_tx_done(ha, i);
} }
@ -1095,7 +1086,6 @@ qls_start(struct ifnet *ifp)
} }
while (ifp->if_snd.ifq_head != NULL) { while (ifp->if_snd.ifq_head != NULL) {
IF_DEQUEUE(&ifp->if_snd, m_head); IF_DEQUEUE(&ifp->if_snd, m_head);
if (m_head == NULL) { if (m_head == NULL) {
@ -1146,7 +1136,6 @@ qls_send(qla_host_t *ha, struct mbuf **m_headp)
BUS_DMA_NOWAIT); BUS_DMA_NOWAIT);
if (ret == EFBIG) { if (ret == EFBIG) {
struct mbuf *m; struct mbuf *m;
QL_DPRINT8((ha->pci_dev, "%s: EFBIG [%d]\n", __func__, QL_DPRINT8((ha->pci_dev, "%s: EFBIG [%d]\n", __func__,
@ -1167,7 +1156,6 @@ qls_send(qla_host_t *ha, struct mbuf **m_headp)
if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head,
segs, &nsegs, BUS_DMA_NOWAIT))) { segs, &nsegs, BUS_DMA_NOWAIT))) {
ha->err_tx_dmamap_load++; ha->err_tx_dmamap_load++;
device_printf(ha->pci_dev, device_printf(ha->pci_dev,
@ -1182,7 +1170,6 @@ qls_send(qla_host_t *ha, struct mbuf **m_headp)
} }
} else if (ret) { } else if (ret) {
ha->err_tx_dmamap_load++; ha->err_tx_dmamap_load++;
device_printf(ha->pci_dev, device_printf(ha->pci_dev,
@ -1201,7 +1188,6 @@ qls_send(qla_host_t *ha, struct mbuf **m_headp)
bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE);
if (!(ret = qls_hw_send(ha, segs, nsegs, tx_idx, m_head, txr_idx))) { if (!(ret = qls_hw_send(ha, segs, nsegs, tx_idx, m_head, txr_idx))) {
ha->tx_ring[txr_idx].count++; ha->tx_ring[txr_idx].count++;
ha->tx_ring[txr_idx].tx_buf[tx_idx].m_head = m_head; ha->tx_ring[txr_idx].tx_buf[tx_idx].m_head = m_head;
ha->tx_ring[txr_idx].tx_buf[tx_idx].map = map; ha->tx_ring[txr_idx].tx_buf[tx_idx].map = map;
@ -1254,7 +1240,6 @@ qls_flush_tx_buf(qla_host_t *ha, qla_tx_buf_t *txb)
QL_DPRINT2((ha->pci_dev, "%s: enter\n", __func__)); QL_DPRINT2((ha->pci_dev, "%s: enter\n", __func__));
if (txb->m_head) { if (txb->m_head) {
bus_dmamap_unload(ha->tx_tag, txb->map); bus_dmamap_unload(ha->tx_tag, txb->map);
m_freem(txb->m_head); m_freem(txb->m_head);
@ -1277,7 +1262,6 @@ qls_flush_xmt_bufs(qla_host_t *ha)
return; return;
} }
static int static int
qls_alloc_rcv_mbufs(qla_host_t *ha, int r) qls_alloc_rcv_mbufs(qla_host_t *ha, int r)
{ {
@ -1286,11 +1270,9 @@ qls_alloc_rcv_mbufs(qla_host_t *ha, int r)
qla_rx_ring_t *rx_ring; qla_rx_ring_t *rx_ring;
volatile q81_bq_addr_e_t *sbq_e; volatile q81_bq_addr_e_t *sbq_e;
rx_ring = &ha->rx_ring[r]; rx_ring = &ha->rx_ring[r];
for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { for (i = 0; i < NUM_RX_DESCRIPTORS; i++) {
rxb = &rx_ring->rx_buf[i]; rxb = &rx_ring->rx_buf[i];
ret = bus_dmamap_create(ha->rx_tag, BUS_DMA_NOWAIT, &rxb->map); ret = bus_dmamap_create(ha->rx_tag, BUS_DMA_NOWAIT, &rxb->map);
@ -1314,9 +1296,7 @@ qls_alloc_rcv_mbufs(qla_host_t *ha, int r)
rxb = &rx_ring->rx_buf[0]; rxb = &rx_ring->rx_buf[0];
for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { for (i = 0; i < NUM_RX_DESCRIPTORS; i++) {
if (!(ret = qls_get_mbuf(ha, rxb, NULL))) { if (!(ret = qls_get_mbuf(ha, rxb, NULL))) {
/* /*
* set the physical address in the * set the physical address in the
* corresponding descriptor entry in the * corresponding descriptor entry in the
@ -1351,11 +1331,9 @@ qls_free_rcv_bufs(qla_host_t *ha)
qla_rx_ring_t *rxr; qla_rx_ring_t *rxr;
for (r = 0; r < ha->num_rx_rings; r++) { for (r = 0; r < ha->num_rx_rings; r++) {
rxr = &ha->rx_ring[r]; rxr = &ha->rx_ring[r];
for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { for (i = 0; i < NUM_RX_DESCRIPTORS; i++) {
rxb = &rxr->rx_buf[i]; rxb = &rxr->rx_buf[i];
if (rxb->m_head != NULL) { if (rxb->m_head != NULL) {
@ -1381,7 +1359,6 @@ qls_alloc_rcv_bufs(qla_host_t *ha)
} }
for (r = 0; r < ha->num_rx_rings; r++) { for (r = 0; r < ha->num_rx_rings; r++) {
ret = qls_alloc_rcv_mbufs(ha, r); ret = qls_alloc_rcv_mbufs(ha, r);
if (ret) if (ret)
@ -1406,11 +1383,9 @@ qls_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp)
ifp = ha->ifp; ifp = ha->ifp;
if (mp == NULL) { if (mp == NULL) {
mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, ha->msize); mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, ha->msize);
if (mp == NULL) { if (mp == NULL) {
if (ha->msize == MCLBYTES) if (ha->msize == MCLBYTES)
ha->err_m_getcl++; ha->err_m_getcl++;
else else
@ -1527,4 +1502,3 @@ qls_error_recovery(void *context, int pending)
return; return;
} }

5
sys/dev/qlxge/qls_os.h
View File

@ -123,7 +123,6 @@ static __inline int qls_sec_to_hz(int sec)
return (tvtohz(&t)); return (tvtohz(&t));
} }
#define qla_host_to_le16(x) htole16(x) #define qla_host_to_le16(x) htole16(x)
#define qla_host_to_le32(x) htole32(x) #define qla_host_to_le32(x) htole32(x)
#define qla_host_to_le64(x) htole64(x) #define qla_host_to_le64(x) htole64(x)
@ -147,13 +146,13 @@ MALLOC_DECLARE(M_QLA8XXXBUF);
else \ else \
pause(fn, qls_ms_to_hz(msecs)); \ pause(fn, qls_ms_to_hz(msecs)); \
} }
/* /*
* Locks * Locks
*/ */
#define QLA_LOCK(ha, str, no_delay) qls_lock(ha, str, no_delay) #define QLA_LOCK(ha, str, no_delay) qls_lock(ha, str, no_delay)
#define QLA_UNLOCK(ha, str) qls_unlock(ha, str) #define QLA_UNLOCK(ha, str) qls_unlock(ha, str)
#define QLA_TX_LOCK(ha) mtx_lock(&ha->tx_lock); #define QLA_TX_LOCK(ha) mtx_lock(&ha->tx_lock);
#define QLA_TX_UNLOCK(ha) mtx_unlock(&ha->tx_lock); #define QLA_TX_UNLOCK(ha) mtx_unlock(&ha->tx_lock);