Add the 802.1q support for the Marvell e6000 series of ethernet switches.
Tested on: espressobin, Clearfog, SG-3100 and others Sponsored by: Rubicon Communications, LLC (Netgate)
This commit is contained in:
Luiz Otavio O Souza
parent
4e4cedb00b
commit
d7cecbd179
@ -1,6 +1,7 @@
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/*-
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* Copyright (c) 2015 Semihalf
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* Copyright (c) 2015 Stormshield
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* Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -60,6 +61,15 @@ MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch");
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#define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx)
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#define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what))
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#define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx)
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#define E6000SW_WAITREADY(_sc, _reg, _bit) \
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e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit))
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#define E6000SW_WAITREADY2(_sc, _reg, _bit) \
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e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit))
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#define MDIO_READ(dev, addr, reg) \
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MDIO_READREG(device_get_parent(dev), (addr), (reg))
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#define MDIO_WRITE(dev, addr, reg, val) \
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MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val))
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typedef struct e6000sw_softc {
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device_t dev;
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@ -71,6 +81,7 @@ typedef struct e6000sw_softc {
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device_t miibus[E6000SW_MAX_PORTS];
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struct proc *kproc;
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int vlans[E6000SW_NUM_VLANS];
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uint32_t swid;
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uint32_t vlan_mode;
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uint32_t cpuports_mask;
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@ -80,13 +91,12 @@ typedef struct e6000sw_softc {
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int phy_base;
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int sw_addr;
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int num_ports;
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boolean_t multi_chip;
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} e6000sw_softc_t;
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static etherswitch_info_t etherswitch_info = {
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.es_nports = 0,
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.es_nvlangroups = 0,
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.es_vlan_caps = ETHERSWITCH_VLAN_PORT,
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.es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q,
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.es_name = "Marvell 6000 series switch"
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};
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@ -100,10 +110,12 @@ static int e6000sw_readphy(device_t, int, int);
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static int e6000sw_writephy(device_t, int, int, int);
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static etherswitch_info_t* e6000sw_getinfo(device_t);
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static int e6000sw_getconf(device_t, etherswitch_conf_t *);
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static int e6000sw_setconf(device_t, etherswitch_conf_t *);
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static void e6000sw_lock(device_t);
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static void e6000sw_unlock(device_t);
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static int e6000sw_getport(device_t, etherswitch_port_t *);
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static int e6000sw_setport(device_t, etherswitch_port_t *);
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static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t);
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static int e6000sw_readreg_wrapper(device_t, int);
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static int e6000sw_writereg_wrapper(device_t, int, int);
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static int e6000sw_readphy_wrapper(device_t, int, int);
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@ -113,10 +125,11 @@ static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *);
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static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *);
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static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *);
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static void e6000sw_setup(device_t, e6000sw_softc_t *);
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static void e6000sw_port_vlan_conf(e6000sw_softc_t *);
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static void e6000sw_tick(void *);
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static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int);
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static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int);
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static int e6000sw_vtu_flush(e6000sw_softc_t *);
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static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int);
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static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int);
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static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int);
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static int e6000sw_ifmedia_upd(struct ifnet *);
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@ -124,7 +137,7 @@ static void e6000sw_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *,
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int);
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static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *);
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static int e6000sw_set_pvid(e6000sw_softc_t *, int, int);
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static void e6000sw_set_pvid(e6000sw_softc_t *, int, int);
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static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int);
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static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int);
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static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int);
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@ -150,6 +163,7 @@ static device_method_t e6000sw_methods[] = {
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/* etherswitch interface */
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DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo),
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DEVMETHOD(etherswitch_getconf, e6000sw_getconf),
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DEVMETHOD(etherswitch_setconf, e6000sw_setconf),
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DEVMETHOD(etherswitch_lock, e6000sw_lock),
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DEVMETHOD(etherswitch_unlock, e6000sw_unlock),
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DEVMETHOD(etherswitch_getport, e6000sw_getport),
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@ -175,16 +189,6 @@ DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, etherswitch_devclass, 0,
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DRIVER_MODULE(miibus, e6000sw, miibus_driver, miibus_devclass, 0, 0);
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MODULE_DEPEND(e6000sw, mdio, 1, 1, 1);
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#define SMI_CMD 0
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#define SMI_CMD_BUSY (1 << 15)
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#define SMI_CMD_OP_READ ((2 << 10) | SMI_CMD_BUSY | (1 << 12))
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#define SMI_CMD_OP_WRITE ((1 << 10) | SMI_CMD_BUSY | (1 << 12))
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#define SMI_DATA 1
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#define MDIO_READ(dev, addr, reg) \
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MDIO_READREG(device_get_parent(dev), (addr), (reg))
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#define MDIO_WRITE(dev, addr, reg, val) \
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MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val))
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static void
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e6000sw_identify(driver_t *driver, device_t parent)
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@ -217,14 +221,8 @@ e6000sw_probe(device_t dev)
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if (OF_getencprop(sc->node, "reg", &sc->sw_addr,
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sizeof(sc->sw_addr)) < 0)
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return (ENXIO);
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/*
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* According to the Linux source code, all of the Switch IDs we support
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* are multi_chip capable, and should go into multi-chip mode if the
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* sw_addr != 0.
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*/
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if (!OF_hasprop(sc->node, "single-chip-addressing") && sc->sw_addr != 0)
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sc->multi_chip = true;
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if (sc->sw_addr < 0 || sc->sw_addr > 32)
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return (ENXIO);
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/*
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* Create temporary lock, just to satisfy assertions,
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@ -396,8 +394,14 @@ e6000sw_attach(device_t dev)
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err = 0;
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sc = device_get_softc(dev);
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if (sc->multi_chip)
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device_printf(dev, "multi-chip addressing mode\n");
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/*
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* According to the Linux source code, all of the Switch IDs we support
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* are multi_chip capable, and should go into multi-chip mode if the
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* sw_addr != 0.
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*/
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if (MVSWITCH_MULTICHIP(sc))
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device_printf(dev, "multi-chip addressing mode (%#x)\n",
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sc->sw_addr);
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else
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device_printf(dev, "single-chip addressing mode\n");
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@ -470,7 +474,11 @@ e6000sw_attach(device_t dev)
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etherswitch_info.es_nports = sc->num_ports;
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/* Default to port vlan. */
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e6000sw_port_vlan_conf(sc);
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e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT);
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reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS);
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if (reg & SWITCH_GLOBAL_STATUS_IR)
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device_printf(dev, "switch is ready.\n");
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E6000SW_UNLOCK(sc);
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bus_generic_probe(dev);
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@ -487,21 +495,19 @@ out_fail:
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return (err);
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}
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static __inline int
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e6000sw_poll_done(e6000sw_softc_t *sc)
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static int
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e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg,
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uint32_t busybit)
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{
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int i;
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for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) {
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if ((e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG) &
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(1 << PHY_CMD_SMI_BUSY)) == 0)
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for (i = 0; i < E6000SW_RETRIES; i++) {
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if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0)
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return (0);
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pause("e6000sw PHY poll", hz/1000);
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DELAY(1);
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}
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return (ETIMEDOUT);
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return (1);
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}
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/*
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@ -513,7 +519,6 @@ e6000sw_readphy(device_t dev, int phy, int reg)
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{
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e6000sw_softc_t *sc;
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uint32_t val;
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int err;
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sc = device_get_softc(dev);
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if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {
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@ -522,24 +527,17 @@ e6000sw_readphy(device_t dev, int phy, int reg)
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}
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E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
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err = e6000sw_poll_done(sc);
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if (err != 0) {
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (err);
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return (ETIMEDOUT);
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}
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val = 1 << PHY_CMD_SMI_BUSY;
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val |= PHY_CMD_MODE_MDIO << PHY_CMD_MODE;
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val |= PHY_CMD_OPCODE_READ << PHY_CMD_OPCODE;
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val |= (reg << PHY_CMD_REG_ADDR) & PHY_CMD_REG_ADDR_MASK;
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val |= (phy << PHY_CMD_DEV_ADDR) & PHY_CMD_DEV_ADDR_MASK;
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, val);
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err = e6000sw_poll_done(sc);
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if (err != 0) {
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) |
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((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (err);
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return (ETIMEDOUT);
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}
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val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG);
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@ -551,8 +549,6 @@ static int
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e6000sw_writephy(device_t dev, int phy, int reg, int data)
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{
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e6000sw_softc_t *sc;
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uint32_t val;
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int err;
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sc = device_get_softc(dev);
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if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {
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@ -561,27 +557,18 @@ e6000sw_writephy(device_t dev, int phy, int reg, int data)
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}
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E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
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err = e6000sw_poll_done(sc);
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if (err != 0) {
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (err);
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return (ETIMEDOUT);
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}
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val = 1 << PHY_CMD_SMI_BUSY;
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val |= PHY_CMD_MODE_MDIO << PHY_CMD_MODE;
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val |= PHY_CMD_OPCODE_WRITE << PHY_CMD_OPCODE;
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val |= (reg << PHY_CMD_REG_ADDR) & PHY_CMD_REG_ADDR_MASK;
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val |= (phy << PHY_CMD_DEV_ADDR) & PHY_CMD_DEV_ADDR_MASK;
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG,
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data & PHY_DATA_MASK);
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, val);
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) |
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((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));
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err = e6000sw_poll_done(sc);
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if (err != 0)
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device_printf(dev, "Timeout while waiting for switch\n");
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return (err);
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return (0);
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}
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static int
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@ -625,6 +612,22 @@ e6000sw_getconf(device_t dev, etherswitch_conf_t *conf)
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return (0);
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}
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static int
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e6000sw_setconf(device_t dev, etherswitch_conf_t *conf)
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{
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struct e6000sw_softc *sc;
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/* Set the VLAN mode. */
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sc = device_get_softc(dev);
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if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) {
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E6000SW_LOCK(sc);
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e6000sw_set_vlan_mode(sc, conf->vlan_mode);
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E6000SW_UNLOCK(sc);
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}
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return (0);
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}
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static void
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e6000sw_lock(device_t dev)
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{
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@ -653,6 +656,7 @@ e6000sw_getport(device_t dev, etherswitch_port_t *p)
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struct mii_data *mii;
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int err;
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struct ifmediareq *ifmr;
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uint32_t reg;
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e6000sw_softc_t *sc = device_get_softc(dev);
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E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED);
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@ -662,10 +666,17 @@ e6000sw_getport(device_t dev, etherswitch_port_t *p)
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if (!e6000sw_is_portenabled(sc, p->es_port))
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return (0);
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err = 0;
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E6000SW_LOCK(sc);
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e6000sw_get_pvid(sc, p->es_port, &p->es_pvid);
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/* Port flags. */
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reg = e6000sw_readreg(sc, REG_PORT(p->es_port), PORT_CONTROL2);
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if (reg & PORT_CONTROL2_DISC_TAGGED)
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p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED;
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if (reg & PORT_CONTROL2_DISC_UNTAGGED)
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p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED;
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err = 0;
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if (e6000sw_is_fixedport(sc, p->es_port)) {
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if (e6000sw_is_cpuport(sc, p->es_port))
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p->es_flags |= ETHERSWITCH_PORT_CPU;
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@ -695,6 +706,7 @@ e6000sw_setport(device_t dev, etherswitch_port_t *p)
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e6000sw_softc_t *sc;
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int err;
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struct mii_data *mii;
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uint32_t reg;
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sc = device_get_softc(dev);
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E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED);
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@ -704,6 +716,18 @@ e6000sw_setport(device_t dev, etherswitch_port_t *p)
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if (!e6000sw_is_portenabled(sc, p->es_port))
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return (0);
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/* Port flags. */
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reg = e6000sw_readreg(sc, REG_PORT(p->es_port), PORT_CONTROL2);
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if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED)
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reg |= PORT_CONTROL2_DISC_TAGGED;
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else
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reg &= ~PORT_CONTROL2_DISC_TAGGED;
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if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED)
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reg |= PORT_CONTROL2_DISC_UNTAGGED;
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else
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reg &= ~PORT_CONTROL2_DISC_UNTAGGED;
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e6000sw_writereg(sc, REG_PORT(p->es_port), PORT_CONTROL2, reg);
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err = 0;
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E6000SW_LOCK(sc);
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if (p->es_pvid != 0)
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@ -718,6 +742,128 @@ e6000sw_setport(device_t dev, etherswitch_port_t *p)
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return (err);
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}
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static __inline void
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e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid,
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uint32_t members)
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{
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uint32_t reg;
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reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VLAN_MAP);
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reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK);
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reg |= members & PORT_MASK(sc) & ~(1 << port);
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reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK;
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e6000sw_writereg(sc, REG_PORT(port), PORT_VLAN_MAP, reg);
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reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL1);
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reg &= ~PORT_CONTROL1_FID_MASK;
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reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK;
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL1, reg);
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}
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static int
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e6000sw_init_vlan(struct e6000sw_softc *sc)
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{
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int i, port, ret;
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uint32_t members;
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/* Disable all ports */
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for (port = 0; port < sc->num_ports; port++) {
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
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(ret & ~PORT_CONTROL_ENABLE));
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}
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/* Flush VTU. */
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e6000sw_vtu_flush(sc);
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for (port = 0; port < sc->num_ports; port++) {
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/* Reset the egress and frame mode. */
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
|
||||
ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL, ret);
|
||||
|
||||
/* Set the the 802.1q mode. */
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL2);
|
||||
ret &= ~PORT_CONTROL2_DOT1Q;
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
ret |= PORT_CONTROL2_DOT1Q;
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL2, ret);
|
||||
}
|
||||
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
if (!e6000sw_is_portenabled(sc, port))
|
||||
continue;
|
||||
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
|
||||
|
||||
/* Set port priority */
|
||||
ret &= ~PORT_VID_PRIORITY_MASK;
|
||||
|
||||
/* Set VID map */
|
||||
ret &= ~PORT_VID_DEF_VID_MASK;
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
ret |= 1;
|
||||
else
|
||||
ret |= (port + 1);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, ret);
|
||||
}
|
||||
|
||||
/* Assign the member ports to each origin port. */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
members = 0;
|
||||
if (e6000sw_is_portenabled(sc, port)) {
|
||||
for (i = 0; i < sc->num_ports; i++) {
|
||||
if (i == port || !e6000sw_is_portenabled(sc, i))
|
||||
continue;
|
||||
members |= (1 << i);
|
||||
}
|
||||
}
|
||||
/* Default to FID 0. */
|
||||
e6000sw_port_vlan_assign(sc, port, 0, members);
|
||||
}
|
||||
|
||||
/* Reset internal VLAN table. */
|
||||
for (i = 0; i < nitems(sc->vlans); i++)
|
||||
sc->vlans[i] = 0;
|
||||
|
||||
/* Create default VLAN (1). */
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
|
||||
sc->vlans[0] = 1;
|
||||
e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask);
|
||||
}
|
||||
|
||||
/* Enable all ports */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
if (!e6000sw_is_portenabled(sc, port))
|
||||
continue;
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
|
||||
(ret | PORT_CONTROL_ENABLE));
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode)
|
||||
{
|
||||
|
||||
E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
|
||||
switch (mode) {
|
||||
case ETHERSWITCH_VLAN_PORT:
|
||||
sc->vlan_mode = ETHERSWITCH_VLAN_PORT;
|
||||
etherswitch_info.es_nvlangroups = sc->num_ports;
|
||||
return (e6000sw_init_vlan(sc));
|
||||
break;
|
||||
case ETHERSWITCH_VLAN_DOT1Q:
|
||||
sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
|
||||
etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS;
|
||||
return (e6000sw_init_vlan(sc));
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Registers in this switch are divided into sections, specified in
|
||||
* documentation. So as to access any of them, section index and reg index
|
||||
@ -825,24 +971,6 @@ e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg)
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid,
|
||||
uint32_t members)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VLAN_MAP);
|
||||
reg &= ~PORT_VLAN_MAP_TABLE_MASK;
|
||||
reg &= ~PORT_VLAN_MAP_FID_MASK;
|
||||
reg |= members & PORT_VLAN_MAP_TABLE_MASK & ~(1 << port);
|
||||
reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK;
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VLAN_MAP, reg);
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL_1);
|
||||
reg &= ~PORT_CONTROL_1_FID_MASK;
|
||||
reg |= (fid >> 4) & PORT_CONTROL_1_FID_MASK;
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL_1, reg);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
@ -857,12 +985,40 @@ e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
e6000sw_port_vlan_assign(sc, port, port + 1, vg->es_untagged_ports);
|
||||
e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports);
|
||||
vg->es_vid = port | ETHERSWITCH_VID_VALID;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
int i, vlan;
|
||||
|
||||
vlan = vg->es_vid & ETHERSWITCH_VID_MASK;
|
||||
|
||||
/* Set VLAN to '0' removes it from table. */
|
||||
if (vlan == 0) {
|
||||
e6000sw_vtu_update(sc, VTU_PURGE,
|
||||
sc->vlans[vg->es_vlangroup], 0, 0, 0);
|
||||
sc->vlans[vg->es_vlangroup] = 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Is this VLAN already in table ? */
|
||||
for (i = 0; i < etherswitch_info.es_nvlangroups; i++)
|
||||
if (i != vg->es_vlangroup && vlan == sc->vlans[i])
|
||||
return (EINVAL);
|
||||
|
||||
sc->vlans[vg->es_vlangroup] = vlan;
|
||||
e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1,
|
||||
vg->es_member_ports & sc->ports_mask,
|
||||
vg->es_untagged_ports & sc->ports_mask);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
@ -873,6 +1029,8 @@ e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
|
||||
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT)
|
||||
return (e6000sw_set_port_vlan(sc, vg));
|
||||
else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
return (e6000sw_set_dot1q_vlan(sc, vg));
|
||||
|
||||
return (EINVAL);
|
||||
}
|
||||
@ -892,12 +1050,61 @@ e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
}
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VLAN_MAP);
|
||||
vg->es_untagged_ports = vg->es_member_ports =
|
||||
reg & PORT_VLAN_MAP_TABLE_MASK;
|
||||
vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc);
|
||||
vg->es_vid = port | ETHERSWITCH_VID_VALID;
|
||||
vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID;
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL_1);
|
||||
vg->es_fid |= (reg & PORT_CONTROL_1_FID_MASK) << 4;
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL1);
|
||||
vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
int i, port;
|
||||
uint32_t reg;
|
||||
|
||||
vg->es_fid = 0;
|
||||
vg->es_vid = sc->vlans[vg->es_vlangroup];
|
||||
vg->es_untagged_ports = vg->es_member_ports = 0;
|
||||
if (vg->es_vid == 0)
|
||||
return (0);
|
||||
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "VTU unit is busy, cannot access\n");
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1);
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION);
|
||||
reg &= ~VTU_OP_MASK;
|
||||
reg |= VTU_GET_NEXT | VTU_BUSY;
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg);
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "Timeout while reading\n");
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID);
|
||||
if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0)
|
||||
return (EINVAL);
|
||||
if ((reg & VTU_VID_MASK) != vg->es_vid)
|
||||
return (EINVAL);
|
||||
|
||||
vg->es_vid |= ETHERSWITCH_VID_VALID;
|
||||
reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA);
|
||||
for (i = 0; i < sc->num_ports; i++) {
|
||||
if (i == VTU_PPREG(sc))
|
||||
reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2);
|
||||
port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK;
|
||||
if (port == VTU_PORT_UNTAGGED) {
|
||||
vg->es_untagged_ports |= (1 << i);
|
||||
vg->es_member_ports |= (1 << i);
|
||||
} else if (port == VTU_PORT_TAGGED)
|
||||
vg->es_member_ports |= (1 << i);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -912,6 +1119,8 @@ e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
|
||||
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT)
|
||||
return (e6000sw_get_port_vlan(sc, vg));
|
||||
else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
return (e6000sw_get_dot1q_vlan(sc, vg));
|
||||
|
||||
return (EINVAL);
|
||||
}
|
||||
@ -978,7 +1187,7 @@ e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg)
|
||||
|
||||
E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
|
||||
|
||||
if (!sc->multi_chip)
|
||||
if (!MVSWITCH_MULTICHIP(sc))
|
||||
return (MDIO_READ(sc->dev, addr, reg) & 0xffff);
|
||||
|
||||
if (e6000sw_smi_waitready(sc, sc->sw_addr)) {
|
||||
@ -986,7 +1195,8 @@ e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg)
|
||||
return (0xffff);
|
||||
}
|
||||
MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD,
|
||||
SMI_CMD_OP_READ | (addr << 5) | reg);
|
||||
SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) |
|
||||
((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));
|
||||
if (e6000sw_smi_waitready(sc, sc->sw_addr)) {
|
||||
printf("e6000sw: readreg timeout\n");
|
||||
return (0xffff);
|
||||
@ -1001,7 +1211,7 @@ e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val)
|
||||
|
||||
E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
|
||||
|
||||
if (!sc->multi_chip) {
|
||||
if (!MVSWITCH_MULTICHIP(sc)) {
|
||||
MDIO_WRITE(sc->dev, addr, reg, val);
|
||||
return;
|
||||
}
|
||||
@ -1012,11 +1222,8 @@ e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val)
|
||||
}
|
||||
MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val);
|
||||
MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD,
|
||||
SMI_CMD_OP_WRITE | (addr << 5) | reg);
|
||||
if (e6000sw_smi_waitready(sc, sc->sw_addr)) {
|
||||
printf("e6000sw: readreg timeout\n");
|
||||
return;
|
||||
}
|
||||
SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) |
|
||||
((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));
|
||||
}
|
||||
|
||||
static __inline bool
|
||||
@ -1056,14 +1263,15 @@ e6000sw_is_portenabled(e6000sw_softc_t *sc, int port)
|
||||
return ((sc->ports_mask & (1 << port)) ? true : false);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
static __inline void
|
||||
e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, pvid &
|
||||
PORT_VID_DEF_VID_MASK);
|
||||
|
||||
return (0);
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
|
||||
reg &= ~PORT_VID_DEF_VID_MASK;
|
||||
reg |= (pvid & PORT_VID_DEF_VID_MASK);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, reg);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
@ -1114,7 +1322,7 @@ e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_ac
|
||||
}
|
||||
|
||||
static void
|
||||
e6000sw_tick (void *arg)
|
||||
e6000sw_tick(void *arg)
|
||||
{
|
||||
e6000sw_softc_t *sc;
|
||||
struct mii_data *mii;
|
||||
@ -1159,12 +1367,13 @@ e6000sw_tick (void *arg)
|
||||
static void
|
||||
e6000sw_setup(device_t dev, e6000sw_softc_t *sc)
|
||||
{
|
||||
uint16_t atu_ctrl, atu_age;
|
||||
uint32_t atu_ctrl;
|
||||
|
||||
/* Set aging time */
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL,
|
||||
(E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME) |
|
||||
(1 << ATU_CONTROL_LEARN2ALL));
|
||||
/* Set aging time. */
|
||||
atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL);
|
||||
atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK;
|
||||
atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME;
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl);
|
||||
|
||||
/* Send all with specific mac address to cpu port */
|
||||
e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL);
|
||||
@ -1183,73 +1392,6 @@ e6000sw_setup(device_t dev, e6000sw_softc_t *sc)
|
||||
e6000sw_atu_flush(dev, sc, NO_OPERATION);
|
||||
e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION);
|
||||
e6000sw_set_atustat(dev, sc, 0, COUNT_ALL);
|
||||
|
||||
/* Set ATU AgeTime to 15 seconds */
|
||||
atu_age = 1;
|
||||
|
||||
atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL);
|
||||
|
||||
/* Set new AgeTime field */
|
||||
atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK;
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl |
|
||||
(atu_age << ATU_CONTROL_AGETIME));
|
||||
}
|
||||
|
||||
static void
|
||||
e6000sw_port_vlan_conf(e6000sw_softc_t *sc)
|
||||
{
|
||||
int i, port, ret;
|
||||
uint32_t members;
|
||||
|
||||
/* Disable all ports */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
|
||||
(ret & ~PORT_CONTROL_ENABLE));
|
||||
}
|
||||
|
||||
/* Set port priority */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
if (!e6000sw_is_portenabled(sc, port))
|
||||
continue;
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
|
||||
ret &= ~PORT_VID_PRIORITY_MASK;
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, ret);
|
||||
}
|
||||
|
||||
/* Set VID map */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
if (!e6000sw_is_portenabled(sc, port))
|
||||
continue;
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
|
||||
ret &= ~PORT_VID_DEF_VID_MASK;
|
||||
ret |= (port + 1);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, ret);
|
||||
}
|
||||
|
||||
/* Enable all ports */
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
if (!e6000sw_is_portenabled(sc, port))
|
||||
continue;
|
||||
ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
|
||||
(ret | PORT_CONTROL_ENABLE));
|
||||
}
|
||||
|
||||
/* Set VLAN mode. */
|
||||
sc->vlan_mode = ETHERSWITCH_VLAN_PORT;
|
||||
etherswitch_info.es_nvlangroups = sc->num_ports;
|
||||
for (port = 0; port < sc->num_ports; port++) {
|
||||
members = 0;
|
||||
if (e6000sw_is_portenabled(sc, port)) {
|
||||
for (i = 0; i < sc->num_ports; i++) {
|
||||
if (i == port || !e6000sw_is_portenabled(sc, i))
|
||||
continue;
|
||||
members |= (1 << i);
|
||||
}
|
||||
}
|
||||
e6000sw_port_vlan_assign(sc, port, port + 1, members);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1268,7 +1410,6 @@ e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu,
|
||||
{
|
||||
uint16_t ret_opt;
|
||||
uint16_t ret_data;
|
||||
int retries;
|
||||
|
||||
if (flag == NO_OPERATION)
|
||||
return (0);
|
||||
@ -1278,41 +1419,34 @@ e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu,
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION);
|
||||
|
||||
if (ret_opt & ATU_UNIT_BUSY) {
|
||||
device_printf(dev, "ATU unit is busy, cannot access"
|
||||
"register\n");
|
||||
if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) {
|
||||
device_printf(dev, "ATU unit is busy, cannot access\n");
|
||||
return (EBUSY);
|
||||
} else {
|
||||
if(flag & LOAD_FROM_FIB) {
|
||||
ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA);
|
||||
e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data &
|
||||
~ENTRY_STATE));
|
||||
}
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid);
|
||||
}
|
||||
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, (ret_opt |
|
||||
ATU_UNIT_BUSY | flag));
|
||||
ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION);
|
||||
if (flag & LOAD_FROM_FIB) {
|
||||
ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA);
|
||||
e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data &
|
||||
~ENTRY_STATE));
|
||||
}
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid);
|
||||
|
||||
retries = E6000SW_RETRIES;
|
||||
while (--retries & (e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_OPERATION) & ATU_UNIT_BUSY))
|
||||
DELAY(1);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION,
|
||||
(ret_opt | ATU_UNIT_BUSY | flag));
|
||||
|
||||
if (retries == 0)
|
||||
device_printf(dev, "Timeout while flushing\n");
|
||||
else if (flag & GET_NEXT_IN_FIB) {
|
||||
atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR01);
|
||||
atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR23);
|
||||
atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR45);
|
||||
}
|
||||
if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY))
|
||||
device_printf(dev, "Timeout while waiting ATU\n");
|
||||
else if (flag & GET_NEXT_IN_FIB) {
|
||||
atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR01);
|
||||
atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR23);
|
||||
atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_MAC_ADDR45);
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -1321,26 +1455,85 @@ e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu,
|
||||
static int
|
||||
e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag)
|
||||
{
|
||||
uint16_t ret;
|
||||
int retries;
|
||||
uint32_t reg;
|
||||
|
||||
if (flag == NO_OPERATION)
|
||||
return (0);
|
||||
|
||||
ret = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION);
|
||||
if (ret & ATU_UNIT_BUSY) {
|
||||
device_printf(dev, "Atu unit is busy, cannot flush\n");
|
||||
if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) {
|
||||
device_printf(dev, "ATU unit is busy, cannot access\n");
|
||||
return (EBUSY);
|
||||
} else {
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, (ret |
|
||||
ATU_UNIT_BUSY | flag));
|
||||
retries = E6000SW_RETRIES;
|
||||
while (--retries & (e6000sw_readreg(sc, REG_GLOBAL,
|
||||
ATU_OPERATION) & ATU_UNIT_BUSY))
|
||||
DELAY(1);
|
||||
}
|
||||
reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION,
|
||||
(reg | ATU_UNIT_BUSY | flag));
|
||||
if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY))
|
||||
device_printf(dev, "Timeout while flushing ATU\n");
|
||||
|
||||
if (retries == 0)
|
||||
device_printf(dev, "Timeout while flushing\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_vtu_flush(e6000sw_softc_t *sc)
|
||||
{
|
||||
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "VTU unit is busy, cannot access\n");
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY);
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "Timeout while flushing VTU\n");
|
||||
return (ETIMEDOUT);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid,
|
||||
int members, int untagged)
|
||||
{
|
||||
int i, op;
|
||||
uint32_t data[2];
|
||||
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "VTU unit is busy, cannot access\n");
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
*data = (vid & VTU_VID_MASK);
|
||||
if (purge == 0)
|
||||
*data |= VTU_VID_VALID;
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data);
|
||||
|
||||
if (purge == 0) {
|
||||
data[0] = 0;
|
||||
data[1] = 0;
|
||||
for (i = 0; i < sc->num_ports; i++) {
|
||||
if ((untagged & (1 << i)) != 0)
|
||||
data[i / VTU_PPREG(sc)] |=
|
||||
VTU_PORT_UNTAGGED << VTU_PORT(sc, i);
|
||||
else if ((members & (1 << i)) != 0)
|
||||
data[i / VTU_PPREG(sc)] |=
|
||||
VTU_PORT_TAGGED << VTU_PORT(sc, i);
|
||||
else
|
||||
data[i / VTU_PPREG(sc)] |=
|
||||
VTU_PORT_DISCARD << VTU_PORT(sc, i);
|
||||
}
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]);
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_FID,
|
||||
fid & VTU_FID_MASK(sc));
|
||||
op = VTU_LOAD;
|
||||
} else
|
||||
op = VTU_PURGE;
|
||||
|
||||
e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY);
|
||||
if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) {
|
||||
device_printf(sc->dev, "Timeout while flushing VTU\n");
|
||||
return (ETIMEDOUT);
|
||||
}
|
||||
|
||||
return (0);
|
||||
|
||||
@ -29,7 +29,7 @@
|
||||
*/
|
||||
|
||||
#ifndef _E6000SWREG_H_
|
||||
#define _E6000SWREG_H_
|
||||
#define _E6000SWREG_H_
|
||||
|
||||
struct atu_opt {
|
||||
uint16_t mac_01;
|
||||
@ -50,20 +50,21 @@ struct atu_opt {
|
||||
#define MV88E6176 0x1760
|
||||
|
||||
#define MVSWITCH(_sc, id) ((_sc)->swid == (id))
|
||||
#define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0)
|
||||
|
||||
/*
|
||||
* Switch Registers
|
||||
*/
|
||||
#define REG_GLOBAL 0x1b
|
||||
#define REG_GLOBAL2 0x1c
|
||||
#define REG_PORT(p) (0x10 + (p))
|
||||
#define REG_GLOBAL 0x1b
|
||||
#define REG_GLOBAL2 0x1c
|
||||
#define REG_PORT(p) (0x10 + (p))
|
||||
|
||||
#define REG_NUM_MAX 31
|
||||
#define REG_NUM_MAX 31
|
||||
|
||||
/*
|
||||
* Per-Port Switch Registers
|
||||
*/
|
||||
#define PORT_STATUS 0x0
|
||||
#define PORT_STATUS 0x0
|
||||
#define PORT_STATUS_SPEED_MASK 0x300
|
||||
#define PORT_STATUS_SPEED_10 0
|
||||
#define PORT_STATUS_SPEED_100 1
|
||||
@ -72,7 +73,7 @@ struct atu_opt {
|
||||
#define PORT_STATUS_LINK_MASK (1 << 11)
|
||||
#define PORT_STATUS_PHY_DETECT_MASK (1 << 12)
|
||||
|
||||
#define PSC_CONTROL 0x1
|
||||
#define PSC_CONTROL 0x1
|
||||
#define PSC_CONTROL_FORCED_SPD (1 << 13)
|
||||
#define PSC_CONTROL_ALT_SPD (1 << 12)
|
||||
#define PSC_CONTROL_EEE_ON (1 << 9)
|
||||
@ -83,130 +84,221 @@ struct atu_opt {
|
||||
#define PSC_CONTROL_FORCED_LINK (1 << 4)
|
||||
#define PSC_CONTROL_FULLDPX (1 << 3)
|
||||
#define PSC_CONTROL_FORCED_DPX (1 << 2)
|
||||
#define PSC_CONTROL_SPD2500 0x3
|
||||
#define PSC_CONTROL_SPD10G 0x3
|
||||
#define PSC_CONTROL_SPD2500 PSC_CONTROL_SPD10G
|
||||
#define PSC_CONTROL_SPD1000 0x2
|
||||
#define SWITCH_ID 0x3
|
||||
#define PORT_CONTROL 0x4
|
||||
#define PORT_CONTROL_1 0x5
|
||||
#define PORT_CONTROL_1_FID_MASK 0xf
|
||||
#define PORT_VLAN_MAP 0x6
|
||||
#define PORT_VID 0x7
|
||||
#define PORT_ASSOCIATION_VECTOR 0xb
|
||||
#define PORT_ATU_CTRL 0xc
|
||||
#define RX_COUNTER 0x12
|
||||
#define TX_COUNTER 0x13
|
||||
#define SWITCH_ID 0x3
|
||||
#define PORT_CONTROL 0x4
|
||||
#define PORT_CONTROL1 0x5
|
||||
#define PORT_CONTROL1_LAG_PORT (1 << 14)
|
||||
#define PORT_CONTROL1_LAG_ID_MASK 0xf
|
||||
#define PORT_CONTROL1_LAG_ID_SHIFT 8
|
||||
#define PORT_CONTROL1_FID_MASK 0xf
|
||||
#define PORT_VLAN_MAP 0x6
|
||||
#define PORT_VID 0x7
|
||||
#define PORT_CONTROL2 0x8
|
||||
#define PORT_ASSOCIATION_VECTOR 0xb
|
||||
#define PORT_ATU_CTRL 0xc
|
||||
#define RX_COUNTER 0x12
|
||||
#define TX_COUNTER 0x13
|
||||
|
||||
#define PORT_VID_DEF_VID 0
|
||||
#define PORT_VID_DEF_VID_MASK 0xfff
|
||||
#define PORT_VID_PRIORITY_MASK 0xc00
|
||||
#define PORT_MASK(_sc) 0x7f
|
||||
#define PORT_VID_DEF_VID 0
|
||||
#define PORT_VID_DEF_VID_MASK 0xfff
|
||||
#define PORT_VID_PRIORITY_MASK 0xc00
|
||||
|
||||
#define PORT_CONTROL_ENABLE 0x3
|
||||
#define PORT_CONTROL_DISABLED 0
|
||||
#define PORT_CONTROL_BLOCKING 1
|
||||
#define PORT_CONTROL_LEARNING 2
|
||||
#define PORT_CONTROL_FORWARDING 3
|
||||
#define PORT_CONTROL_ENABLE 3
|
||||
#define PORT_CONTROL_FRAME 0x0300
|
||||
#define PORT_CONTROL_EGRESS 0x3000
|
||||
#define PORT_CONTROL2_DOT1Q 0x0c00
|
||||
#define PORT_CONTROL2_DISC_TAGGED (1 << 9)
|
||||
#define PORT_CONTROL2_DISC_UNTAGGED (1 << 8)
|
||||
|
||||
/* PORT_VLAN fields */
|
||||
#define PORT_VLAN_MAP_TABLE_MASK 0x7f
|
||||
#define PORT_VLAN_MAP_FID 12
|
||||
#define PORT_VLAN_MAP_FID_MASK 0xf000
|
||||
#define PORT_VLAN_MAP_FID 12
|
||||
#define PORT_VLAN_MAP_FID_MASK 0xf000
|
||||
|
||||
/*
|
||||
* Switch Global Register 1 accessed via REG_GLOBAL_ADDR
|
||||
*/
|
||||
#define SWITCH_GLOBAL_STATUS 0
|
||||
#define SWITCH_GLOBAL_CONTROL 4
|
||||
#define SWITCH_GLOBAL_CONTROL2 28
|
||||
#define SWITCH_GLOBAL_STATUS 0
|
||||
#define SWITCH_GLOBAL_STATUS_IR (1 << 11)
|
||||
#define SWITCH_GLOBAL_CONTROL 4
|
||||
#define SWITCH_GLOBAL_CONTROL2 28
|
||||
|
||||
#define MONITOR_CONTROL 26
|
||||
#define MONITOR_CONTROL 26
|
||||
|
||||
/* VTU operation */
|
||||
#define VTU_FID 2
|
||||
#define VTU_OPERATION 5
|
||||
#define VTU_VID 6
|
||||
#define VTU_DATA 7
|
||||
#define VTU_DATA2 8
|
||||
|
||||
#define VTU_FID_MASK(_sc) 0xff
|
||||
#define VTU_FID_POLICY (1 << 12)
|
||||
#define VTU_PORT_UNMODIFIED 0
|
||||
#define VTU_PORT_UNTAGGED 1
|
||||
#define VTU_PORT_TAGGED 2
|
||||
#define VTU_PORT_DISCARD 3
|
||||
#define VTU_PPREG(_sc) 4
|
||||
#define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc)))
|
||||
#define VTU_PORT_MASK 3
|
||||
#define VTU_BUSY (1 << 15)
|
||||
#define VTU_VID_VALID (1 << 12)
|
||||
#define VTU_VID_MASK 0xfff
|
||||
|
||||
/* VTU opcodes */
|
||||
#define VTU_OP_MASK (7 << 12)
|
||||
#define VTU_NOP (0 << 12)
|
||||
#define VTU_FLUSH (1 << 12)
|
||||
#define VTU_LOAD (3 << 12)
|
||||
#define VTU_PURGE (3 << 12)
|
||||
#define VTU_GET_NEXT (4 << 12)
|
||||
#define STU_LOAD (5 << 12)
|
||||
#define STU_PURGE (5 << 12)
|
||||
#define STU_GET_NEXT (6 << 12)
|
||||
#define VTU_GET_VIOLATION_DATA (7 << 12)
|
||||
#define VTU_CLEAR_VIOLATION_DATA (7 << 12)
|
||||
|
||||
/* ATU operation */
|
||||
#define ATU_FID 1
|
||||
#define ATU_CONTROL 10
|
||||
#define ATU_OPERATION 11
|
||||
#define ATU_DATA 12
|
||||
#define ATU_MAC_ADDR01 13
|
||||
#define ATU_MAC_ADDR23 14
|
||||
#define ATU_MAC_ADDR45 15
|
||||
#define ATU_FID 1
|
||||
#define ATU_CONTROL 10
|
||||
#define ATU_OPERATION 11
|
||||
#define ATU_DATA 12
|
||||
#define ATU_MAC_ADDR01 13
|
||||
#define ATU_MAC_ADDR23 14
|
||||
#define ATU_MAC_ADDR45 15
|
||||
|
||||
#define ATU_UNIT_BUSY (1 << 15)
|
||||
#define ENTRY_STATE 0xf
|
||||
#define ATU_DATA_LAG (1 << 15)
|
||||
#define ATU_PORT_MASK(_sc) 0xff0
|
||||
#define ATU_PORT_SHIFT 4
|
||||
#define ATU_LAG_MASK 0xf0
|
||||
#define ATU_LAG_SHIFT 4
|
||||
#define ATU_STATE_MASK 0xf
|
||||
#define ATU_UNIT_BUSY (1 << 15)
|
||||
#define ENTRY_STATE 0xf
|
||||
|
||||
/* ATU_CONTROL fields */
|
||||
#define ATU_CONTROL_AGETIME 4
|
||||
#define ATU_CONTROL_AGETIME_MASK 0xff0
|
||||
#define ATU_CONTROL_LEARN2ALL 3
|
||||
#define ATU_CONTROL_AGETIME 4
|
||||
#define ATU_CONTROL_AGETIME_MASK 0xff0
|
||||
#define ATU_CONTROL_LEARN2ALL 3
|
||||
|
||||
/* ATU opcode */
|
||||
#define NO_OPERATION (0 << 0)
|
||||
#define FLUSH_ALL (1 << 0)
|
||||
#define FLUSH_NON_STATIC (1 << 1)
|
||||
#define LOAD_FROM_FIB (3 << 0)
|
||||
#define PURGE_FROM_FIB (3 << 0)
|
||||
#define GET_NEXT_IN_FIB (1 << 2)
|
||||
#define FLUSH_ALL_IN_FIB (5 << 0)
|
||||
#define FLUSH_NON_STATIC_IN_FIB (3 << 1)
|
||||
#define GET_VIOLATION_DATA (7 << 0)
|
||||
#define CLEAR_VIOLATION_DATA (7 << 0)
|
||||
#define ATU_OP_MASK (7 << 12)
|
||||
#define NO_OPERATION (0 << 12)
|
||||
#define FLUSH_ALL (1 << 12)
|
||||
#define FLUSH_NON_STATIC (2 << 12)
|
||||
#define LOAD_FROM_FIB (3 << 12)
|
||||
#define PURGE_FROM_FIB (3 << 12)
|
||||
#define GET_NEXT_IN_FIB (4 << 12)
|
||||
#define FLUSH_ALL_IN_FIB (5 << 12)
|
||||
#define FLUSH_NON_STATIC_IN_FIB (6 << 12)
|
||||
#define GET_VIOLATION_DATA (7 << 12)
|
||||
#define CLEAR_VIOLATION_DATA (7 << 12)
|
||||
|
||||
/* ATU Stats */
|
||||
#define COUNT_ALL (0 << 0)
|
||||
#define COUNT_ALL (0 << 0)
|
||||
|
||||
/*
|
||||
* Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
|
||||
*/
|
||||
#define MGMT_EN_2x 2
|
||||
#define MGMT_EN_0x 3
|
||||
#define SWITCH_MGMT 5
|
||||
#define ATU_STATS 14
|
||||
#define MGMT_EN_2x 2
|
||||
#define MGMT_EN_0x 3
|
||||
#define SWITCH_MGMT 5
|
||||
#define LAG_MASK 7
|
||||
#define LAG_MAPPING 8
|
||||
#define ATU_STATS 14
|
||||
|
||||
#define MGMT_EN_ALL 0xffff
|
||||
#define MGMT_EN_ALL 0xffff
|
||||
#define LAG_UPDATE (1 << 15)
|
||||
#define LAG_MASKNUM_SHIFT 12
|
||||
#define LAGID_SHIFT 11
|
||||
|
||||
/* SWITCH_MGMT fields */
|
||||
|
||||
#define SWITCH_MGMT_PRI 0
|
||||
#define SWITCH_MGMT_PRI_MASK 7
|
||||
#define SWITCH_MGMT_PRI 0
|
||||
#define SWITCH_MGMT_PRI_MASK 7
|
||||
#define SWITCH_MGMT_RSVD2CPU 3
|
||||
#define SWITCH_MGMT_FC_PRI 4
|
||||
#define SWITCH_MGMT_FC_PRI_MASK (7 << 4)
|
||||
#define SWITCH_MGMT_FORCEFLOW 7
|
||||
#define SWITCH_MGMT_FC_PRI 4
|
||||
#define SWITCH_MGMT_FC_PRI_MASK (7 << 4)
|
||||
#define SWITCH_MGMT_FORCEFLOW 7
|
||||
|
||||
/* ATU_STATS fields */
|
||||
|
||||
#define ATU_STATS_BIN 14
|
||||
#define ATU_STATS_FLAG 12
|
||||
#define ATU_STATS_BIN 14
|
||||
#define ATU_STATS_FLAG 12
|
||||
|
||||
/* Offset of SMI registers in multi-chip setup. */
|
||||
#define SMI_CMD 0
|
||||
#define SMI_DATA 1
|
||||
|
||||
/*
|
||||
* PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2).
|
||||
* 'Switch Global Registers 2' (REG_GLOBAL2).
|
||||
*/
|
||||
#define SMI_PHY_CMD_REG 0x18
|
||||
#define SMI_PHY_DATA_REG 0x19
|
||||
|
||||
#define PHY_DATA_MASK 0xffff
|
||||
/* EEPROM registers */
|
||||
#define EEPROM_CMD 0x14
|
||||
#define EEPROM_BUSY (1 << 15)
|
||||
#define EEPROM_READ_CMD (4 << 12)
|
||||
#define EEPROM_WRITE_CMD (3 << 12)
|
||||
#define EEPROM_WRITE_EN (1 << 10)
|
||||
#define EEPROM_DATA_MASK 0xff
|
||||
#define EEPROM_ADDR 0x15
|
||||
|
||||
#define PHY_CMD_SMI_BUSY 15
|
||||
#define PHY_CMD_MODE 12
|
||||
#define PHY_CMD_MODE_MDIO 1
|
||||
#define PHY_CMD_MODE_XMDIO 0
|
||||
#define PHY_CMD_OPCODE 10
|
||||
#define PHY_CMD_OPCODE_WRITE 1
|
||||
#define PHY_CMD_OPCODE_READ 2
|
||||
#define PHY_CMD_DEV_ADDR 5
|
||||
#define PHY_CMD_DEV_ADDR_MASK 0x3e0
|
||||
#define PHY_CMD_REG_ADDR 0
|
||||
#define PHY_CMD_REG_ADDR_MASK 0x1f
|
||||
/* PHY registers */
|
||||
#define SMI_PHY_CMD_REG 0x18
|
||||
#define SMI_CMD_BUSY (1 << 15)
|
||||
#define SMI_CMD_MODE_C22 (1 << 12)
|
||||
#define SMI_CMD_C22_WRITE (1 << 10)
|
||||
#define SMI_CMD_C22_READ (2 << 10)
|
||||
#define SMI_CMD_OP_C22_WRITE \
|
||||
(SMI_CMD_C22_WRITE | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
|
||||
#define SMI_CMD_OP_C22_READ \
|
||||
(SMI_CMD_C22_READ | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
|
||||
#define SMI_CMD_C45 (0 << 12)
|
||||
#define SMI_CMD_C45_ADDR (0 << 10)
|
||||
#define SMI_CMD_C45_WRITE (1 << 10)
|
||||
#define SMI_CMD_C45_READ (3 << 10)
|
||||
#define SMI_CMD_OP_C45_ADDR \
|
||||
(SMI_CMD_C45_ADDR | SMI_CMD_BUSY | SMI_CMD_C45)
|
||||
#define SMI_CMD_OP_C45_WRITE \
|
||||
(SMI_CMD_C45_WRITE | SMI_CMD_BUSY | SMI_CMD_C45)
|
||||
#define SMI_CMD_OP_C45_READ \
|
||||
(SMI_CMD_C45_READ | SMI_CMD_BUSY | SMI_CMD_C45)
|
||||
#define SMI_CMD_DEV_ADDR 5
|
||||
#define SMI_CMD_DEV_ADDR_MASK 0x3e0
|
||||
#define SMI_CMD_REG_ADDR_MASK 0x1f
|
||||
#define SMI_PHY_DATA_REG 0x19
|
||||
#define PHY_DATA_MASK 0xffff
|
||||
|
||||
#define PHY_PAGE_REG 22
|
||||
#define PHY_PAGE_REG 22
|
||||
|
||||
/*
|
||||
* Scratch and Misc register accessed via
|
||||
* 'Switch Global Registers' (REG_GLOBAL2)
|
||||
*/
|
||||
#define SCR_AND_MISC_REG 0x1a
|
||||
#define SCR_AND_MISC_REG 0x1a
|
||||
|
||||
#define SCR_AND_MISC_PTR_CFG 0x7000
|
||||
#define SCR_AND_MISC_DATA_CFG_MASK 0xf0
|
||||
#define SCR_AND_MISC_PTR_CFG 0x7000
|
||||
#define SCR_AND_MISC_DATA_CFG_MASK 0xf0
|
||||
|
||||
#define E6000SW_NUM_PHY_REGS 29
|
||||
#define E6000SW_MAX_PORTS 8
|
||||
#define E6000SW_DEFAULT_AGETIME 20
|
||||
#define E6000SW_RETRIES 100
|
||||
#define E6000SW_SMI_TIMEOUT 16
|
||||
/* SERDES registers. */
|
||||
#define E6000SW_SERDES_DEV 4
|
||||
#define E6000SW_SERDES_PCS_CTL1 0x1000
|
||||
#define E6000SW_SERDES_SGMII_CTL 0x2000
|
||||
#define E6000SW_SERDES_PDOWN (1 << 11)
|
||||
|
||||
#define E6000SW_NUM_VLANS 128
|
||||
#define E6000SW_NUM_LAGMASK 8
|
||||
#define E6000SW_NUM_PHY_REGS 29
|
||||
#define E6000SW_MAX_PORTS 11
|
||||
#define E6000SW_DEFAULT_AGETIME 20
|
||||
#define E6000SW_RETRIES 100
|
||||
#define E6000SW_SMI_TIMEOUT 16
|
||||
|
||||
#endif /* _E6000SWREG_H_ */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user