Rename dcache_dma_preread() to dcache_inv_poc_dma() to make it clear that it
is a dcache invalidate to point of coherency just like dcache_inv_poc(), but a slightly different version specific to dma operations. Elaborate the comment about how and why it's different.
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@ -1284,7 +1284,7 @@ dma_preread_safe(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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if ((va + size) & cpuinfo.dcache_line_mask)
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dcache_wb_poc(va + size, pa + size, 1);
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dcache_dma_preread(va, pa, size);
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dcache_inv_poc_dma(va, pa, size);
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}
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static void
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@ -1406,7 +1406,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
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if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) {
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bpage = STAILQ_FIRST(&map->bpages);
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while (bpage != NULL) {
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dcache_dma_preread(bpage->vaddr, bpage->busaddr,
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dcache_inv_poc_dma(bpage->vaddr, bpage->busaddr,
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bpage->datacount);
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bpage = STAILQ_NEXT(bpage, links);
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}
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@ -471,15 +471,17 @@ dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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}
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/*
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* Discard D-cache lines to PoC, prior to overwrite by DMA engine
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* Discard D-cache lines to PoC, prior to overwrite by DMA engine.
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*
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* Invalidate caches, discarding data in dirty lines. This is useful
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* if the memory is about to be overwritten, e.g. by a DMA engine.
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* Invalidate caches from innermost to outermost to follow the flow
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* of dirty cachelines.
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* Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
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* flow into L1 while invalidating. This routine is intended to be used only
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* when invalidating a buffer before a DMA operation loads new data into memory.
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* The concern in this case is that dirty lines are not evicted to main memory,
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* overwriting the DMA data. For that reason, the L1 is done first to ensure
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* that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
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*/
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static __inline void
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dcache_dma_preread(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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vm_offset_t eva = va + size;
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