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x86 MCA: Enable AMD thresholding support on 17h

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17h supports MCA thresholding in the same way as 16h and earlier.
Supposedly a ScalableMca feature bit in CPUID 8000_0007:EBX must be set, but
that was not true for earlier models, so be careful about relying on it.

While here, document a missing bit in LS MCA MISC0.

Reviewed by:	truckman
Sponsored by:	Dell EMC Isilon
Differential Revision:	https://reviews.freebsd.org/D12237
This commit is contained in:
Conrad Meyer 2017-09-07 21:31:07 +00:00
parent cd8c258198
commit d848ecfb7e
2 changed files with 15 additions and 2 deletions
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1
sys/x86/include/specialreg.h
View File

@ -718,6 +718,7 @@
#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
#define MC_MISC_AMDNB_INTP 0x1000000000000000 /* Int. type can generate interrupts */
#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
#define MC_MISC_AMDNB_LVT_SHIFT 52
#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */

16
sys/x86/x86/mca.c
View File

@ -132,8 +132,20 @@ static int amd_elvt = -1;
static inline bool
amd_thresholding_supported(void)
{
return (cpu_vendor_id == CPU_VENDOR_AMD &&
CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16);
if (cpu_vendor_id != CPU_VENDOR_AMD)
return (false);
/*
* The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F).
*
* It begins to be documented in family 0x15 model 30 and family 0x16,
* but neither of these families documents the ScalableMca bit, which
* supposedly defines the presence of this feature on family 0x17.
*/
if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16)
return (true);
if (CPUID_TO_FAMILY(cpu_id) >= 0x17)
return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0);
return (false);
}
#endif