Synchronize with sys/i386/i386/microtime.s revision up to 1.29.
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@ -32,16 +32,13 @@
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* SUCH DAMAGE.
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*
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* from: Steve McCanne's microtime code
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* $Id: microtime.s,v 1.12 1997/07/20 11:56:48 kato Exp $
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* $Id: microtime.s,v 1.13 1997/07/21 13:12:45 kato Exp $
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*/
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#include "opt_cpu.h"
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#include <machine/asmacros.h>
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#ifdef APIC_IO
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#include <machine/smptests.h> /** NEW STRATEGY, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <machine/param.h>
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#include <i386/isa/icu.h>
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#ifdef PC98
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@ -118,21 +115,18 @@ ENTRY(microtime)
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movl _timer0_max_count, %edx /* prepare for 2 uses */
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#ifdef APIC_IO
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#ifdef NEW_STRATEGY
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#if defined(REAL_MCPL) /* XXX do we need this??? */
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pushl %ecx /* s_lock destroys %eax, %ecx */
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CPL_LOCK /* MP-safe, INTs disabled above */
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popl %ecx /* restore %ecx */
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movl _ipending, %eax
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movl $0, _cpl_lock /* s_unlock would destroy %eax */
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testl %eax, _mask8254 /* is soft timer interrupt pending? */
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#else /* REAL_MCPL */
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/** XXX FIXME: take our chances with a race, is this OK? */
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movl _ipending, %eax
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testl %eax, _mask8254 /* is soft timer interrupt pending? */
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#else /** NEW_STRATEGY */
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#ifdef APIC_PIN0_TIMER
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testl $IRQ0, _ipending /* is soft timer interrupt pending? */
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#else
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movl _ipending, %eax
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testl %eax, _mask8254 /* is soft timer interrupt pending? */
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#endif /* APIC_PIN0_TIMER */
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#endif /** NEW_STRATEGY */
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#endif /* REAL_MCPL */
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#else
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testb $IRQ0, _ipending /* is soft timer interrupt pending? */
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#endif /* APIC_IO */
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@ -143,21 +137,8 @@ ENTRY(microtime)
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jbe 1f
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#ifdef APIC_IO
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#ifdef NEW_STRATEGY
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movl lapic_irr1, %eax /** XXX assumption: IRQ0-24 */
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testl %eax, _mask8254 /* is hard timer interrupt pending? */
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#else /** NEW_STRATEGY */
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#ifdef APIC_PIN0_TIMER
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testl $IRQ0, lapic_irr1
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#else
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movl lapic_irr1, %eax /** XXX assumption: IRQ0-24 */
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testl %eax, _mask8254 /* is hard timer interrupt pending? */
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#endif /* APIC_PIN0_TIMER */
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#endif /** NEW_STRATEGY */
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#else
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inb $IO_ICU1, %al /* read IRR in ICU */
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testb $IRQ0, %al /* is hard timer interrupt pending? */
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