Convert #defines to enums so that the values are visible in the debugger.
Requested by: gibbs MFC after: 2 weeks
This commit is contained in:
George V. Neville-Neil
parent
e6c8bc291a
commit
d9168b014f
@ -62,80 +62,101 @@
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/* Table 3.1 Two-wire interface ID: Data Fields */
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#define SFF_8472_BASE 0xa0 /* Base address for all our queries. */
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#define SFF_8472_ID 0 /* Transceiver Type (Table 3.2) */
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#define SFF_8472_EXT_ID 1 /* Extended transceiver type (Table 3.3) */
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#define SFF_8472_CONNECTOR 2 /* Connector type (Table 3.4) */
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#define SFF_8472_TRANS_START 3 /* Elec or Optical Compatibility
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enum {
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SFF_8472_BASE = 0xa0, /* Base address for all our queries. */
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SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */
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SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */
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SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */
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SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility
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* (Table 3.5) */
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#define SFF_8472_TRANS_END 10
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#define SFF_8472_ENCODING 11 /* Encoding Code for high speed
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* serial encoding algorithm (see
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* Table 3.6) */
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#define SFF_8472_BITRATE 12 /* Nominal signaling rate, units
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* of 100MBd. (see details for
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* rates > 25.0Gb/s) */
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#define SFF_8472_RATEID 13 /* Type of rate select
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* functionality (see Table
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* 3.6a) */
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#define SFF_8472_LEN_SMF_KM 14 /* Link length supported for single
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SFF_8472_TRANS_END = 10,
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SFF_8472_ENCODING = 11, /* Encoding Code for high speed
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* serial encoding algorithm (see
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* Table 3.6) */
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SFF_8472_BITRATE = 12, /* Nominal signaling rate, units
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* of 100MBd. (see details for
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* rates > 25.0Gb/s) */
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SFF_8472_RATEID = 13, /* Type of rate select
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* functionality (see Table
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* 3.6a) */
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SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single
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* mode fiber, units of km */
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#define SFF_8472_LEN_SMF 15 /* Link length supported for single
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SFF_8472_LEN_SMF = 15, /* Link length supported for single
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* mode fiber, units of 100 m */
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#define SFF_8472_LEN_50UM 16 /* Link length supported for 50 um
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SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um
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* OM2 fiber, units of 10 m */
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#define SFF_8472_LEN_625UM 17 /* Link length supported for 62.5
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SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5
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* um OM1 fiber, units of 10 m */
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#define SFF_8472_LEN_OM4 18 /* Link length supported for 50um
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SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um
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* OM4 fiber, units of 10m.
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* Alternatively copper or direct
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* attach cable, units of m */
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#define SFF_8472_LEN_OM3 19 /* Link length supported for 50 um OM3 fiber, units of 10 m */
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#define SFF_8472_VENDOR_START 20 /* Vendor name [Address A0h, Bytes
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SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */
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SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes
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* 20-35] */
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#define SFF_8472_VENDOR_END 35
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#define SFF_8472_TRANS 36 /* Transceiver Code for electronic
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SFF_8472_VENDOR_END = 35,
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SFF_8472_TRANS = 36, /* Transceiver Code for electronic
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* or optical compatibility (see
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* Table 3.5) */
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#define SFF_8472_VENDOR_OUI_START 37 /* Vendor OUI SFP vendor IEEE
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SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE
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* company ID */
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#define SFF_8472_VENDOR_OUI_END 39
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#define SFF_8472_PN_START 40 /* Vendor PN */
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#define SFF_8472_PN_END 55
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#define SFF_8472_REV_START 56 /* Vendor Revision */
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#define SFF_8472_REV_END 59
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#define SFF_8472_WAVELEN_START 60 /* Wavelength Laser wavelength
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SFF_8472_VENDOR_OUI_END = 39,
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SFF_8472_PN_START = 40, /* Vendor PN */
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SFF_8472_PN_END = 55,
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SFF_8472_REV_START = 56, /* Vendor Revision */
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SFF_8472_REV_END = 59,
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SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength
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* (Passive/Active Cable
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* Specification Compliance) */
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#define SFF_8472_WAVELEN_END 61
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#define SFF_8472_CC_BASE 63 /* CC_BASE Check code for Base ID
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SFF_8472_WAVELEN_END = 61,
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SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID
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* Fields (addresses 0 to 62) */
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/*
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* Extension Fields (optional) check the options before reading other
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* addresses.
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*/
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#define SFF_8472_OPTIONS_MSB 64 /* Options Indicates which optional
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SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional
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* transceiver signals are
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* implemented */
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#define SFF_8472_OPTIONS_LSB 65 /* (see Table 3.7) */
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#define SFF_8472_BR_MAX 66 /* BR max Upper bit rate margin,
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SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */
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SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin,
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* units of % (see details for
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* rates > 25.0Gb/s) */
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#define SFF_8472_BR_MIN 67 /* Lower bit rate margin, units of
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SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of
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* % (see details for rates >
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* 25.0Gb/s) */
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#define SFF_8472_SN_START 68 /* Vendor SN [Address A0h, Bytes 68-83] */
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#define SFF_8472_SN_END 83
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#define SFF_8472_DATE_START 84 /* Date code Vendor’s manufacturing
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SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */
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SFF_8472_SN_END = 83,
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SFF_8472_DATE_START = 84, /* Date code Vendor’s manufacturing
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* date code (see Table 3.8) */
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#define SFF_8472_DATE_END 91
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#define SFF_8472_DIAG_TYPE 92 /* Diagnostic Monitoring Type
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SFF_8472_DATE_END = 91,
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SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type
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* Indicates which type of
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* diagnostic monitoring is
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* implemented (if any) in the
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* transceiver (see Table 3.9)
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*/
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SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which
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* optional enhanced features are
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* implemented (if any) in the
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* transceiver (see Table 3.10) */
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SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates
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* which revision of SFF-8472 the
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* transceiver complies with. (see
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* Table 3.12)*/
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SFF_8472_CC_EXT = 95, /* Check code for the Extended ID
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* Fields (addresses 64 to 94)
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*/
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SFF_8472_VENDOR_RSRVD_START = 96,
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SFF_8472_VENDOR_RSRVD_END = 127,
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SFF_8472_RESERVED_START = 128,
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SFF_8472_RESERVED_END = 255
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};
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#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
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#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
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#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
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@ -143,101 +164,84 @@
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#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
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* See SFF-8472 doc. */
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#define SFF_8472_ENHANCED 93 /* Enhanced Options Indicates which
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* optional enhanced features are
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* implemented (if any) in the
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* transceiver (see Table 3.10) */
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#define SFF_8472_COMPLIANCE 94 /* SFF-8472 Compliance Indicates
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* which revision of SFF-8472 the
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* transceiver complies with. (see
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* Table 3.12)*/
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#define SFF_8472_CC_EXT 95 /* Check code for the Extended ID
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* Fields (addresses 64 to 94)
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*/
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#define SFF_8472_VENDOR_RSRVD_START 96
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#define SFF_8472_VENDOR_RSRVD_END 127
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#define SFF_8472_RESERVED_START 128
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#define SFF_8472_RESERVED_END 255
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/*
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* Diagnostics are available at the two wire address 0xa2. All
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* diagnostics are OPTIONAL so you should check 0xa0 registers 92 to
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* see which, if any are supported.
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*/
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#define SFF_8472_DIAG 0xa2 /* Base address for diagnostics. */
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enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */
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/*
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* Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
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* and MUST be read in a single read operation starting at the MSB
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*/
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#define SFF_8472_TEMP_HIGH_ALM 0 /* Temp High Alarm */
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#define SFF_8472_TEMP_LOW_ALM 2 /* Temp Low Alarm */
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#define SFF_8472_TEMP_HIGH_WARN 4 /* Temp High Warning */
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#define SFF_8472_TEMP_LOW_WARN 6 /* Temp Low Warning */
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#define SFF_8472_VOLTAGE_HIGH_ALM 8 /* Voltage High Alarm */
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#define SFF_8472_VOLTAGE_LOW_ALM 10 /* Voltage Low Alarm */
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#define SFF_8472_VOLTAGE_HIGH_WARN 12 /* Voltage High Warning */
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#define SFF_8472_VOLTAGE_LOW_WARN 14 /* Voltage Low Warning */
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#define SFF_8472_BIAS_HIGH_ALM 16 /* Bias High Alarm */
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#define SFF_8472_BIAS_LOW_ALM 18 /* Bias Low Alarm */
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#define SFF_8472_BIAS_HIGH_WARN 20 /* Bias High Warning */
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#define SFF_8472_BIAS_LOW_WARN 22 /* Bias Low Warning */
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#define SFF_8472_TX_POWER_HIGH_ALM 24 /* TX Power High Alarm */
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#define SFF_8472_TX_POWER_LOW_ALM 26 /* TX Power Low Alarm */
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#define SFF_8472_TX_POWER_HIGH_WARN 28 /* TX Power High Warning */
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#define SFF_8472_TX_POWER_LOW_WARN 30 /* TX Power Low Warning */
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#define SFF_8472_RX_POWER_HIGH_ALM 32 /* RX Power High Alarm */
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#define SFF_8472_RX_POWER_LOW_ALM 34 /* RX Power Low Alarm */
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#define SFF_8472_RX_POWER_HIGH_WARN 36 /* RX Power High Warning */
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#define SFF_8472_RX_POWER_LOW_WARN 38 /* RX Power Low Warning */
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enum {
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SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */
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SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */
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SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */
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SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */
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SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */
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SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */
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SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */
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SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */
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SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */
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SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */
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SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */
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SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */
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SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */
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SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */
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SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */
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SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */
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SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */
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SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */
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SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */
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SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */
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#define SFF_8472_RX_POWER4 56 /* Rx_PWR(4) Single precision
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SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision
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* floating point calibration data
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* - Rx optical power. Bit 7 of
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* byte 56 is MSB. Bit 0 of byte
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* 59 is LSB. Rx_PWR(4) should be
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* set to zero for “internally
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* calibrated” devices. */
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#define SFF_8472_RX_POWER3 60 /* Rx_PWR(3) Single precision
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SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision
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* floating point calibration data
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* - Rx optical power. Bit 7 of
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* byte 60 is MSB. Bit 0 of byte 63
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* is LSB. Rx_PWR(3) should be set
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* to zero for “internally
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* calibrated” devices.*/
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#define SFF_8472_RX_POWER2 64 /* Rx_PWR(2) Single precision
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SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision
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* floating point calibration data,
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* Rx optical power. Bit 7 of byte
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* 64 is MSB, bit 0 of byte 67 is
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* LSB. Rx_PWR(2) should be set to
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* zero for “internally calibrated”
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* devices. */
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#define SFF_8472_RX_POWER1 68 /* Rx_PWR(1) Single precision
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SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision
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* floating point calibration data,
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* Rx optical power. Bit 7 of byte
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* 68 is MSB, bit 0 of byte 71 is
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* LSB. Rx_PWR(1) should be set to
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* 1 for “internally calibrated”
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* devices. */
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#define SFF_8472_RX_POWER0 72 /* Rx_PWR(0) Single precision
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SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision
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* floating point calibration data,
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* Rx optical power. Bit 7 of byte
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* 72 is MSB, bit 0 of byte 75 is
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* LSB. Rx_PWR(0) should be set to
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* zero for “internally calibrated”
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* devices. */
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#define SFF_8472_TX_I_SLOPE 76 /* Tx_I(Slope) Fixed decimal
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SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal
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* (unsigned) calibration data,
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* laser bias current. Bit 7 of
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* byte 76 is MSB, bit 0 of byte 77
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* is LSB. Tx_I(Slope) should be
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* set to 1 for “internally
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* calibrated” devices. */
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#define SFF_8472_TX_I_OFFSET 78 /* Tx_I(Offset) Fixed decimal
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SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal
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* (signed two’s complement)
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* calibration data, laser bias
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* current. Bit 7 of byte 78 is
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@ -245,7 +249,7 @@
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* LSB. Tx_I(Offset) should be set
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* to zero for “internally
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* calibrated” devices. */
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#define SFF_8472_TX_POWER_SLOPE 80 /* Tx_PWR(Slope) Fixed decimal
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SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal
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* (unsigned) calibration data,
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* transmitter coupled output
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* power. Bit 7 of byte 80 is MSB,
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@ -253,22 +257,22 @@
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* Tx_PWR(Slope) should be set to 1
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* for “internally calibrated”
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* devices. */
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#define SFF_8472_TX_POWER_OFFSET 82 /* Tx_PWR(Offset) Fixed decimal
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* (signed two’s complement)
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* calibration data, transmitter
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* coupled output power. Bit 7 of
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* byte 82 is MSB, bit 0 of byte 83
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* is LSB. Tx_PWR(Offset) should be
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* set to zero for “internally
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* calibrated” devices. */
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#define SFF_8472_T_SLOPE 84 /* T (Slope) Fixed decimal
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SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal
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* (signed two’s complement)
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* calibration data, transmitter
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* coupled output power. Bit 7 of
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* byte 82 is MSB, bit 0 of byte 83
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* is LSB. Tx_PWR(Offset) should be
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* set to zero for “internally
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* calibrated” devices. */
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SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal
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* (unsigned) calibration data,
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* internal module temperature. Bit
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* 7 of byte 84 is MSB, bit 0 of
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* byte 85 is LSB. T(Slope) should
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* be set to 1 for “internally
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* calibrated” devices. */
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#define SFF_8472_T_OFFSET 86 /* T (Offset) Fixed decimal (signed
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SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed
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* two’s complement) calibration
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* data, internal module
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* temperature. Bit 7 of byte 86 is
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@ -276,7 +280,7 @@
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* T(Offset) should be set to zero
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* for “internally calibrated”
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* devices. */
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#define SFF_8472_V_SLOPE 88 /* V (Slope) Fixed decimal
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SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal
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* (unsigned) calibration data,
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* internal module supply
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* voltage. Bit 7 of byte 88 is
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@ -284,7 +288,7 @@
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* LSB. V(Slope) should be set to 1
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* for “internally calibrated”
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* devices. */
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#define SFF_8472_V_OFFSET 90 /* V (Offset) Fixed decimal (signed
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SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed
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* two’s complement) calibration
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* data, internal module supply
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* voltage. Bit 7 of byte 90 is
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@ -292,21 +296,21 @@
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* LSB. V(Offset) should be set to
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* zero for “internally calibrated”
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* devices. */
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#define SFF_8472_CHECKSUM 95 /* Checksum Byte 95 contains the
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SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the
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* low order 8 bits of the sum of
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* bytes 0 – 94. */
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/* Internal measurements. */
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/* Internal measurements. */
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#define SFF_8472_TEMP 96 /* Internally measured module temperature. */
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#define SFF_8472_VCC 98 /* Internally measured supply
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SFF_8472_TEMP = 96, /* Internally measured module temperature. */
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SFF_8472_VCC = 98, /* Internally measured supply
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* voltage in transceiver.
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*/
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#define SFF_8472_TX_BIAS 100 /* Internally measured TX Bias Current. */
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#define SFF_8472_TX_POWER 102 /* Measured TX output power. */
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#define SFF_8472_RX_POWER 104 /* Measured RX input power. */
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#define SFF_8472_STATUS 110 /* See below */
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SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */
|
||||
SFF_8472_TX_POWER = 102, /* Measured TX output power. */
|
||||
SFF_8472_RX_POWER = 104, /* Measured RX input power. */
|
||||
|
||||
SFF_8472_STATUS = 110 /* See below */
|
||||
};
|
||||
/* Status Bits Described */
|
||||
|
||||
/*
|
||||
@ -372,20 +376,22 @@
|
||||
#define SFF_8472_STATUS_DATA_READY (1 << 0)
|
||||
|
||||
/* Table 3.2 Identifier values */
|
||||
#define SFF_8472_ID_UNKNOWN 0x0 /* Unknown or unspecified */
|
||||
#define SFF_8472_ID_GBIC 0x1 /* GBIC */
|
||||
#define SFF_8472_ID_SFF 0x2 /* Module soldered to motherboard (ex: SFF)*/
|
||||
#define SFF_8472_ID_SFP 0x3 /* SFP or SFP “Plus” */
|
||||
#define SFF_8472_ID_XBI 0x4 /* Reserved for “300 pin XBI” devices */
|
||||
#define SFF_8472_ID_XENPAK 0x5 /* Reserved for “Xenpak” devices */
|
||||
#define SFF_8472_ID_XFP 0x6 /* Reserved for “XFP” devices */
|
||||
#define SFF_8472_ID_XFF 0x7 /* Reserved for “XFF” devices */
|
||||
#define SFF_8472_ID_XFPE 0x8 /* Reserved for “XFP-E” devices */
|
||||
#define SFF_8472_ID_XPAK 0x9 /* Reserved for “XPak” devices */
|
||||
#define SFF_8472_ID_X2 0xA /* Reserved for “X2” devices */
|
||||
#define SFF_8472_ID_DWDM_SFP 0xB /* Reserved for “DWDM-SFP” devices */
|
||||
#define SFF_8472_ID_QSFP 0xC /* Reserved for “QSFP” devices */
|
||||
#define SFF_8472_ID_LAST SFF_8472_ID_QSFP
|
||||
enum {
|
||||
SFF_8472_ID_UNKNOWN = 0x0, /* Unknown or unspecified */
|
||||
SFF_8472_ID_GBIC = 0x1, /* GBIC */
|
||||
SFF_8472_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/
|
||||
SFF_8472_ID_SFP = 0x3, /* SFP or SFP “Plus” */
|
||||
SFF_8472_ID_XBI = 0x4, /* Reserved for “300 pin XBI” devices */
|
||||
SFF_8472_ID_XENPAK = 0x5, /* Reserved for “Xenpak” devices */
|
||||
SFF_8472_ID_XFP = 0x6, /* Reserved for “XFP” devices */
|
||||
SFF_8472_ID_XFF = 0x7, /* Reserved for “XFF” devices */
|
||||
SFF_8472_ID_XFPE = 0x8, /* Reserved for “XFP-E” devices */
|
||||
SFF_8472_ID_XPAK = 0x9, /* Reserved for “XPak” devices */
|
||||
SFF_8472_ID_X2 = 0xA, /* Reserved for “X2” devices */
|
||||
SFF_8472_ID_DWDM_SFP = 0xB, /* Reserved for “DWDM-SFP” devices */
|
||||
SFF_8472_ID_QSFP = 0xC, /* Reserved for “QSFP” devices */
|
||||
SFF_8472_ID_LAST = SFF_8472_ID_QSFP
|
||||
};
|
||||
|
||||
static char *sff_8472_id[SFF_8472_ID_LAST + 1] = {"Unknown",
|
||||
"GBIC",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user