Initialization bugfixes and enhancements:
- Fix bug preventing adoption of running firmware - Set PCIe max read request size to 4KB - Read PCIe link width from config space - Assume aligned completions from the southbridge ports of intel E5000 chips - Use aligned firmware when link width is x4 or less - Add hw.mxge.force_firmware tunable to allow user to force selection of aligned (or unaligned) firmware
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c228248880
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@ -84,6 +84,7 @@ __FBSDID("$FreeBSD$");
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/* tunable params */
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static int mxge_nvidia_ecrc_enable = 1;
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static int mxge_force_firmware = 0;
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static int mxge_max_intr_slots = 1024;
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static int mxge_intr_coal_delay = 30;
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static int mxge_deassert_wait = 1;
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@ -403,6 +404,29 @@ mxge_select_firmware(mxge_softc_t *sc)
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device_t pdev;
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uint16_t pvend, pdid;
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if (mxge_force_firmware != 0) {
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if (mxge_force_firmware == 1)
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aligned = 1;
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else
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aligned = 0;
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if (mxge_verbose)
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device_printf(sc->dev,
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"Assuming %s completions (forced)\n",
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aligned ? "aligned" : "unaligned");
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goto abort;
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}
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/* if the PCIe link width is 4 or less, we can use the aligned
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firmware and skip any checks */
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if (sc->link_width != 0 && sc->link_width <= 4) {
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device_printf(sc->dev,
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"PCIe x%d Link, expect reduced performance\n",
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sc->link_width);
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aligned = 1;
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goto abort;
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}
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pdev = device_get_parent(device_get_parent(sc->dev));
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if (pdev == NULL) {
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device_printf(sc->dev, "could not find parent?\n");
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@ -428,8 +452,10 @@ mxge_select_firmware(mxge_softc_t *sc)
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provided aligned completions */
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if (/* HT2000 */ (pvend == 0x1166 && pdid == 0x0132) ||
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/* PLX */ (pvend == 0x10b5 && pdid == 0x8532) ||
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/* Intel */ (pvend == 0x8086 &&
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/* E5000 */(pdid >= 0x25f7 && pdid <= 0x25fa))) {
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/* Intel */ (pvend == 0x8086 &&
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/* E5000 NorthBridge*/((pdid >= 0x25f7 && pdid <= 0x25fa) ||
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/* E5000 SouthBridge*/ (pdid >= 0x3510 && pdid <= 0x351b)))) {
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aligned = 1;
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if (mxge_verbose)
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device_printf(sc->dev,
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"Assuming aligned completions "
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@ -722,7 +748,9 @@ mxge_load_firmware(mxge_softc_t *sc)
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"performance consider loading optimized "
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"firmware\n");
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}
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sc->fw_name = mxge_fw_unaligned;
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sc->tx.boundary = 2048;
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return 0;
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}
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/* clear confirmation addr */
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confirm = (volatile uint32_t *)sc->cmd;
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@ -1092,6 +1120,10 @@ mxge_add_sysctls(mxge_softc_t *sc)
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"product_code",
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CTLFLAG_RD, &sc->product_code_string,
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0, "product_code");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO,
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"pcie_link_width",
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CTLFLAG_RD, &sc->link_width,
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0, "tx_boundary");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO,
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"tx_boundary",
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CTLFLAG_RD, &sc->tx.boundary,
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@ -2669,6 +2701,8 @@ mxge_fetch_tunables(mxge_softc_t *sc)
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&mxge_intr_coal_delay);
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TUNABLE_INT_FETCH("hw.mxge.nvidia_ecrc_enable",
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&mxge_nvidia_ecrc_enable);
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TUNABLE_INT_FETCH("hw.mxge.force_firmware",
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&mxge_force_firmware);
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TUNABLE_INT_FETCH("hw.mxge.deassert_wait",
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&mxge_deassert_wait);
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TUNABLE_INT_FETCH("hw.mxge.verbose",
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@ -2687,8 +2721,8 @@ mxge_attach(device_t dev)
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mxge_softc_t *sc = device_get_softc(dev);
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struct ifnet *ifp;
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size_t bytes;
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int count, rid, err;
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uint16_t cmd;
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int count, rid, err, reg;
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uint16_t cmd, pectl, lnk;
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sc->dev = dev;
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mxge_fetch_tunables(sc);
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@ -2724,6 +2758,16 @@ mxge_attach(device_t dev)
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MTX_NETWORK_LOCK, MTX_DEF);
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sx_init(&sc->driver_lock, device_get_nameunit(dev));
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/* find the PCIe link width and set max read request to 4KB*/
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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lnk = pci_read_config(dev, reg + 0x12, 2);
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sc->link_width = (lnk >> 4) & 0x3f;
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pectl = pci_read_config(dev, reg + 0x8, 2);
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pectl = (pectl & ~0x7000) | (5 << 12);
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pci_write_config(dev, reg + 0x8, 2, pectl);
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}
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/* Enable DMA and Memory space access */
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pci_enable_busmaster(dev);
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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@ -2802,7 +2846,7 @@ mxge_attach(device_t dev)
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device_printf(dev, "could not alloc interrupt\n");
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goto abort_with_rx_done;
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}
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if (bootverbose)
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if (mxge_verbose)
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device_printf(dev, "using %s irq %ld\n",
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sc->msi_enabled ? "MSI" : "INTx",
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rman_get_start(sc->irq_res));
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@ -156,6 +156,7 @@ typedef struct {
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int write_dma;
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int read_write_dma;
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int fw_multicast_support;
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int link_width;
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char *mac_addr_string;
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char product_code_string[64];
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char serial_number_string[64];
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