Remove dead code. Code Cleanup. Improve clarity in debug messages

MFC after:5 days
This commit is contained in:
davidcs 2016-02-19 22:46:52 +00:00
parent 225a8e89c9
commit d95a4ea06f
4 changed files with 110 additions and 1064 deletions

File diff suppressed because it is too large Load Diff

View File

@ -320,13 +320,6 @@ struct bxe_device_type
#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
#define RX_BD_MAX (RX_BD_TOTAL - 1)
#if 0
#define NUM_RX_RINGS RX_BD_NUM_PAGES
#define NUM_RX_BD RX_BD_TOTAL
#define MAX_RX_BD RX_BD_MAX
#define MAX_RX_AVAIL RX_BD_USABLE
#endif
#define RX_BD_NEXT(x) \
((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
((x) + 3) : ((x) + 1))
@ -386,13 +379,6 @@ struct bxe_device_type
#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
#if 0
#define NUM_RCQ_RINGS RCQ_NUM_PAGES
#define NUM_RCQ_BD RCQ_TOTAL
#define MAX_RCQ_BD RCQ_MAX
#define MAX_RCQ_AVAIL RCQ_USABLE
#endif
/*
* dropless fc calculations for RCQs
* Number of RCQs should be as number of buffers in BRB:
@ -627,14 +613,6 @@ struct bxe_fastpath {
struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
bus_dmamap_t rx_tpa_info_mbuf_spare_map;
uint64_t rx_tpa_queue_used;
#if 0
bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
bus_dmamap_t rx_tpa_mbuf_spare_map;
struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
#endif
uint16_t *sb_index_values;
uint16_t *sb_running_index;
@ -688,16 +666,6 @@ struct bxe_fastpath {
uint16_t tx_bd_prod;
uint16_t tx_bd_cons;
#if 0
/* status block number in hardware */
uint8_t sb_id;
#define FP_SB_ID(fp) (fp->sb_id)
/* driver copy of the fastpath CSTORM/USTORM indices */
uint16_t fp_c_idx;
uint16_t fp_u_idx;
#endif
uint64_t sge_mask[RX_SGE_MASK_LEN];
uint16_t rx_sge_prod;
@ -964,19 +932,6 @@ struct bxe_fw_stats_data {
*/
struct bxe_slowpath {
#if 0
/*
* The cdu_context array MUST be the first element in this
* structure. It is used during the leading edge ramrod
* operation.
*/
union cdu_context context[MAX_CONTEXT];
/* Used as a DMA source for MAC configuration. */
struct mac_configuration_cmd mac_config;
struct mac_configuration_cmd mcast_config;
#endif
/* used by the DMAE command executer */
struct dmae_command dmae[MAX_DMAE_C];
@ -1754,10 +1709,6 @@ struct bxe_softc {
uint8_t dropless_fc;
#if 0
struct bxe_dma *t2;
#endif
/* total number of FW statistics requests */
uint8_t fw_stats_num;
/*
@ -1953,13 +1904,6 @@ void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
#if 0
#define bxe_fp(sc, nr, var) ((sc)->fp[nr].var)
#define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index])
#define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index])
#define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats)
#endif
#define REG_RD_DMAE(sc, offset, valp, len32) \
do { \
bxe_read_dmae(sc, offset, len32); \
@ -2487,12 +2431,6 @@ bxe_stats_id(struct bxe_fastpath *fp)
struct bxe_softc *sc = fp->sc;
if (!CHIP_IS_E1x(sc)) {
#if 0
/* there are special statistics counters for FCoE 136..140 */
if (IS_FCOE_FP(fp)) {
return (sc->cnic_base_cl_id + (sc->pf_num >> 1));
}
#endif
return (fp->cl_id);
}

View File

@ -1558,23 +1558,6 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
#if 0
/**** FCoE FW statistics data ****/
if (!NO_FCOE(sc)) {
cur_data_offset = (sc->fw_stats_data_mapping +
offsetof(struct bxe_fw_stats_data, fcoe));
cur_query_entry = &sc->fw_stats_req->query[BXE_FCOE_QUERY_IDX];
cur_query_entry->kind = STATS_TYPE_FCOE;
/* For FCoE query index is a DONT CARE */
cur_query_entry->index = SC_PORT(sc);
cur_query_entry->funcID = cpu_to_le16(SC_FUNC(sc));
cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
}
#endif
/**** Clients' queries ****/
cur_data_offset = (sc->fw_stats_data_mapping +
offsetof(struct bxe_fw_stats_data, queue_stats));
@ -1583,12 +1566,7 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
* First queue query index depends whether FCoE offloaded request will
* be included in the ramrod
*/
#if 0
if (!NO_FCOE(sc))
first_queue_query_index = BXE_FIRST_QUEUE_QUERY_IDX;
else
#endif
first_queue_query_index = (BXE_FIRST_QUEUE_QUERY_IDX - 1);
first_queue_query_index = (BXE_FIRST_QUEUE_QUERY_IDX - 1);
for (i = 0; i < sc->num_queues; i++) {
cur_query_entry =
@ -1602,20 +1580,6 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
cur_data_offset += sizeof(struct per_queue_stats);
}
#if 0
/* add FCoE queue query if needed */
if (!NO_FCOE(sc)) {
cur_query_entry =
&sc->fw_stats_req->query[first_queue_query_index + i];
cur_query_entry->kind = STATS_TYPE_QUEUE;
cur_query_entry->index = bxe_stats_id(&sc->fp[FCOE_IDX(sc)]);
cur_query_entry->funcID = htole16(SC_FUNC(sc));
cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
}
#endif
}
void
@ -1757,22 +1721,6 @@ bxe_afex_collect_stats(struct bxe_softc *sc,
int i;
struct afex_stats *afex_stats = (struct afex_stats *)void_afex_stats;
struct bxe_eth_stats *estats = &sc->eth_stats;
#if 0
struct per_queue_stats *fcoe_q_stats =
&sc->fw_stats_data->queue_stats[FCOE_IDX(sc)];
struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
&fcoe_q_stats->tstorm_queue_statistics;
struct ustorm_per_queue_stats *fcoe_q_ustorm_stats =
&fcoe_q_stats->ustorm_queue_statistics;
struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
&fcoe_q_stats->xstorm_queue_statistics;
struct fcoe_statistics_params *fw_fcoe_stat =
&sc->fw_stats_data->fcoe;
#endif
memset(afex_stats, 0, sizeof(struct afex_stats));
@ -1869,144 +1817,6 @@ bxe_afex_collect_stats(struct bxe_softc *sc,
qstats->total_transmitted_dropped_packets_error_lo);
}
#if 0
/*
* Now add FCoE statistics which are collected separately
* (both offloaded and non offloaded)
*/
if (!NO_FCOE(sc)) {
ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
LE32_0,
afex_stats->rx_unicast_bytes_lo,
fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
afex_stats->rx_unicast_bytes_lo,
fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
ADD_64_LE(afex_stats->rx_broadcast_bytes_hi,
fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
afex_stats->rx_broadcast_bytes_lo,
fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
ADD_64_LE(afex_stats->rx_multicast_bytes_hi,
fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
afex_stats->rx_multicast_bytes_lo,
fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
ADD_64_LE(afex_stats->rx_unicast_frames_hi,
LE32_0,
afex_stats->rx_unicast_frames_lo,
fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
ADD_64_LE(afex_stats->rx_unicast_frames_hi,
LE32_0,
afex_stats->rx_unicast_frames_lo,
fcoe_q_tstorm_stats->rcv_ucast_pkts);
ADD_64_LE(afex_stats->rx_broadcast_frames_hi,
LE32_0,
afex_stats->rx_broadcast_frames_lo,
fcoe_q_tstorm_stats->rcv_bcast_pkts);
ADD_64_LE(afex_stats->rx_multicast_frames_hi,
LE32_0,
afex_stats->rx_multicast_frames_lo,
fcoe_q_tstorm_stats->rcv_ucast_pkts);
ADD_64_LE(afex_stats->rx_frames_discarded_hi,
LE32_0,
afex_stats->rx_frames_discarded_lo,
fcoe_q_tstorm_stats->checksum_discard);
ADD_64_LE(afex_stats->rx_frames_discarded_hi,
LE32_0,
afex_stats->rx_frames_discarded_lo,
fcoe_q_tstorm_stats->pkts_too_big_discard);
ADD_64_LE(afex_stats->rx_frames_discarded_hi,
LE32_0,
afex_stats->rx_frames_discarded_lo,
fcoe_q_tstorm_stats->ttl0_discard);
ADD_64_LE16(afex_stats->rx_frames_dropped_hi,
LE16_0,
afex_stats->rx_frames_dropped_lo,
fcoe_q_tstorm_stats->no_buff_discard);
ADD_64_LE(afex_stats->rx_frames_dropped_hi,
LE32_0,
afex_stats->rx_frames_dropped_lo,
fcoe_q_ustorm_stats->ucast_no_buff_pkts);
ADD_64_LE(afex_stats->rx_frames_dropped_hi,
LE32_0,
afex_stats->rx_frames_dropped_lo,
fcoe_q_ustorm_stats->mcast_no_buff_pkts);
ADD_64_LE(afex_stats->rx_frames_dropped_hi,
LE32_0,
afex_stats->rx_frames_dropped_lo,
fcoe_q_ustorm_stats->bcast_no_buff_pkts);
ADD_64_LE(afex_stats->rx_frames_dropped_hi,
LE32_0,
afex_stats->rx_frames_dropped_lo,
fw_fcoe_stat->rx_stat1.fcoe_rx_drop_pkt_cnt);
ADD_64_LE(afex_stats->rx_frames_dropped_hi,
LE32_0,
afex_stats->rx_frames_dropped_lo,
fw_fcoe_stat->rx_stat2.fcoe_rx_drop_pkt_cnt);
ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
LE32_0,
afex_stats->tx_unicast_bytes_lo,
fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
afex_stats->tx_unicast_bytes_lo,
fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
ADD_64_LE(afex_stats->tx_broadcast_bytes_hi,
fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
afex_stats->tx_broadcast_bytes_lo,
fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
ADD_64_LE(afex_stats->tx_multicast_bytes_hi,
fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
afex_stats->tx_multicast_bytes_lo,
fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
ADD_64_LE(afex_stats->tx_unicast_frames_hi,
LE32_0,
afex_stats->tx_unicast_frames_lo,
fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
ADD_64_LE(afex_stats->tx_unicast_frames_hi,
LE32_0,
afex_stats->tx_unicast_frames_lo,
fcoe_q_xstorm_stats->ucast_pkts_sent);
ADD_64_LE(afex_stats->tx_broadcast_frames_hi,
LE32_0,
afex_stats->tx_broadcast_frames_lo,
fcoe_q_xstorm_stats->bcast_pkts_sent);
ADD_64_LE(afex_stats->tx_multicast_frames_hi,
LE32_0,
afex_stats->tx_multicast_frames_lo,
fcoe_q_xstorm_stats->mcast_pkts_sent);
ADD_64_LE(afex_stats->tx_frames_dropped_hi,
LE32_0,
afex_stats->tx_frames_dropped_lo,
fcoe_q_xstorm_stats->error_drop_pkts);
}
#endif
/*
* If port stats are requested, add them to the PMF
* stats, as anyway they will be accumulated by the

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@ -749,17 +749,10 @@ static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable)
for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
#if 0
if (enable)
reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
else
reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
#else
if (enable)
reg_val |= mcp_attn_ctl_regs[i].bits;
else
reg_val &= ~mcp_attn_ctl_regs[i].bits;
#endif
REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
}