Remove dead code. Code Cleanup. Improve clarity in debug messages
MFC after:5 days
This commit is contained in:
parent
225a8e89c9
commit
d95a4ea06f
File diff suppressed because it is too large
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@ -320,13 +320,6 @@ struct bxe_device_type
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#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
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#define RX_BD_MAX (RX_BD_TOTAL - 1)
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#if 0
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#define NUM_RX_RINGS RX_BD_NUM_PAGES
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#define NUM_RX_BD RX_BD_TOTAL
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#define MAX_RX_BD RX_BD_MAX
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#define MAX_RX_AVAIL RX_BD_USABLE
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#endif
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#define RX_BD_NEXT(x) \
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((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
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((x) + 3) : ((x) + 1))
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@ -386,13 +379,6 @@ struct bxe_device_type
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#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
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#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
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#if 0
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#define NUM_RCQ_RINGS RCQ_NUM_PAGES
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#define NUM_RCQ_BD RCQ_TOTAL
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#define MAX_RCQ_BD RCQ_MAX
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#define MAX_RCQ_AVAIL RCQ_USABLE
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#endif
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/*
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* dropless fc calculations for RCQs
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* Number of RCQs should be as number of buffers in BRB:
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@ -627,14 +613,6 @@ struct bxe_fastpath {
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struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
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bus_dmamap_t rx_tpa_info_mbuf_spare_map;
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uint64_t rx_tpa_queue_used;
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#if 0
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bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
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bus_dmamap_t rx_tpa_mbuf_spare_map;
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struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
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bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
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uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
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#endif
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uint16_t *sb_index_values;
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uint16_t *sb_running_index;
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@ -688,16 +666,6 @@ struct bxe_fastpath {
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uint16_t tx_bd_prod;
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uint16_t tx_bd_cons;
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#if 0
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/* status block number in hardware */
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uint8_t sb_id;
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#define FP_SB_ID(fp) (fp->sb_id)
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/* driver copy of the fastpath CSTORM/USTORM indices */
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uint16_t fp_c_idx;
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uint16_t fp_u_idx;
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#endif
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uint64_t sge_mask[RX_SGE_MASK_LEN];
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uint16_t rx_sge_prod;
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@ -964,19 +932,6 @@ struct bxe_fw_stats_data {
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*/
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struct bxe_slowpath {
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#if 0
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/*
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* The cdu_context array MUST be the first element in this
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* structure. It is used during the leading edge ramrod
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* operation.
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*/
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union cdu_context context[MAX_CONTEXT];
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/* Used as a DMA source for MAC configuration. */
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struct mac_configuration_cmd mac_config;
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struct mac_configuration_cmd mcast_config;
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#endif
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/* used by the DMAE command executer */
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struct dmae_command dmae[MAX_DMAE_C];
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@ -1754,10 +1709,6 @@ struct bxe_softc {
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uint8_t dropless_fc;
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#if 0
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struct bxe_dma *t2;
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#endif
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/* total number of FW statistics requests */
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uint8_t fw_stats_num;
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/*
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@ -1953,13 +1904,6 @@ void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
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#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
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#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
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#if 0
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#define bxe_fp(sc, nr, var) ((sc)->fp[nr].var)
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#define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index])
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#define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index])
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#define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats)
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#endif
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#define REG_RD_DMAE(sc, offset, valp, len32) \
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do { \
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bxe_read_dmae(sc, offset, len32); \
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@ -2487,12 +2431,6 @@ bxe_stats_id(struct bxe_fastpath *fp)
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struct bxe_softc *sc = fp->sc;
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if (!CHIP_IS_E1x(sc)) {
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#if 0
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/* there are special statistics counters for FCoE 136..140 */
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if (IS_FCOE_FP(fp)) {
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return (sc->cnic_base_cl_id + (sc->pf_num >> 1));
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}
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#endif
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return (fp->cl_id);
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}
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@ -1558,23 +1558,6 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
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cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
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cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
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#if 0
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/**** FCoE FW statistics data ****/
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if (!NO_FCOE(sc)) {
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cur_data_offset = (sc->fw_stats_data_mapping +
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offsetof(struct bxe_fw_stats_data, fcoe));
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cur_query_entry = &sc->fw_stats_req->query[BXE_FCOE_QUERY_IDX];
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cur_query_entry->kind = STATS_TYPE_FCOE;
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/* For FCoE query index is a DONT CARE */
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cur_query_entry->index = SC_PORT(sc);
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cur_query_entry->funcID = cpu_to_le16(SC_FUNC(sc));
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cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
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cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
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}
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#endif
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/**** Clients' queries ****/
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cur_data_offset = (sc->fw_stats_data_mapping +
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offsetof(struct bxe_fw_stats_data, queue_stats));
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@ -1583,12 +1566,7 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
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* First queue query index depends whether FCoE offloaded request will
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* be included in the ramrod
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*/
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#if 0
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if (!NO_FCOE(sc))
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first_queue_query_index = BXE_FIRST_QUEUE_QUERY_IDX;
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else
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#endif
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first_queue_query_index = (BXE_FIRST_QUEUE_QUERY_IDX - 1);
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first_queue_query_index = (BXE_FIRST_QUEUE_QUERY_IDX - 1);
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for (i = 0; i < sc->num_queues; i++) {
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cur_query_entry =
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@ -1602,20 +1580,6 @@ bxe_prep_fw_stats_req(struct bxe_softc *sc)
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cur_data_offset += sizeof(struct per_queue_stats);
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}
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#if 0
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/* add FCoE queue query if needed */
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if (!NO_FCOE(sc)) {
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cur_query_entry =
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&sc->fw_stats_req->query[first_queue_query_index + i];
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cur_query_entry->kind = STATS_TYPE_QUEUE;
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cur_query_entry->index = bxe_stats_id(&sc->fp[FCOE_IDX(sc)]);
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cur_query_entry->funcID = htole16(SC_FUNC(sc));
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cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
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cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
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}
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#endif
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}
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void
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@ -1757,22 +1721,6 @@ bxe_afex_collect_stats(struct bxe_softc *sc,
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int i;
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struct afex_stats *afex_stats = (struct afex_stats *)void_afex_stats;
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struct bxe_eth_stats *estats = &sc->eth_stats;
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#if 0
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struct per_queue_stats *fcoe_q_stats =
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&sc->fw_stats_data->queue_stats[FCOE_IDX(sc)];
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struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
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&fcoe_q_stats->tstorm_queue_statistics;
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struct ustorm_per_queue_stats *fcoe_q_ustorm_stats =
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&fcoe_q_stats->ustorm_queue_statistics;
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struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
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&fcoe_q_stats->xstorm_queue_statistics;
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struct fcoe_statistics_params *fw_fcoe_stat =
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&sc->fw_stats_data->fcoe;
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#endif
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memset(afex_stats, 0, sizeof(struct afex_stats));
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@ -1869,144 +1817,6 @@ bxe_afex_collect_stats(struct bxe_softc *sc,
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qstats->total_transmitted_dropped_packets_error_lo);
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}
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#if 0
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/*
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* Now add FCoE statistics which are collected separately
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* (both offloaded and non offloaded)
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*/
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if (!NO_FCOE(sc)) {
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ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
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LE32_0,
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afex_stats->rx_unicast_bytes_lo,
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fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
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ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
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fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
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afex_stats->rx_unicast_bytes_lo,
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fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
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ADD_64_LE(afex_stats->rx_broadcast_bytes_hi,
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fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
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afex_stats->rx_broadcast_bytes_lo,
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fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
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ADD_64_LE(afex_stats->rx_multicast_bytes_hi,
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fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
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afex_stats->rx_multicast_bytes_lo,
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fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
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ADD_64_LE(afex_stats->rx_unicast_frames_hi,
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LE32_0,
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afex_stats->rx_unicast_frames_lo,
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fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
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ADD_64_LE(afex_stats->rx_unicast_frames_hi,
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LE32_0,
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afex_stats->rx_unicast_frames_lo,
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fcoe_q_tstorm_stats->rcv_ucast_pkts);
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ADD_64_LE(afex_stats->rx_broadcast_frames_hi,
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LE32_0,
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afex_stats->rx_broadcast_frames_lo,
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fcoe_q_tstorm_stats->rcv_bcast_pkts);
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ADD_64_LE(afex_stats->rx_multicast_frames_hi,
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LE32_0,
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afex_stats->rx_multicast_frames_lo,
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fcoe_q_tstorm_stats->rcv_ucast_pkts);
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ADD_64_LE(afex_stats->rx_frames_discarded_hi,
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LE32_0,
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afex_stats->rx_frames_discarded_lo,
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fcoe_q_tstorm_stats->checksum_discard);
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ADD_64_LE(afex_stats->rx_frames_discarded_hi,
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LE32_0,
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afex_stats->rx_frames_discarded_lo,
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fcoe_q_tstorm_stats->pkts_too_big_discard);
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ADD_64_LE(afex_stats->rx_frames_discarded_hi,
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LE32_0,
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afex_stats->rx_frames_discarded_lo,
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fcoe_q_tstorm_stats->ttl0_discard);
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ADD_64_LE16(afex_stats->rx_frames_dropped_hi,
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LE16_0,
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afex_stats->rx_frames_dropped_lo,
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fcoe_q_tstorm_stats->no_buff_discard);
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ADD_64_LE(afex_stats->rx_frames_dropped_hi,
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LE32_0,
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afex_stats->rx_frames_dropped_lo,
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fcoe_q_ustorm_stats->ucast_no_buff_pkts);
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ADD_64_LE(afex_stats->rx_frames_dropped_hi,
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LE32_0,
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afex_stats->rx_frames_dropped_lo,
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fcoe_q_ustorm_stats->mcast_no_buff_pkts);
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ADD_64_LE(afex_stats->rx_frames_dropped_hi,
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LE32_0,
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afex_stats->rx_frames_dropped_lo,
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fcoe_q_ustorm_stats->bcast_no_buff_pkts);
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ADD_64_LE(afex_stats->rx_frames_dropped_hi,
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LE32_0,
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afex_stats->rx_frames_dropped_lo,
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fw_fcoe_stat->rx_stat1.fcoe_rx_drop_pkt_cnt);
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ADD_64_LE(afex_stats->rx_frames_dropped_hi,
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LE32_0,
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afex_stats->rx_frames_dropped_lo,
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fw_fcoe_stat->rx_stat2.fcoe_rx_drop_pkt_cnt);
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ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
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LE32_0,
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afex_stats->tx_unicast_bytes_lo,
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fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
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ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
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fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
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afex_stats->tx_unicast_bytes_lo,
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fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
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ADD_64_LE(afex_stats->tx_broadcast_bytes_hi,
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fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
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afex_stats->tx_broadcast_bytes_lo,
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fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
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ADD_64_LE(afex_stats->tx_multicast_bytes_hi,
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fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
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afex_stats->tx_multicast_bytes_lo,
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fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
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ADD_64_LE(afex_stats->tx_unicast_frames_hi,
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LE32_0,
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afex_stats->tx_unicast_frames_lo,
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fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
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ADD_64_LE(afex_stats->tx_unicast_frames_hi,
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LE32_0,
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afex_stats->tx_unicast_frames_lo,
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fcoe_q_xstorm_stats->ucast_pkts_sent);
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ADD_64_LE(afex_stats->tx_broadcast_frames_hi,
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LE32_0,
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afex_stats->tx_broadcast_frames_lo,
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fcoe_q_xstorm_stats->bcast_pkts_sent);
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ADD_64_LE(afex_stats->tx_multicast_frames_hi,
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LE32_0,
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afex_stats->tx_multicast_frames_lo,
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fcoe_q_xstorm_stats->mcast_pkts_sent);
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ADD_64_LE(afex_stats->tx_frames_dropped_hi,
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LE32_0,
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afex_stats->tx_frames_dropped_lo,
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fcoe_q_xstorm_stats->error_drop_pkts);
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}
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#endif
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/*
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* If port stats are requested, add them to the PMF
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* stats, as anyway they will be accumulated by the
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@ -749,17 +749,10 @@ static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable)
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for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
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reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
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#if 0
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if (enable)
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reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
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else
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reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
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#else
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if (enable)
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reg_val |= mcp_attn_ctl_regs[i].bits;
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else
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reg_val &= ~mcp_attn_ctl_regs[i].bits;
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#endif
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REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
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}
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